sdhci.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <mmc.h>
  13. #include <sdhci.h>
  14. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  15. void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  16. #else
  17. void *aligned_buffer;
  18. #endif
  19. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  20. {
  21. unsigned long timeout;
  22. /* Wait max 100 ms */
  23. timeout = 100;
  24. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  25. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  26. if (timeout == 0) {
  27. printf("%s: Reset 0x%x never completed.\n",
  28. __func__, (int)mask);
  29. return;
  30. }
  31. timeout--;
  32. udelay(1000);
  33. }
  34. }
  35. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  36. {
  37. int i;
  38. if (cmd->resp_type & MMC_RSP_136) {
  39. /* CRC is stripped so we need to do some shifting. */
  40. for (i = 0; i < 4; i++) {
  41. cmd->response[i] = sdhci_readl(host,
  42. SDHCI_RESPONSE + (3-i)*4) << 8;
  43. if (i != 3)
  44. cmd->response[i] |= sdhci_readb(host,
  45. SDHCI_RESPONSE + (3-i)*4-1);
  46. }
  47. } else {
  48. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  49. }
  50. }
  51. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  52. {
  53. int i;
  54. char *offs;
  55. for (i = 0; i < data->blocksize; i += 4) {
  56. offs = data->dest + i;
  57. if (data->flags == MMC_DATA_READ)
  58. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  59. else
  60. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  61. }
  62. }
  63. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  64. unsigned int start_addr)
  65. {
  66. unsigned int stat, rdy, mask, timeout, block = 0;
  67. bool transfer_done = false;
  68. #ifdef CONFIG_MMC_SDHCI_SDMA
  69. unsigned char ctrl;
  70. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  71. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  72. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  73. #endif
  74. timeout = 1000000;
  75. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  76. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  77. do {
  78. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  79. if (stat & SDHCI_INT_ERROR) {
  80. pr_debug("%s: Error detected in status(0x%X)!\n",
  81. __func__, stat);
  82. return -EIO;
  83. }
  84. if (!transfer_done && (stat & rdy)) {
  85. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  86. continue;
  87. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  88. sdhci_transfer_pio(host, data);
  89. data->dest += data->blocksize;
  90. if (++block >= data->blocks) {
  91. /* Keep looping until the SDHCI_INT_DATA_END is
  92. * cleared, even if we finished sending all the
  93. * blocks.
  94. */
  95. transfer_done = true;
  96. continue;
  97. }
  98. }
  99. #ifdef CONFIG_MMC_SDHCI_SDMA
  100. if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
  101. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  102. start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  103. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  104. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  105. }
  106. #endif
  107. if (timeout-- > 0)
  108. udelay(10);
  109. else {
  110. printf("%s: Transfer data timeout\n", __func__);
  111. return -ETIMEDOUT;
  112. }
  113. } while (!(stat & SDHCI_INT_DATA_END));
  114. return 0;
  115. }
  116. /*
  117. * No command will be sent by driver if card is busy, so driver must wait
  118. * for card ready state.
  119. * Every time when card is busy after timeout then (last) timeout value will be
  120. * increased twice but only if it doesn't exceed global defined maximum.
  121. * Each function call will use last timeout value.
  122. */
  123. #define SDHCI_CMD_MAX_TIMEOUT 3200
  124. #define SDHCI_CMD_DEFAULT_TIMEOUT 100
  125. #define SDHCI_READ_STATUS_TIMEOUT 1000
  126. #ifdef CONFIG_DM_MMC
  127. static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
  128. struct mmc_data *data)
  129. {
  130. struct mmc *mmc = mmc_get_mmc_dev(dev);
  131. #else
  132. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  133. struct mmc_data *data)
  134. {
  135. #endif
  136. struct sdhci_host *host = mmc->priv;
  137. unsigned int stat = 0;
  138. int ret = 0;
  139. int trans_bytes = 0, is_aligned = 1;
  140. u32 mask, flags, mode;
  141. unsigned int time = 0, start_addr = 0;
  142. int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
  143. ulong start = get_timer(0);
  144. /* Timeout unit - ms */
  145. static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
  146. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  147. /* We shouldn't wait for data inihibit for stop commands, even
  148. though they might use busy signaling */
  149. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  150. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  151. mask &= ~SDHCI_DATA_INHIBIT;
  152. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  153. if (time >= cmd_timeout) {
  154. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  155. if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
  156. cmd_timeout += cmd_timeout;
  157. printf("timeout increasing to: %u ms.\n",
  158. cmd_timeout);
  159. } else {
  160. puts("timeout.\n");
  161. return -ECOMM;
  162. }
  163. }
  164. time++;
  165. udelay(1000);
  166. }
  167. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  168. mask = SDHCI_INT_RESPONSE;
  169. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  170. mask = SDHCI_INT_DATA_AVAIL;
  171. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  172. flags = SDHCI_CMD_RESP_NONE;
  173. else if (cmd->resp_type & MMC_RSP_136)
  174. flags = SDHCI_CMD_RESP_LONG;
  175. else if (cmd->resp_type & MMC_RSP_BUSY) {
  176. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  177. if (data)
  178. mask |= SDHCI_INT_DATA_END;
  179. } else
  180. flags = SDHCI_CMD_RESP_SHORT;
  181. if (cmd->resp_type & MMC_RSP_CRC)
  182. flags |= SDHCI_CMD_CRC;
  183. if (cmd->resp_type & MMC_RSP_OPCODE)
  184. flags |= SDHCI_CMD_INDEX;
  185. if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  186. flags |= SDHCI_CMD_DATA;
  187. /* Set Transfer mode regarding to data flag */
  188. if (data) {
  189. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  190. mode = SDHCI_TRNS_BLK_CNT_EN;
  191. trans_bytes = data->blocks * data->blocksize;
  192. if (data->blocks > 1)
  193. mode |= SDHCI_TRNS_MULTI;
  194. if (data->flags == MMC_DATA_READ)
  195. mode |= SDHCI_TRNS_READ;
  196. #ifdef CONFIG_MMC_SDHCI_SDMA
  197. if (data->flags == MMC_DATA_READ)
  198. start_addr = (unsigned long)data->dest;
  199. else
  200. start_addr = (unsigned long)data->src;
  201. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  202. (start_addr & 0x7) != 0x0) {
  203. is_aligned = 0;
  204. start_addr = (unsigned long)aligned_buffer;
  205. if (data->flags != MMC_DATA_READ)
  206. memcpy(aligned_buffer, data->src, trans_bytes);
  207. }
  208. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  209. /*
  210. * Always use this bounce-buffer when
  211. * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
  212. */
  213. is_aligned = 0;
  214. start_addr = (unsigned long)aligned_buffer;
  215. if (data->flags != MMC_DATA_READ)
  216. memcpy(aligned_buffer, data->src, trans_bytes);
  217. #endif
  218. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  219. mode |= SDHCI_TRNS_DMA;
  220. #endif
  221. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  222. data->blocksize),
  223. SDHCI_BLOCK_SIZE);
  224. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  225. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  226. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  227. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  228. }
  229. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  230. #ifdef CONFIG_MMC_SDHCI_SDMA
  231. if (data) {
  232. trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
  233. flush_cache(start_addr, trans_bytes);
  234. }
  235. #endif
  236. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  237. start = get_timer(0);
  238. do {
  239. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  240. if (stat & SDHCI_INT_ERROR)
  241. break;
  242. if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
  243. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
  244. return 0;
  245. } else {
  246. printf("%s: Timeout for status update!\n",
  247. __func__);
  248. return -ETIMEDOUT;
  249. }
  250. }
  251. } while ((stat & mask) != mask);
  252. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  253. sdhci_cmd_done(host, cmd);
  254. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  255. } else
  256. ret = -1;
  257. if (!ret && data)
  258. ret = sdhci_transfer_data(host, data, start_addr);
  259. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  260. udelay(1000);
  261. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  262. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  263. if (!ret) {
  264. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  265. !is_aligned && (data->flags == MMC_DATA_READ))
  266. memcpy(data->dest, aligned_buffer, trans_bytes);
  267. return 0;
  268. }
  269. sdhci_reset(host, SDHCI_RESET_CMD);
  270. sdhci_reset(host, SDHCI_RESET_DATA);
  271. if (stat & SDHCI_INT_TIMEOUT)
  272. return -ETIMEDOUT;
  273. else
  274. return -ECOMM;
  275. }
  276. #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  277. static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  278. {
  279. int err;
  280. struct mmc *mmc = mmc_get_mmc_dev(dev);
  281. struct sdhci_host *host = mmc->priv;
  282. debug("%s\n", __func__);
  283. if (host->ops->platform_execute_tuning) {
  284. err = host->ops->platform_execute_tuning(mmc, opcode);
  285. if (err)
  286. return err;
  287. return 0;
  288. }
  289. return 0;
  290. }
  291. #endif
  292. static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  293. {
  294. struct sdhci_host *host = mmc->priv;
  295. unsigned int div, clk = 0, timeout;
  296. /* Wait max 20 ms */
  297. timeout = 200;
  298. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  299. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  300. if (timeout == 0) {
  301. printf("%s: Timeout to wait cmd & data inhibit\n",
  302. __func__);
  303. return -EBUSY;
  304. }
  305. timeout--;
  306. udelay(100);
  307. }
  308. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  309. if (clock == 0)
  310. return 0;
  311. if (host->ops->set_delay)
  312. host->ops->set_delay(host);
  313. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  314. /*
  315. * Check if the Host Controller supports Programmable Clock
  316. * Mode.
  317. */
  318. if (host->clk_mul) {
  319. for (div = 1; div <= 1024; div++) {
  320. if ((host->max_clk / div) <= clock)
  321. break;
  322. }
  323. /*
  324. * Set Programmable Clock Mode in the Clock
  325. * Control register.
  326. */
  327. clk = SDHCI_PROG_CLOCK_MODE;
  328. div--;
  329. } else {
  330. /* Version 3.00 divisors must be a multiple of 2. */
  331. if (host->max_clk <= clock) {
  332. div = 1;
  333. } else {
  334. for (div = 2;
  335. div < SDHCI_MAX_DIV_SPEC_300;
  336. div += 2) {
  337. if ((host->max_clk / div) <= clock)
  338. break;
  339. }
  340. }
  341. div >>= 1;
  342. }
  343. } else {
  344. /* Version 2.00 divisors must be a power of 2. */
  345. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  346. if ((host->max_clk / div) <= clock)
  347. break;
  348. }
  349. div >>= 1;
  350. }
  351. if (host->ops && host->ops->set_clock)
  352. host->ops->set_clock(host, div);
  353. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  354. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  355. << SDHCI_DIVIDER_HI_SHIFT;
  356. clk |= SDHCI_CLOCK_INT_EN;
  357. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  358. /* Wait max 20 ms */
  359. timeout = 20;
  360. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  361. & SDHCI_CLOCK_INT_STABLE)) {
  362. if (timeout == 0) {
  363. printf("%s: Internal clock never stabilised.\n",
  364. __func__);
  365. return -EBUSY;
  366. }
  367. timeout--;
  368. udelay(1000);
  369. }
  370. clk |= SDHCI_CLOCK_CARD_EN;
  371. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  372. return 0;
  373. }
  374. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  375. {
  376. u8 pwr = 0;
  377. if (power != (unsigned short)-1) {
  378. switch (1 << power) {
  379. case MMC_VDD_165_195:
  380. pwr = SDHCI_POWER_180;
  381. break;
  382. case MMC_VDD_29_30:
  383. case MMC_VDD_30_31:
  384. pwr = SDHCI_POWER_300;
  385. break;
  386. case MMC_VDD_32_33:
  387. case MMC_VDD_33_34:
  388. pwr = SDHCI_POWER_330;
  389. break;
  390. }
  391. }
  392. if (pwr == 0) {
  393. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  394. return;
  395. }
  396. pwr |= SDHCI_POWER_ON;
  397. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  398. }
  399. #ifdef CONFIG_DM_MMC
  400. static int sdhci_set_ios(struct udevice *dev)
  401. {
  402. struct mmc *mmc = mmc_get_mmc_dev(dev);
  403. #else
  404. static int sdhci_set_ios(struct mmc *mmc)
  405. {
  406. #endif
  407. u32 ctrl;
  408. struct sdhci_host *host = mmc->priv;
  409. if (host->ops && host->ops->set_control_reg)
  410. host->ops->set_control_reg(host);
  411. if (mmc->clock != host->clock)
  412. sdhci_set_clock(mmc, mmc->clock);
  413. if (mmc->clk_disable)
  414. sdhci_set_clock(mmc, 0);
  415. /* Set bus width */
  416. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  417. if (mmc->bus_width == 8) {
  418. ctrl &= ~SDHCI_CTRL_4BITBUS;
  419. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  420. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  421. ctrl |= SDHCI_CTRL_8BITBUS;
  422. } else {
  423. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  424. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  425. ctrl &= ~SDHCI_CTRL_8BITBUS;
  426. if (mmc->bus_width == 4)
  427. ctrl |= SDHCI_CTRL_4BITBUS;
  428. else
  429. ctrl &= ~SDHCI_CTRL_4BITBUS;
  430. }
  431. if (mmc->clock > 26000000)
  432. ctrl |= SDHCI_CTRL_HISPD;
  433. else
  434. ctrl &= ~SDHCI_CTRL_HISPD;
  435. if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
  436. (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
  437. ctrl &= ~SDHCI_CTRL_HISPD;
  438. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  439. /* If available, call the driver specific "post" set_ios() function */
  440. if (host->ops && host->ops->set_ios_post)
  441. host->ops->set_ios_post(host);
  442. return 0;
  443. }
  444. static int sdhci_init(struct mmc *mmc)
  445. {
  446. struct sdhci_host *host = mmc->priv;
  447. sdhci_reset(host, SDHCI_RESET_ALL);
  448. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
  449. aligned_buffer = memalign(8, 512*1024);
  450. if (!aligned_buffer) {
  451. printf("%s: Aligned buffer alloc failed!!!\n",
  452. __func__);
  453. return -ENOMEM;
  454. }
  455. }
  456. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  457. if (host->ops && host->ops->get_cd)
  458. host->ops->get_cd(host);
  459. /* Enable only interrupts served by the SD controller */
  460. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  461. SDHCI_INT_ENABLE);
  462. /* Mask all sdhci interrupt sources */
  463. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  464. return 0;
  465. }
  466. #ifdef CONFIG_DM_MMC
  467. int sdhci_probe(struct udevice *dev)
  468. {
  469. struct mmc *mmc = mmc_get_mmc_dev(dev);
  470. return sdhci_init(mmc);
  471. }
  472. const struct dm_mmc_ops sdhci_ops = {
  473. .send_cmd = sdhci_send_command,
  474. .set_ios = sdhci_set_ios,
  475. #ifdef MMC_SUPPORTS_TUNING
  476. .execute_tuning = sdhci_execute_tuning,
  477. #endif
  478. };
  479. #else
  480. static const struct mmc_ops sdhci_ops = {
  481. .send_cmd = sdhci_send_command,
  482. .set_ios = sdhci_set_ios,
  483. .init = sdhci_init,
  484. };
  485. #endif
  486. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  487. u32 f_max, u32 f_min)
  488. {
  489. u32 caps, caps_1 = 0;
  490. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  491. #ifdef CONFIG_MMC_SDHCI_SDMA
  492. if (!(caps & SDHCI_CAN_DO_SDMA)) {
  493. printf("%s: Your controller doesn't support SDMA!!\n",
  494. __func__);
  495. return -EINVAL;
  496. }
  497. #endif
  498. if (host->quirks & SDHCI_QUIRK_REG32_RW)
  499. host->version =
  500. sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
  501. else
  502. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  503. cfg->name = host->name;
  504. #ifndef CONFIG_DM_MMC
  505. cfg->ops = &sdhci_ops;
  506. #endif
  507. /* Check whether the clock multiplier is supported or not */
  508. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  509. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  510. host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
  511. SDHCI_CLOCK_MUL_SHIFT;
  512. }
  513. if (host->max_clk == 0) {
  514. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  515. host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
  516. SDHCI_CLOCK_BASE_SHIFT;
  517. else
  518. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
  519. SDHCI_CLOCK_BASE_SHIFT;
  520. host->max_clk *= 1000000;
  521. if (host->clk_mul)
  522. host->max_clk *= host->clk_mul;
  523. }
  524. if (host->max_clk == 0) {
  525. printf("%s: Hardware doesn't specify base clock frequency\n",
  526. __func__);
  527. return -EINVAL;
  528. }
  529. if (f_max && (f_max < host->max_clk))
  530. cfg->f_max = f_max;
  531. else
  532. cfg->f_max = host->max_clk;
  533. if (f_min)
  534. cfg->f_min = f_min;
  535. else {
  536. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  537. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
  538. else
  539. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
  540. }
  541. cfg->voltages = 0;
  542. if (caps & SDHCI_CAN_VDD_330)
  543. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  544. if (caps & SDHCI_CAN_VDD_300)
  545. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  546. if (caps & SDHCI_CAN_VDD_180)
  547. cfg->voltages |= MMC_VDD_165_195;
  548. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  549. cfg->voltages |= host->voltages;
  550. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
  551. /* Since Host Controller Version3.0 */
  552. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  553. if (!(caps & SDHCI_CAN_DO_8BIT))
  554. cfg->host_caps &= ~MMC_MODE_8BIT;
  555. }
  556. if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
  557. cfg->host_caps &= ~MMC_MODE_HS;
  558. cfg->host_caps &= ~MMC_MODE_HS_52MHz;
  559. }
  560. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  561. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  562. if (!(cfg->voltages & MMC_VDD_165_195) ||
  563. (host->quirks & SDHCI_QUIRK_NO_1_8_V))
  564. caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  565. SDHCI_SUPPORT_DDR50);
  566. if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  567. SDHCI_SUPPORT_DDR50))
  568. cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  569. if (caps_1 & SDHCI_SUPPORT_SDR104) {
  570. cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  571. /*
  572. * SD3.0: SDR104 is supported so (for eMMC) the caps2
  573. * field can be promoted to support HS200.
  574. */
  575. cfg->host_caps |= MMC_CAP(MMC_HS_200);
  576. } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  577. cfg->host_caps |= MMC_CAP(UHS_SDR50);
  578. }
  579. if (caps_1 & SDHCI_SUPPORT_DDR50)
  580. cfg->host_caps |= MMC_CAP(UHS_DDR50);
  581. if (host->host_caps)
  582. cfg->host_caps |= host->host_caps;
  583. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  584. return 0;
  585. }
  586. #ifdef CONFIG_BLK
  587. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  588. {
  589. return mmc_bind(dev, mmc, cfg);
  590. }
  591. #else
  592. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
  593. {
  594. int ret;
  595. ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
  596. if (ret)
  597. return ret;
  598. host->mmc = mmc_create(&host->cfg, host);
  599. if (host->mmc == NULL) {
  600. printf("%s: mmc create fail!\n", __func__);
  601. return -ENOMEM;
  602. }
  603. return 0;
  604. }
  605. #endif