mmc.c 60 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008, Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based vaguely on the Linux code
  7. */
  8. #include <config.h>
  9. #include <common.h>
  10. #include <command.h>
  11. #include <dm.h>
  12. #include <dm/device-internal.h>
  13. #include <errno.h>
  14. #include <mmc.h>
  15. #include <part.h>
  16. #include <power/regulator.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <linux/list.h>
  20. #include <div64.h>
  21. #include "mmc_private.h"
  22. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  23. static int mmc_power_cycle(struct mmc *mmc);
  24. static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
  25. #if CONFIG_IS_ENABLED(MMC_TINY)
  26. static struct mmc mmc_static;
  27. struct mmc *find_mmc_device(int dev_num)
  28. {
  29. return &mmc_static;
  30. }
  31. void mmc_do_preinit(void)
  32. {
  33. struct mmc *m = &mmc_static;
  34. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  35. mmc_set_preinit(m, 1);
  36. #endif
  37. if (m->preinit)
  38. mmc_start_init(m);
  39. }
  40. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
  41. {
  42. return &mmc->block_dev;
  43. }
  44. #endif
  45. #if !CONFIG_IS_ENABLED(DM_MMC)
  46. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  47. static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
  48. {
  49. return -ENOSYS;
  50. }
  51. #endif
  52. __weak int board_mmc_getwp(struct mmc *mmc)
  53. {
  54. return -1;
  55. }
  56. int mmc_getwp(struct mmc *mmc)
  57. {
  58. int wp;
  59. wp = board_mmc_getwp(mmc);
  60. if (wp < 0) {
  61. if (mmc->cfg->ops->getwp)
  62. wp = mmc->cfg->ops->getwp(mmc);
  63. else
  64. wp = 0;
  65. }
  66. return wp;
  67. }
  68. __weak int board_mmc_getcd(struct mmc *mmc)
  69. {
  70. return -1;
  71. }
  72. #endif
  73. #ifdef CONFIG_MMC_TRACE
  74. void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  75. {
  76. printf("CMD_SEND:%d\n", cmd->cmdidx);
  77. printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
  78. }
  79. void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  80. {
  81. int i;
  82. u8 *ptr;
  83. if (ret) {
  84. printf("\t\tRET\t\t\t %d\n", ret);
  85. } else {
  86. switch (cmd->resp_type) {
  87. case MMC_RSP_NONE:
  88. printf("\t\tMMC_RSP_NONE\n");
  89. break;
  90. case MMC_RSP_R1:
  91. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
  92. cmd->response[0]);
  93. break;
  94. case MMC_RSP_R1b:
  95. printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
  96. cmd->response[0]);
  97. break;
  98. case MMC_RSP_R2:
  99. printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
  100. cmd->response[0]);
  101. printf("\t\t \t\t 0x%08X \n",
  102. cmd->response[1]);
  103. printf("\t\t \t\t 0x%08X \n",
  104. cmd->response[2]);
  105. printf("\t\t \t\t 0x%08X \n",
  106. cmd->response[3]);
  107. printf("\n");
  108. printf("\t\t\t\t\tDUMPING DATA\n");
  109. for (i = 0; i < 4; i++) {
  110. int j;
  111. printf("\t\t\t\t\t%03d - ", i*4);
  112. ptr = (u8 *)&cmd->response[i];
  113. ptr += 3;
  114. for (j = 0; j < 4; j++)
  115. printf("%02X ", *ptr--);
  116. printf("\n");
  117. }
  118. break;
  119. case MMC_RSP_R3:
  120. printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
  121. cmd->response[0]);
  122. break;
  123. default:
  124. printf("\t\tERROR MMC rsp not supported\n");
  125. break;
  126. }
  127. }
  128. }
  129. void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
  130. {
  131. int status;
  132. status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
  133. printf("CURR STATE:%d\n", status);
  134. }
  135. #endif
  136. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  137. const char *mmc_mode_name(enum bus_mode mode)
  138. {
  139. static const char *const names[] = {
  140. [MMC_LEGACY] = "MMC legacy",
  141. [SD_LEGACY] = "SD Legacy",
  142. [MMC_HS] = "MMC High Speed (26MHz)",
  143. [SD_HS] = "SD High Speed (50MHz)",
  144. [UHS_SDR12] = "UHS SDR12 (25MHz)",
  145. [UHS_SDR25] = "UHS SDR25 (50MHz)",
  146. [UHS_SDR50] = "UHS SDR50 (100MHz)",
  147. [UHS_SDR104] = "UHS SDR104 (208MHz)",
  148. [UHS_DDR50] = "UHS DDR50 (50MHz)",
  149. [MMC_HS_52] = "MMC High Speed (52MHz)",
  150. [MMC_DDR_52] = "MMC DDR52 (52MHz)",
  151. [MMC_HS_200] = "HS200 (200MHz)",
  152. };
  153. if (mode >= MMC_MODES_END)
  154. return "Unknown mode";
  155. else
  156. return names[mode];
  157. }
  158. #endif
  159. static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
  160. {
  161. static const int freqs[] = {
  162. [MMC_LEGACY] = 25000000,
  163. [SD_LEGACY] = 25000000,
  164. [MMC_HS] = 26000000,
  165. [SD_HS] = 50000000,
  166. [MMC_HS_52] = 52000000,
  167. [MMC_DDR_52] = 52000000,
  168. [UHS_SDR12] = 25000000,
  169. [UHS_SDR25] = 50000000,
  170. [UHS_SDR50] = 100000000,
  171. [UHS_DDR50] = 50000000,
  172. [UHS_SDR104] = 208000000,
  173. [MMC_HS_200] = 200000000,
  174. };
  175. if (mode == MMC_LEGACY)
  176. return mmc->legacy_speed;
  177. else if (mode >= MMC_MODES_END)
  178. return 0;
  179. else
  180. return freqs[mode];
  181. }
  182. static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
  183. {
  184. mmc->selected_mode = mode;
  185. mmc->tran_speed = mmc_mode2freq(mmc, mode);
  186. mmc->ddr_mode = mmc_is_mode_ddr(mode);
  187. pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
  188. mmc->tran_speed / 1000000);
  189. return 0;
  190. }
  191. #if !CONFIG_IS_ENABLED(DM_MMC)
  192. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  193. {
  194. int ret;
  195. mmmc_trace_before_send(mmc, cmd);
  196. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  197. mmmc_trace_after_send(mmc, cmd, ret);
  198. return ret;
  199. }
  200. #endif
  201. int mmc_send_status(struct mmc *mmc, int timeout)
  202. {
  203. struct mmc_cmd cmd;
  204. int err, retries = 5;
  205. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  206. cmd.resp_type = MMC_RSP_R1;
  207. if (!mmc_host_is_spi(mmc))
  208. cmd.cmdarg = mmc->rca << 16;
  209. while (1) {
  210. err = mmc_send_cmd(mmc, &cmd, NULL);
  211. if (!err) {
  212. if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
  213. (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
  214. MMC_STATE_PRG)
  215. break;
  216. if (cmd.response[0] & MMC_STATUS_MASK) {
  217. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  218. pr_err("Status Error: 0x%08X\n",
  219. cmd.response[0]);
  220. #endif
  221. return -ECOMM;
  222. }
  223. } else if (--retries < 0)
  224. return err;
  225. if (timeout-- <= 0)
  226. break;
  227. udelay(1000);
  228. }
  229. mmc_trace_state(mmc, &cmd);
  230. if (timeout <= 0) {
  231. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  232. pr_err("Timeout waiting card ready\n");
  233. #endif
  234. return -ETIMEDOUT;
  235. }
  236. return 0;
  237. }
  238. int mmc_set_blocklen(struct mmc *mmc, int len)
  239. {
  240. struct mmc_cmd cmd;
  241. int err;
  242. if (mmc->ddr_mode)
  243. return 0;
  244. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  245. cmd.resp_type = MMC_RSP_R1;
  246. cmd.cmdarg = len;
  247. err = mmc_send_cmd(mmc, &cmd, NULL);
  248. #ifdef CONFIG_MMC_QUIRKS
  249. if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
  250. int retries = 4;
  251. /*
  252. * It has been seen that SET_BLOCKLEN may fail on the first
  253. * attempt, let's try a few more time
  254. */
  255. do {
  256. err = mmc_send_cmd(mmc, &cmd, NULL);
  257. if (!err)
  258. break;
  259. } while (retries--);
  260. }
  261. #endif
  262. return err;
  263. }
  264. #ifdef MMC_SUPPORTS_TUNING
  265. static const u8 tuning_blk_pattern_4bit[] = {
  266. 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
  267. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  268. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  269. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  270. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  271. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  272. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  273. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  274. };
  275. static const u8 tuning_blk_pattern_8bit[] = {
  276. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  277. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  278. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  279. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  280. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  281. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  282. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  283. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  284. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  285. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  286. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  287. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  288. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  289. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  290. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  291. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  292. };
  293. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
  294. {
  295. struct mmc_cmd cmd;
  296. struct mmc_data data;
  297. const u8 *tuning_block_pattern;
  298. int size, err;
  299. if (mmc->bus_width == 8) {
  300. tuning_block_pattern = tuning_blk_pattern_8bit;
  301. size = sizeof(tuning_blk_pattern_8bit);
  302. } else if (mmc->bus_width == 4) {
  303. tuning_block_pattern = tuning_blk_pattern_4bit;
  304. size = sizeof(tuning_blk_pattern_4bit);
  305. } else {
  306. return -EINVAL;
  307. }
  308. ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
  309. cmd.cmdidx = opcode;
  310. cmd.cmdarg = 0;
  311. cmd.resp_type = MMC_RSP_R1;
  312. data.dest = (void *)data_buf;
  313. data.blocks = 1;
  314. data.blocksize = size;
  315. data.flags = MMC_DATA_READ;
  316. err = mmc_send_cmd(mmc, &cmd, &data);
  317. if (err)
  318. return err;
  319. if (memcmp(data_buf, tuning_block_pattern, size))
  320. return -EIO;
  321. return 0;
  322. }
  323. #endif
  324. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  325. lbaint_t blkcnt)
  326. {
  327. struct mmc_cmd cmd;
  328. struct mmc_data data;
  329. if (blkcnt > 1)
  330. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  331. else
  332. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  333. if (mmc->high_capacity)
  334. cmd.cmdarg = start;
  335. else
  336. cmd.cmdarg = start * mmc->read_bl_len;
  337. cmd.resp_type = MMC_RSP_R1;
  338. data.dest = dst;
  339. data.blocks = blkcnt;
  340. data.blocksize = mmc->read_bl_len;
  341. data.flags = MMC_DATA_READ;
  342. if (mmc_send_cmd(mmc, &cmd, &data))
  343. return 0;
  344. if (blkcnt > 1) {
  345. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  346. cmd.cmdarg = 0;
  347. cmd.resp_type = MMC_RSP_R1b;
  348. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  349. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  350. pr_err("mmc fail to send stop cmd\n");
  351. #endif
  352. return 0;
  353. }
  354. }
  355. return blkcnt;
  356. }
  357. #if CONFIG_IS_ENABLED(BLK)
  358. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  359. #else
  360. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  361. void *dst)
  362. #endif
  363. {
  364. #if CONFIG_IS_ENABLED(BLK)
  365. struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
  366. #endif
  367. int dev_num = block_dev->devnum;
  368. int err;
  369. lbaint_t cur, blocks_todo = blkcnt;
  370. if (blkcnt == 0)
  371. return 0;
  372. struct mmc *mmc = find_mmc_device(dev_num);
  373. if (!mmc)
  374. return 0;
  375. if (CONFIG_IS_ENABLED(MMC_TINY))
  376. err = mmc_switch_part(mmc, block_dev->hwpart);
  377. else
  378. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  379. if (err < 0)
  380. return 0;
  381. if ((start + blkcnt) > block_dev->lba) {
  382. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  383. pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  384. start + blkcnt, block_dev->lba);
  385. #endif
  386. return 0;
  387. }
  388. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  389. pr_debug("%s: Failed to set blocklen\n", __func__);
  390. return 0;
  391. }
  392. do {
  393. cur = (blocks_todo > mmc->cfg->b_max) ?
  394. mmc->cfg->b_max : blocks_todo;
  395. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  396. pr_debug("%s: Failed to read blocks\n", __func__);
  397. return 0;
  398. }
  399. blocks_todo -= cur;
  400. start += cur;
  401. dst += cur * mmc->read_bl_len;
  402. } while (blocks_todo > 0);
  403. return blkcnt;
  404. }
  405. static int mmc_go_idle(struct mmc *mmc)
  406. {
  407. struct mmc_cmd cmd;
  408. int err;
  409. udelay(1000);
  410. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  411. cmd.cmdarg = 0;
  412. cmd.resp_type = MMC_RSP_NONE;
  413. err = mmc_send_cmd(mmc, &cmd, NULL);
  414. if (err)
  415. return err;
  416. udelay(2000);
  417. return 0;
  418. }
  419. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  420. static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
  421. {
  422. struct mmc_cmd cmd;
  423. int err = 0;
  424. /*
  425. * Send CMD11 only if the request is to switch the card to
  426. * 1.8V signalling.
  427. */
  428. if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  429. return mmc_set_signal_voltage(mmc, signal_voltage);
  430. cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
  431. cmd.cmdarg = 0;
  432. cmd.resp_type = MMC_RSP_R1;
  433. err = mmc_send_cmd(mmc, &cmd, NULL);
  434. if (err)
  435. return err;
  436. if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
  437. return -EIO;
  438. /*
  439. * The card should drive cmd and dat[0:3] low immediately
  440. * after the response of cmd11, but wait 100 us to be sure
  441. */
  442. err = mmc_wait_dat0(mmc, 0, 100);
  443. if (err == -ENOSYS)
  444. udelay(100);
  445. else if (err)
  446. return -ETIMEDOUT;
  447. /*
  448. * During a signal voltage level switch, the clock must be gated
  449. * for 5 ms according to the SD spec
  450. */
  451. mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
  452. err = mmc_set_signal_voltage(mmc, signal_voltage);
  453. if (err)
  454. return err;
  455. /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
  456. mdelay(10);
  457. mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
  458. /*
  459. * Failure to switch is indicated by the card holding
  460. * dat[0:3] low. Wait for at least 1 ms according to spec
  461. */
  462. err = mmc_wait_dat0(mmc, 1, 1000);
  463. if (err == -ENOSYS)
  464. udelay(1000);
  465. else if (err)
  466. return -ETIMEDOUT;
  467. return 0;
  468. }
  469. #endif
  470. static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
  471. {
  472. int timeout = 1000;
  473. int err;
  474. struct mmc_cmd cmd;
  475. while (1) {
  476. cmd.cmdidx = MMC_CMD_APP_CMD;
  477. cmd.resp_type = MMC_RSP_R1;
  478. cmd.cmdarg = 0;
  479. err = mmc_send_cmd(mmc, &cmd, NULL);
  480. if (err)
  481. return err;
  482. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  483. cmd.resp_type = MMC_RSP_R3;
  484. /*
  485. * Most cards do not answer if some reserved bits
  486. * in the ocr are set. However, Some controller
  487. * can set bit 7 (reserved for low voltages), but
  488. * how to manage low voltages SD card is not yet
  489. * specified.
  490. */
  491. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  492. (mmc->cfg->voltages & 0xff8000);
  493. if (mmc->version == SD_VERSION_2)
  494. cmd.cmdarg |= OCR_HCS;
  495. if (uhs_en)
  496. cmd.cmdarg |= OCR_S18R;
  497. err = mmc_send_cmd(mmc, &cmd, NULL);
  498. if (err)
  499. return err;
  500. if (cmd.response[0] & OCR_BUSY)
  501. break;
  502. if (timeout-- <= 0)
  503. return -EOPNOTSUPP;
  504. udelay(1000);
  505. }
  506. if (mmc->version != SD_VERSION_2)
  507. mmc->version = SD_VERSION_1_0;
  508. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  509. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  510. cmd.resp_type = MMC_RSP_R3;
  511. cmd.cmdarg = 0;
  512. err = mmc_send_cmd(mmc, &cmd, NULL);
  513. if (err)
  514. return err;
  515. }
  516. mmc->ocr = cmd.response[0];
  517. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  518. if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
  519. == 0x41000000) {
  520. err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  521. if (err)
  522. return err;
  523. }
  524. #endif
  525. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  526. mmc->rca = 0;
  527. return 0;
  528. }
  529. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  530. {
  531. struct mmc_cmd cmd;
  532. int err;
  533. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  534. cmd.resp_type = MMC_RSP_R3;
  535. cmd.cmdarg = 0;
  536. if (use_arg && !mmc_host_is_spi(mmc))
  537. cmd.cmdarg = OCR_HCS |
  538. (mmc->cfg->voltages &
  539. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  540. (mmc->ocr & OCR_ACCESS_MODE);
  541. err = mmc_send_cmd(mmc, &cmd, NULL);
  542. if (err)
  543. return err;
  544. mmc->ocr = cmd.response[0];
  545. return 0;
  546. }
  547. static int mmc_send_op_cond(struct mmc *mmc)
  548. {
  549. int err, i;
  550. /* Some cards seem to need this */
  551. mmc_go_idle(mmc);
  552. /* Asking to the card its capabilities */
  553. for (i = 0; i < 2; i++) {
  554. err = mmc_send_op_cond_iter(mmc, i != 0);
  555. if (err)
  556. return err;
  557. /* exit if not busy (flag seems to be inverted) */
  558. if (mmc->ocr & OCR_BUSY)
  559. break;
  560. }
  561. mmc->op_cond_pending = 1;
  562. return 0;
  563. }
  564. static int mmc_complete_op_cond(struct mmc *mmc)
  565. {
  566. struct mmc_cmd cmd;
  567. int timeout = 1000;
  568. ulong start;
  569. int err;
  570. mmc->op_cond_pending = 0;
  571. if (!(mmc->ocr & OCR_BUSY)) {
  572. /* Some cards seem to need this */
  573. mmc_go_idle(mmc);
  574. start = get_timer(0);
  575. while (1) {
  576. err = mmc_send_op_cond_iter(mmc, 1);
  577. if (err)
  578. return err;
  579. if (mmc->ocr & OCR_BUSY)
  580. break;
  581. if (get_timer(start) > timeout)
  582. return -EOPNOTSUPP;
  583. udelay(100);
  584. }
  585. }
  586. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  587. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  588. cmd.resp_type = MMC_RSP_R3;
  589. cmd.cmdarg = 0;
  590. err = mmc_send_cmd(mmc, &cmd, NULL);
  591. if (err)
  592. return err;
  593. mmc->ocr = cmd.response[0];
  594. }
  595. mmc->version = MMC_VERSION_UNKNOWN;
  596. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  597. mmc->rca = 1;
  598. return 0;
  599. }
  600. static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  601. {
  602. struct mmc_cmd cmd;
  603. struct mmc_data data;
  604. int err;
  605. /* Get the Card Status Register */
  606. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  607. cmd.resp_type = MMC_RSP_R1;
  608. cmd.cmdarg = 0;
  609. data.dest = (char *)ext_csd;
  610. data.blocks = 1;
  611. data.blocksize = MMC_MAX_BLOCK_LEN;
  612. data.flags = MMC_DATA_READ;
  613. err = mmc_send_cmd(mmc, &cmd, &data);
  614. return err;
  615. }
  616. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  617. {
  618. struct mmc_cmd cmd;
  619. int timeout = 1000;
  620. int retries = 3;
  621. int ret;
  622. cmd.cmdidx = MMC_CMD_SWITCH;
  623. cmd.resp_type = MMC_RSP_R1b;
  624. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  625. (index << 16) |
  626. (value << 8);
  627. while (retries > 0) {
  628. ret = mmc_send_cmd(mmc, &cmd, NULL);
  629. /* Waiting for the ready status */
  630. if (!ret) {
  631. ret = mmc_send_status(mmc, timeout);
  632. return ret;
  633. }
  634. retries--;
  635. }
  636. return ret;
  637. }
  638. static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  639. {
  640. int err;
  641. int speed_bits;
  642. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  643. switch (mode) {
  644. case MMC_HS:
  645. case MMC_HS_52:
  646. case MMC_DDR_52:
  647. speed_bits = EXT_CSD_TIMING_HS;
  648. break;
  649. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  650. case MMC_HS_200:
  651. speed_bits = EXT_CSD_TIMING_HS200;
  652. break;
  653. #endif
  654. case MMC_LEGACY:
  655. speed_bits = EXT_CSD_TIMING_LEGACY;
  656. break;
  657. default:
  658. return -EINVAL;
  659. }
  660. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
  661. speed_bits);
  662. if (err)
  663. return err;
  664. if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
  665. /* Now check to see that it worked */
  666. err = mmc_send_ext_csd(mmc, test_csd);
  667. if (err)
  668. return err;
  669. /* No high-speed support */
  670. if (!test_csd[EXT_CSD_HS_TIMING])
  671. return -ENOTSUPP;
  672. }
  673. return 0;
  674. }
  675. static int mmc_get_capabilities(struct mmc *mmc)
  676. {
  677. u8 *ext_csd = mmc->ext_csd;
  678. char cardtype;
  679. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  680. if (mmc_host_is_spi(mmc))
  681. return 0;
  682. /* Only version 4 supports high-speed */
  683. if (mmc->version < MMC_VERSION_4)
  684. return 0;
  685. if (!ext_csd) {
  686. pr_err("No ext_csd found!\n"); /* this should enver happen */
  687. return -ENOTSUPP;
  688. }
  689. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  690. cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
  691. mmc->cardtype = cardtype;
  692. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  693. if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  694. EXT_CSD_CARD_TYPE_HS200_1_8V)) {
  695. mmc->card_caps |= MMC_MODE_HS200;
  696. }
  697. #endif
  698. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  699. if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
  700. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  701. mmc->card_caps |= MMC_MODE_HS_52MHz;
  702. }
  703. if (cardtype & EXT_CSD_CARD_TYPE_26)
  704. mmc->card_caps |= MMC_MODE_HS;
  705. return 0;
  706. }
  707. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  708. {
  709. switch (part_num) {
  710. case 0:
  711. mmc->capacity = mmc->capacity_user;
  712. break;
  713. case 1:
  714. case 2:
  715. mmc->capacity = mmc->capacity_boot;
  716. break;
  717. case 3:
  718. mmc->capacity = mmc->capacity_rpmb;
  719. break;
  720. case 4:
  721. case 5:
  722. case 6:
  723. case 7:
  724. mmc->capacity = mmc->capacity_gp[part_num - 4];
  725. break;
  726. default:
  727. return -1;
  728. }
  729. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  730. return 0;
  731. }
  732. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  733. static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
  734. {
  735. int forbidden = 0;
  736. bool change = false;
  737. if (part_num & PART_ACCESS_MASK)
  738. forbidden = MMC_CAP(MMC_HS_200);
  739. if (MMC_CAP(mmc->selected_mode) & forbidden) {
  740. pr_debug("selected mode (%s) is forbidden for part %d\n",
  741. mmc_mode_name(mmc->selected_mode), part_num);
  742. change = true;
  743. } else if (mmc->selected_mode != mmc->best_mode) {
  744. pr_debug("selected mode is not optimal\n");
  745. change = true;
  746. }
  747. if (change)
  748. return mmc_select_mode_and_width(mmc,
  749. mmc->card_caps & ~forbidden);
  750. return 0;
  751. }
  752. #else
  753. static inline int mmc_boot_part_access_chk(struct mmc *mmc,
  754. unsigned int part_num)
  755. {
  756. return 0;
  757. }
  758. #endif
  759. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  760. {
  761. int ret;
  762. ret = mmc_boot_part_access_chk(mmc, part_num);
  763. if (ret)
  764. return ret;
  765. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
  766. (mmc->part_config & ~PART_ACCESS_MASK)
  767. | (part_num & PART_ACCESS_MASK));
  768. /*
  769. * Set the capacity if the switch succeeded or was intended
  770. * to return to representing the raw device.
  771. */
  772. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  773. ret = mmc_set_capacity(mmc, part_num);
  774. mmc_get_blk_desc(mmc)->hwpart = part_num;
  775. }
  776. return ret;
  777. }
  778. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  779. int mmc_hwpart_config(struct mmc *mmc,
  780. const struct mmc_hwpart_conf *conf,
  781. enum mmc_hwpart_conf_mode mode)
  782. {
  783. u8 part_attrs = 0;
  784. u32 enh_size_mult;
  785. u32 enh_start_addr;
  786. u32 gp_size_mult[4];
  787. u32 max_enh_size_mult;
  788. u32 tot_enh_size_mult = 0;
  789. u8 wr_rel_set;
  790. int i, pidx, err;
  791. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  792. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  793. return -EINVAL;
  794. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  795. pr_err("eMMC >= 4.4 required for enhanced user data area\n");
  796. return -EMEDIUMTYPE;
  797. }
  798. if (!(mmc->part_support & PART_SUPPORT)) {
  799. pr_err("Card does not support partitioning\n");
  800. return -EMEDIUMTYPE;
  801. }
  802. if (!mmc->hc_wp_grp_size) {
  803. pr_err("Card does not define HC WP group size\n");
  804. return -EMEDIUMTYPE;
  805. }
  806. /* check partition alignment and total enhanced size */
  807. if (conf->user.enh_size) {
  808. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  809. conf->user.enh_start % mmc->hc_wp_grp_size) {
  810. pr_err("User data enhanced area not HC WP group "
  811. "size aligned\n");
  812. return -EINVAL;
  813. }
  814. part_attrs |= EXT_CSD_ENH_USR;
  815. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  816. if (mmc->high_capacity) {
  817. enh_start_addr = conf->user.enh_start;
  818. } else {
  819. enh_start_addr = (conf->user.enh_start << 9);
  820. }
  821. } else {
  822. enh_size_mult = 0;
  823. enh_start_addr = 0;
  824. }
  825. tot_enh_size_mult += enh_size_mult;
  826. for (pidx = 0; pidx < 4; pidx++) {
  827. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  828. pr_err("GP%i partition not HC WP group size "
  829. "aligned\n", pidx+1);
  830. return -EINVAL;
  831. }
  832. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  833. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  834. part_attrs |= EXT_CSD_ENH_GP(pidx);
  835. tot_enh_size_mult += gp_size_mult[pidx];
  836. }
  837. }
  838. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  839. pr_err("Card does not support enhanced attribute\n");
  840. return -EMEDIUMTYPE;
  841. }
  842. err = mmc_send_ext_csd(mmc, ext_csd);
  843. if (err)
  844. return err;
  845. max_enh_size_mult =
  846. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  847. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  848. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  849. if (tot_enh_size_mult > max_enh_size_mult) {
  850. pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
  851. tot_enh_size_mult, max_enh_size_mult);
  852. return -EMEDIUMTYPE;
  853. }
  854. /* The default value of EXT_CSD_WR_REL_SET is device
  855. * dependent, the values can only be changed if the
  856. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  857. * changed only once and before partitioning is completed. */
  858. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  859. if (conf->user.wr_rel_change) {
  860. if (conf->user.wr_rel_set)
  861. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  862. else
  863. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  864. }
  865. for (pidx = 0; pidx < 4; pidx++) {
  866. if (conf->gp_part[pidx].wr_rel_change) {
  867. if (conf->gp_part[pidx].wr_rel_set)
  868. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  869. else
  870. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  871. }
  872. }
  873. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  874. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  875. puts("Card does not support host controlled partition write "
  876. "reliability settings\n");
  877. return -EMEDIUMTYPE;
  878. }
  879. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  880. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  881. pr_err("Card already partitioned\n");
  882. return -EPERM;
  883. }
  884. if (mode == MMC_HWPART_CONF_CHECK)
  885. return 0;
  886. /* Partitioning requires high-capacity size definitions */
  887. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  888. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  889. EXT_CSD_ERASE_GROUP_DEF, 1);
  890. if (err)
  891. return err;
  892. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  893. /* update erase group size to be high-capacity */
  894. mmc->erase_grp_size =
  895. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  896. }
  897. /* all OK, write the configuration */
  898. for (i = 0; i < 4; i++) {
  899. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  900. EXT_CSD_ENH_START_ADDR+i,
  901. (enh_start_addr >> (i*8)) & 0xFF);
  902. if (err)
  903. return err;
  904. }
  905. for (i = 0; i < 3; i++) {
  906. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  907. EXT_CSD_ENH_SIZE_MULT+i,
  908. (enh_size_mult >> (i*8)) & 0xFF);
  909. if (err)
  910. return err;
  911. }
  912. for (pidx = 0; pidx < 4; pidx++) {
  913. for (i = 0; i < 3; i++) {
  914. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  915. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  916. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  917. if (err)
  918. return err;
  919. }
  920. }
  921. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  922. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  923. if (err)
  924. return err;
  925. if (mode == MMC_HWPART_CONF_SET)
  926. return 0;
  927. /* The WR_REL_SET is a write-once register but shall be
  928. * written before setting PART_SETTING_COMPLETED. As it is
  929. * write-once we can only write it when completing the
  930. * partitioning. */
  931. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  932. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  933. EXT_CSD_WR_REL_SET, wr_rel_set);
  934. if (err)
  935. return err;
  936. }
  937. /* Setting PART_SETTING_COMPLETED confirms the partition
  938. * configuration but it only becomes effective after power
  939. * cycle, so we do not adjust the partition related settings
  940. * in the mmc struct. */
  941. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  942. EXT_CSD_PARTITION_SETTING,
  943. EXT_CSD_PARTITION_SETTING_COMPLETED);
  944. if (err)
  945. return err;
  946. return 0;
  947. }
  948. #endif
  949. #if !CONFIG_IS_ENABLED(DM_MMC)
  950. int mmc_getcd(struct mmc *mmc)
  951. {
  952. int cd;
  953. cd = board_mmc_getcd(mmc);
  954. if (cd < 0) {
  955. if (mmc->cfg->ops->getcd)
  956. cd = mmc->cfg->ops->getcd(mmc);
  957. else
  958. cd = 1;
  959. }
  960. return cd;
  961. }
  962. #endif
  963. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  964. {
  965. struct mmc_cmd cmd;
  966. struct mmc_data data;
  967. /* Switch the frequency */
  968. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  969. cmd.resp_type = MMC_RSP_R1;
  970. cmd.cmdarg = (mode << 31) | 0xffffff;
  971. cmd.cmdarg &= ~(0xf << (group * 4));
  972. cmd.cmdarg |= value << (group * 4);
  973. data.dest = (char *)resp;
  974. data.blocksize = 64;
  975. data.blocks = 1;
  976. data.flags = MMC_DATA_READ;
  977. return mmc_send_cmd(mmc, &cmd, &data);
  978. }
  979. static int sd_get_capabilities(struct mmc *mmc)
  980. {
  981. int err;
  982. struct mmc_cmd cmd;
  983. ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
  984. ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
  985. struct mmc_data data;
  986. int timeout;
  987. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  988. u32 sd3_bus_mode;
  989. #endif
  990. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
  991. if (mmc_host_is_spi(mmc))
  992. return 0;
  993. /* Read the SCR to find out if this card supports higher speeds */
  994. cmd.cmdidx = MMC_CMD_APP_CMD;
  995. cmd.resp_type = MMC_RSP_R1;
  996. cmd.cmdarg = mmc->rca << 16;
  997. err = mmc_send_cmd(mmc, &cmd, NULL);
  998. if (err)
  999. return err;
  1000. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  1001. cmd.resp_type = MMC_RSP_R1;
  1002. cmd.cmdarg = 0;
  1003. timeout = 3;
  1004. retry_scr:
  1005. data.dest = (char *)scr;
  1006. data.blocksize = 8;
  1007. data.blocks = 1;
  1008. data.flags = MMC_DATA_READ;
  1009. err = mmc_send_cmd(mmc, &cmd, &data);
  1010. if (err) {
  1011. if (timeout--)
  1012. goto retry_scr;
  1013. return err;
  1014. }
  1015. mmc->scr[0] = __be32_to_cpu(scr[0]);
  1016. mmc->scr[1] = __be32_to_cpu(scr[1]);
  1017. switch ((mmc->scr[0] >> 24) & 0xf) {
  1018. case 0:
  1019. mmc->version = SD_VERSION_1_0;
  1020. break;
  1021. case 1:
  1022. mmc->version = SD_VERSION_1_10;
  1023. break;
  1024. case 2:
  1025. mmc->version = SD_VERSION_2;
  1026. if ((mmc->scr[0] >> 15) & 0x1)
  1027. mmc->version = SD_VERSION_3;
  1028. break;
  1029. default:
  1030. mmc->version = SD_VERSION_1_0;
  1031. break;
  1032. }
  1033. if (mmc->scr[0] & SD_DATA_4BIT)
  1034. mmc->card_caps |= MMC_MODE_4BIT;
  1035. /* Version 1.0 doesn't support switching */
  1036. if (mmc->version == SD_VERSION_1_0)
  1037. return 0;
  1038. timeout = 4;
  1039. while (timeout--) {
  1040. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  1041. (u8 *)switch_status);
  1042. if (err)
  1043. return err;
  1044. /* The high-speed function is busy. Try again */
  1045. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  1046. break;
  1047. }
  1048. /* If high-speed isn't supported, we return */
  1049. if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
  1050. mmc->card_caps |= MMC_CAP(SD_HS);
  1051. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1052. /* Version before 3.0 don't support UHS modes */
  1053. if (mmc->version < SD_VERSION_3)
  1054. return 0;
  1055. sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
  1056. if (sd3_bus_mode & SD_MODE_UHS_SDR104)
  1057. mmc->card_caps |= MMC_CAP(UHS_SDR104);
  1058. if (sd3_bus_mode & SD_MODE_UHS_SDR50)
  1059. mmc->card_caps |= MMC_CAP(UHS_SDR50);
  1060. if (sd3_bus_mode & SD_MODE_UHS_SDR25)
  1061. mmc->card_caps |= MMC_CAP(UHS_SDR25);
  1062. if (sd3_bus_mode & SD_MODE_UHS_SDR12)
  1063. mmc->card_caps |= MMC_CAP(UHS_SDR12);
  1064. if (sd3_bus_mode & SD_MODE_UHS_DDR50)
  1065. mmc->card_caps |= MMC_CAP(UHS_DDR50);
  1066. #endif
  1067. return 0;
  1068. }
  1069. static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  1070. {
  1071. int err;
  1072. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  1073. int speed;
  1074. switch (mode) {
  1075. case SD_LEGACY:
  1076. speed = UHS_SDR12_BUS_SPEED;
  1077. break;
  1078. case SD_HS:
  1079. speed = HIGH_SPEED_BUS_SPEED;
  1080. break;
  1081. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1082. case UHS_SDR12:
  1083. speed = UHS_SDR12_BUS_SPEED;
  1084. break;
  1085. case UHS_SDR25:
  1086. speed = UHS_SDR25_BUS_SPEED;
  1087. break;
  1088. case UHS_SDR50:
  1089. speed = UHS_SDR50_BUS_SPEED;
  1090. break;
  1091. case UHS_DDR50:
  1092. speed = UHS_DDR50_BUS_SPEED;
  1093. break;
  1094. case UHS_SDR104:
  1095. speed = UHS_SDR104_BUS_SPEED;
  1096. break;
  1097. #endif
  1098. default:
  1099. return -EINVAL;
  1100. }
  1101. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
  1102. if (err)
  1103. return err;
  1104. if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
  1105. return -ENOTSUPP;
  1106. return 0;
  1107. }
  1108. static int sd_select_bus_width(struct mmc *mmc, int w)
  1109. {
  1110. int err;
  1111. struct mmc_cmd cmd;
  1112. if ((w != 4) && (w != 1))
  1113. return -EINVAL;
  1114. cmd.cmdidx = MMC_CMD_APP_CMD;
  1115. cmd.resp_type = MMC_RSP_R1;
  1116. cmd.cmdarg = mmc->rca << 16;
  1117. err = mmc_send_cmd(mmc, &cmd, NULL);
  1118. if (err)
  1119. return err;
  1120. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1121. cmd.resp_type = MMC_RSP_R1;
  1122. if (w == 4)
  1123. cmd.cmdarg = 2;
  1124. else if (w == 1)
  1125. cmd.cmdarg = 0;
  1126. err = mmc_send_cmd(mmc, &cmd, NULL);
  1127. if (err)
  1128. return err;
  1129. return 0;
  1130. }
  1131. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1132. static int sd_read_ssr(struct mmc *mmc)
  1133. {
  1134. static const unsigned int sd_au_size[] = {
  1135. 0, SZ_16K / 512, SZ_32K / 512,
  1136. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  1137. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  1138. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  1139. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  1140. SZ_64M / 512,
  1141. };
  1142. int err, i;
  1143. struct mmc_cmd cmd;
  1144. ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
  1145. struct mmc_data data;
  1146. int timeout = 3;
  1147. unsigned int au, eo, et, es;
  1148. cmd.cmdidx = MMC_CMD_APP_CMD;
  1149. cmd.resp_type = MMC_RSP_R1;
  1150. cmd.cmdarg = mmc->rca << 16;
  1151. err = mmc_send_cmd(mmc, &cmd, NULL);
  1152. if (err)
  1153. return err;
  1154. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  1155. cmd.resp_type = MMC_RSP_R1;
  1156. cmd.cmdarg = 0;
  1157. retry_ssr:
  1158. data.dest = (char *)ssr;
  1159. data.blocksize = 64;
  1160. data.blocks = 1;
  1161. data.flags = MMC_DATA_READ;
  1162. err = mmc_send_cmd(mmc, &cmd, &data);
  1163. if (err) {
  1164. if (timeout--)
  1165. goto retry_ssr;
  1166. return err;
  1167. }
  1168. for (i = 0; i < 16; i++)
  1169. ssr[i] = be32_to_cpu(ssr[i]);
  1170. au = (ssr[2] >> 12) & 0xF;
  1171. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  1172. mmc->ssr.au = sd_au_size[au];
  1173. es = (ssr[3] >> 24) & 0xFF;
  1174. es |= (ssr[2] & 0xFF) << 8;
  1175. et = (ssr[3] >> 18) & 0x3F;
  1176. if (es && et) {
  1177. eo = (ssr[3] >> 16) & 0x3;
  1178. mmc->ssr.erase_timeout = (et * 1000) / es;
  1179. mmc->ssr.erase_offset = eo * 1000;
  1180. }
  1181. } else {
  1182. pr_debug("Invalid Allocation Unit Size.\n");
  1183. }
  1184. return 0;
  1185. }
  1186. #endif
  1187. /* frequency bases */
  1188. /* divided by 10 to be nice to platforms without floating point */
  1189. static const int fbase[] = {
  1190. 10000,
  1191. 100000,
  1192. 1000000,
  1193. 10000000,
  1194. };
  1195. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  1196. * to platforms without floating point.
  1197. */
  1198. static const u8 multipliers[] = {
  1199. 0, /* reserved */
  1200. 10,
  1201. 12,
  1202. 13,
  1203. 15,
  1204. 20,
  1205. 25,
  1206. 30,
  1207. 35,
  1208. 40,
  1209. 45,
  1210. 50,
  1211. 55,
  1212. 60,
  1213. 70,
  1214. 80,
  1215. };
  1216. static inline int bus_width(uint cap)
  1217. {
  1218. if (cap == MMC_MODE_8BIT)
  1219. return 8;
  1220. if (cap == MMC_MODE_4BIT)
  1221. return 4;
  1222. if (cap == MMC_MODE_1BIT)
  1223. return 1;
  1224. pr_warn("invalid bus witdh capability 0x%x\n", cap);
  1225. return 0;
  1226. }
  1227. #if !CONFIG_IS_ENABLED(DM_MMC)
  1228. #ifdef MMC_SUPPORTS_TUNING
  1229. static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
  1230. {
  1231. return -ENOTSUPP;
  1232. }
  1233. #endif
  1234. static void mmc_send_init_stream(struct mmc *mmc)
  1235. {
  1236. }
  1237. static int mmc_set_ios(struct mmc *mmc)
  1238. {
  1239. int ret = 0;
  1240. if (mmc->cfg->ops->set_ios)
  1241. ret = mmc->cfg->ops->set_ios(mmc);
  1242. return ret;
  1243. }
  1244. #endif
  1245. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
  1246. {
  1247. if (!disable) {
  1248. if (clock > mmc->cfg->f_max)
  1249. clock = mmc->cfg->f_max;
  1250. if (clock < mmc->cfg->f_min)
  1251. clock = mmc->cfg->f_min;
  1252. }
  1253. mmc->clock = clock;
  1254. mmc->clk_disable = disable;
  1255. debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
  1256. return mmc_set_ios(mmc);
  1257. }
  1258. static int mmc_set_bus_width(struct mmc *mmc, uint width)
  1259. {
  1260. mmc->bus_width = width;
  1261. return mmc_set_ios(mmc);
  1262. }
  1263. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  1264. /*
  1265. * helper function to display the capabilities in a human
  1266. * friendly manner. The capabilities include bus width and
  1267. * supported modes.
  1268. */
  1269. void mmc_dump_capabilities(const char *text, uint caps)
  1270. {
  1271. enum bus_mode mode;
  1272. pr_debug("%s: widths [", text);
  1273. if (caps & MMC_MODE_8BIT)
  1274. pr_debug("8, ");
  1275. if (caps & MMC_MODE_4BIT)
  1276. pr_debug("4, ");
  1277. if (caps & MMC_MODE_1BIT)
  1278. pr_debug("1, ");
  1279. pr_debug("\b\b] modes [");
  1280. for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
  1281. if (MMC_CAP(mode) & caps)
  1282. pr_debug("%s, ", mmc_mode_name(mode));
  1283. pr_debug("\b\b]\n");
  1284. }
  1285. #endif
  1286. struct mode_width_tuning {
  1287. enum bus_mode mode;
  1288. uint widths;
  1289. #ifdef MMC_SUPPORTS_TUNING
  1290. uint tuning;
  1291. #endif
  1292. };
  1293. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1294. int mmc_voltage_to_mv(enum mmc_voltage voltage)
  1295. {
  1296. switch (voltage) {
  1297. case MMC_SIGNAL_VOLTAGE_000: return 0;
  1298. case MMC_SIGNAL_VOLTAGE_330: return 3300;
  1299. case MMC_SIGNAL_VOLTAGE_180: return 1800;
  1300. case MMC_SIGNAL_VOLTAGE_120: return 1200;
  1301. }
  1302. return -EINVAL;
  1303. }
  1304. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1305. {
  1306. int err;
  1307. if (mmc->signal_voltage == signal_voltage)
  1308. return 0;
  1309. mmc->signal_voltage = signal_voltage;
  1310. err = mmc_set_ios(mmc);
  1311. if (err)
  1312. pr_debug("unable to set voltage (err %d)\n", err);
  1313. return err;
  1314. }
  1315. #else
  1316. static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1317. {
  1318. return 0;
  1319. }
  1320. #endif
  1321. static const struct mode_width_tuning sd_modes_by_pref[] = {
  1322. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1323. #ifdef MMC_SUPPORTS_TUNING
  1324. {
  1325. .mode = UHS_SDR104,
  1326. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1327. .tuning = MMC_CMD_SEND_TUNING_BLOCK
  1328. },
  1329. #endif
  1330. {
  1331. .mode = UHS_SDR50,
  1332. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1333. },
  1334. {
  1335. .mode = UHS_DDR50,
  1336. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1337. },
  1338. {
  1339. .mode = UHS_SDR25,
  1340. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1341. },
  1342. #endif
  1343. {
  1344. .mode = SD_HS,
  1345. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1346. },
  1347. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1348. {
  1349. .mode = UHS_SDR12,
  1350. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1351. },
  1352. #endif
  1353. {
  1354. .mode = SD_LEGACY,
  1355. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1356. }
  1357. };
  1358. #define for_each_sd_mode_by_pref(caps, mwt) \
  1359. for (mwt = sd_modes_by_pref;\
  1360. mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
  1361. mwt++) \
  1362. if (caps & MMC_CAP(mwt->mode))
  1363. static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1364. {
  1365. int err;
  1366. uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
  1367. const struct mode_width_tuning *mwt;
  1368. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1369. bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
  1370. #else
  1371. bool uhs_en = false;
  1372. #endif
  1373. uint caps;
  1374. #ifdef DEBUG
  1375. mmc_dump_capabilities("sd card", card_caps);
  1376. mmc_dump_capabilities("host", mmc->host_caps);
  1377. #endif
  1378. /* Restrict card's capabilities by what the host can do */
  1379. caps = card_caps & mmc->host_caps;
  1380. if (!uhs_en)
  1381. caps &= ~UHS_CAPS;
  1382. for_each_sd_mode_by_pref(caps, mwt) {
  1383. uint *w;
  1384. for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
  1385. if (*w & caps & mwt->widths) {
  1386. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1387. mmc_mode_name(mwt->mode),
  1388. bus_width(*w),
  1389. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1390. /* configure the bus width (card + host) */
  1391. err = sd_select_bus_width(mmc, bus_width(*w));
  1392. if (err)
  1393. goto error;
  1394. mmc_set_bus_width(mmc, bus_width(*w));
  1395. /* configure the bus mode (card) */
  1396. err = sd_set_card_speed(mmc, mwt->mode);
  1397. if (err)
  1398. goto error;
  1399. /* configure the bus mode (host) */
  1400. mmc_select_mode(mmc, mwt->mode);
  1401. mmc_set_clock(mmc, mmc->tran_speed,
  1402. MMC_CLK_ENABLE);
  1403. #ifdef MMC_SUPPORTS_TUNING
  1404. /* execute tuning if needed */
  1405. if (mwt->tuning && !mmc_host_is_spi(mmc)) {
  1406. err = mmc_execute_tuning(mmc,
  1407. mwt->tuning);
  1408. if (err) {
  1409. pr_debug("tuning failed\n");
  1410. goto error;
  1411. }
  1412. }
  1413. #endif
  1414. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1415. err = sd_read_ssr(mmc);
  1416. if (err)
  1417. pr_warn("unable to read ssr\n");
  1418. #endif
  1419. if (!err)
  1420. return 0;
  1421. error:
  1422. /* revert to a safer bus speed */
  1423. mmc_select_mode(mmc, SD_LEGACY);
  1424. mmc_set_clock(mmc, mmc->tran_speed,
  1425. MMC_CLK_ENABLE);
  1426. }
  1427. }
  1428. }
  1429. pr_err("unable to select a mode\n");
  1430. return -ENOTSUPP;
  1431. }
  1432. /*
  1433. * read the compare the part of ext csd that is constant.
  1434. * This can be used to check that the transfer is working
  1435. * as expected.
  1436. */
  1437. static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
  1438. {
  1439. int err;
  1440. const u8 *ext_csd = mmc->ext_csd;
  1441. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  1442. if (mmc->version < MMC_VERSION_4)
  1443. return 0;
  1444. err = mmc_send_ext_csd(mmc, test_csd);
  1445. if (err)
  1446. return err;
  1447. /* Only compare read only fields */
  1448. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1449. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1450. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1451. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1452. ext_csd[EXT_CSD_REV]
  1453. == test_csd[EXT_CSD_REV] &&
  1454. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1455. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1456. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1457. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1458. return 0;
  1459. return -EBADMSG;
  1460. }
  1461. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1462. static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1463. uint32_t allowed_mask)
  1464. {
  1465. u32 card_mask = 0;
  1466. switch (mode) {
  1467. case MMC_HS_200:
  1468. if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
  1469. card_mask |= MMC_SIGNAL_VOLTAGE_180;
  1470. if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
  1471. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1472. break;
  1473. case MMC_DDR_52:
  1474. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  1475. card_mask |= MMC_SIGNAL_VOLTAGE_330 |
  1476. MMC_SIGNAL_VOLTAGE_180;
  1477. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
  1478. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1479. break;
  1480. default:
  1481. card_mask |= MMC_SIGNAL_VOLTAGE_330;
  1482. break;
  1483. }
  1484. while (card_mask & allowed_mask) {
  1485. enum mmc_voltage best_match;
  1486. best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
  1487. if (!mmc_set_signal_voltage(mmc, best_match))
  1488. return 0;
  1489. allowed_mask &= ~best_match;
  1490. }
  1491. return -ENOTSUPP;
  1492. }
  1493. #else
  1494. static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1495. uint32_t allowed_mask)
  1496. {
  1497. return 0;
  1498. }
  1499. #endif
  1500. static const struct mode_width_tuning mmc_modes_by_pref[] = {
  1501. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  1502. {
  1503. .mode = MMC_HS_200,
  1504. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1505. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1506. },
  1507. #endif
  1508. {
  1509. .mode = MMC_DDR_52,
  1510. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1511. },
  1512. {
  1513. .mode = MMC_HS_52,
  1514. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1515. },
  1516. {
  1517. .mode = MMC_HS,
  1518. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1519. },
  1520. {
  1521. .mode = MMC_LEGACY,
  1522. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1523. }
  1524. };
  1525. #define for_each_mmc_mode_by_pref(caps, mwt) \
  1526. for (mwt = mmc_modes_by_pref;\
  1527. mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
  1528. mwt++) \
  1529. if (caps & MMC_CAP(mwt->mode))
  1530. static const struct ext_csd_bus_width {
  1531. uint cap;
  1532. bool is_ddr;
  1533. uint ext_csd_bits;
  1534. } ext_csd_bus_width[] = {
  1535. {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
  1536. {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
  1537. {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
  1538. {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
  1539. {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
  1540. };
  1541. #define for_each_supported_width(caps, ddr, ecbv) \
  1542. for (ecbv = ext_csd_bus_width;\
  1543. ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
  1544. ecbv++) \
  1545. if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
  1546. static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1547. {
  1548. int err;
  1549. const struct mode_width_tuning *mwt;
  1550. const struct ext_csd_bus_width *ecbw;
  1551. #ifdef DEBUG
  1552. mmc_dump_capabilities("mmc", card_caps);
  1553. mmc_dump_capabilities("host", mmc->host_caps);
  1554. #endif
  1555. /* Restrict card's capabilities by what the host can do */
  1556. card_caps &= mmc->host_caps;
  1557. /* Only version 4 of MMC supports wider bus widths */
  1558. if (mmc->version < MMC_VERSION_4)
  1559. return 0;
  1560. if (!mmc->ext_csd) {
  1561. pr_debug("No ext_csd found!\n"); /* this should enver happen */
  1562. return -ENOTSUPP;
  1563. }
  1564. mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
  1565. for_each_mmc_mode_by_pref(card_caps, mwt) {
  1566. for_each_supported_width(card_caps & mwt->widths,
  1567. mmc_is_mode_ddr(mwt->mode), ecbw) {
  1568. enum mmc_voltage old_voltage;
  1569. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1570. mmc_mode_name(mwt->mode),
  1571. bus_width(ecbw->cap),
  1572. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1573. old_voltage = mmc->signal_voltage;
  1574. err = mmc_set_lowest_voltage(mmc, mwt->mode,
  1575. MMC_ALL_SIGNAL_VOLTAGE);
  1576. if (err)
  1577. continue;
  1578. /* configure the bus width (card + host) */
  1579. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1580. EXT_CSD_BUS_WIDTH,
  1581. ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
  1582. if (err)
  1583. goto error;
  1584. mmc_set_bus_width(mmc, bus_width(ecbw->cap));
  1585. /* configure the bus speed (card) */
  1586. err = mmc_set_card_speed(mmc, mwt->mode);
  1587. if (err)
  1588. goto error;
  1589. /*
  1590. * configure the bus width AND the ddr mode (card)
  1591. * The host side will be taken care of in the next step
  1592. */
  1593. if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
  1594. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1595. EXT_CSD_BUS_WIDTH,
  1596. ecbw->ext_csd_bits);
  1597. if (err)
  1598. goto error;
  1599. }
  1600. /* configure the bus mode (host) */
  1601. mmc_select_mode(mmc, mwt->mode);
  1602. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1603. #ifdef MMC_SUPPORTS_TUNING
  1604. /* execute tuning if needed */
  1605. if (mwt->tuning) {
  1606. err = mmc_execute_tuning(mmc, mwt->tuning);
  1607. if (err) {
  1608. pr_debug("tuning failed\n");
  1609. goto error;
  1610. }
  1611. }
  1612. #endif
  1613. /* do a transfer to check the configuration */
  1614. err = mmc_read_and_compare_ext_csd(mmc);
  1615. if (!err)
  1616. return 0;
  1617. error:
  1618. mmc_set_signal_voltage(mmc, old_voltage);
  1619. /* if an error occured, revert to a safer bus mode */
  1620. mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1621. EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
  1622. mmc_select_mode(mmc, MMC_LEGACY);
  1623. mmc_set_bus_width(mmc, 1);
  1624. }
  1625. }
  1626. pr_err("unable to select a mode\n");
  1627. return -ENOTSUPP;
  1628. }
  1629. static int mmc_startup_v4(struct mmc *mmc)
  1630. {
  1631. int err, i;
  1632. u64 capacity;
  1633. bool has_parts = false;
  1634. bool part_completed;
  1635. static const u32 mmc_versions[] = {
  1636. MMC_VERSION_4,
  1637. MMC_VERSION_4_1,
  1638. MMC_VERSION_4_2,
  1639. MMC_VERSION_4_3,
  1640. MMC_VERSION_4_4,
  1641. MMC_VERSION_4_41,
  1642. MMC_VERSION_4_5,
  1643. MMC_VERSION_5_0,
  1644. MMC_VERSION_5_1
  1645. };
  1646. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  1647. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
  1648. return 0;
  1649. /* check ext_csd version and capacity */
  1650. err = mmc_send_ext_csd(mmc, ext_csd);
  1651. if (err)
  1652. goto error;
  1653. /* store the ext csd for future reference */
  1654. if (!mmc->ext_csd)
  1655. mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
  1656. if (!mmc->ext_csd)
  1657. return -ENOMEM;
  1658. memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
  1659. if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
  1660. return -EINVAL;
  1661. mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
  1662. if (mmc->version >= MMC_VERSION_4_2) {
  1663. /*
  1664. * According to the JEDEC Standard, the value of
  1665. * ext_csd's capacity is valid if the value is more
  1666. * than 2GB
  1667. */
  1668. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  1669. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  1670. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  1671. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  1672. capacity *= MMC_MAX_BLOCK_LEN;
  1673. if ((capacity >> 20) > 2 * 1024)
  1674. mmc->capacity_user = capacity;
  1675. }
  1676. /* The partition data may be non-zero but it is only
  1677. * effective if PARTITION_SETTING_COMPLETED is set in
  1678. * EXT_CSD, so ignore any data if this bit is not set,
  1679. * except for enabling the high-capacity group size
  1680. * definition (see below).
  1681. */
  1682. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  1683. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1684. /* store the partition info of emmc */
  1685. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  1686. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  1687. ext_csd[EXT_CSD_BOOT_MULT])
  1688. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  1689. if (part_completed &&
  1690. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  1691. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  1692. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  1693. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1694. for (i = 0; i < 4; i++) {
  1695. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1696. uint mult = (ext_csd[idx + 2] << 16) +
  1697. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1698. if (mult)
  1699. has_parts = true;
  1700. if (!part_completed)
  1701. continue;
  1702. mmc->capacity_gp[i] = mult;
  1703. mmc->capacity_gp[i] *=
  1704. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1705. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1706. mmc->capacity_gp[i] <<= 19;
  1707. }
  1708. #ifndef CONFIG_SPL_BUILD
  1709. if (part_completed) {
  1710. mmc->enh_user_size =
  1711. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
  1712. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
  1713. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1714. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1715. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1716. mmc->enh_user_size <<= 19;
  1717. mmc->enh_user_start =
  1718. (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
  1719. (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
  1720. (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
  1721. ext_csd[EXT_CSD_ENH_START_ADDR];
  1722. if (mmc->high_capacity)
  1723. mmc->enh_user_start <<= 9;
  1724. }
  1725. #endif
  1726. /*
  1727. * Host needs to enable ERASE_GRP_DEF bit if device is
  1728. * partitioned. This bit will be lost every time after a reset
  1729. * or power off. This will affect erase size.
  1730. */
  1731. if (part_completed)
  1732. has_parts = true;
  1733. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1734. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1735. has_parts = true;
  1736. if (has_parts) {
  1737. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1738. EXT_CSD_ERASE_GROUP_DEF, 1);
  1739. if (err)
  1740. goto error;
  1741. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1742. }
  1743. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  1744. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1745. /* Read out group size from ext_csd */
  1746. mmc->erase_grp_size =
  1747. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  1748. #endif
  1749. /*
  1750. * if high capacity and partition setting completed
  1751. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1752. * JEDEC Standard JESD84-B45, 6.2.4
  1753. */
  1754. if (mmc->high_capacity && part_completed) {
  1755. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1756. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1757. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  1758. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  1759. capacity *= MMC_MAX_BLOCK_LEN;
  1760. mmc->capacity_user = capacity;
  1761. }
  1762. }
  1763. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1764. else {
  1765. /* Calculate the group size from the csd value. */
  1766. int erase_gsz, erase_gmul;
  1767. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  1768. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  1769. mmc->erase_grp_size = (erase_gsz + 1)
  1770. * (erase_gmul + 1);
  1771. }
  1772. #endif
  1773. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  1774. mmc->hc_wp_grp_size = 1024
  1775. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1776. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1777. #endif
  1778. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  1779. return 0;
  1780. error:
  1781. if (mmc->ext_csd) {
  1782. free(mmc->ext_csd);
  1783. mmc->ext_csd = NULL;
  1784. }
  1785. return err;
  1786. }
  1787. static int mmc_startup(struct mmc *mmc)
  1788. {
  1789. int err, i;
  1790. uint mult, freq;
  1791. u64 cmult, csize;
  1792. struct mmc_cmd cmd;
  1793. struct blk_desc *bdesc;
  1794. #ifdef CONFIG_MMC_SPI_CRC_ON
  1795. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  1796. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  1797. cmd.resp_type = MMC_RSP_R1;
  1798. cmd.cmdarg = 1;
  1799. err = mmc_send_cmd(mmc, &cmd, NULL);
  1800. if (err)
  1801. return err;
  1802. }
  1803. #endif
  1804. /* Put the Card in Identify Mode */
  1805. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  1806. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  1807. cmd.resp_type = MMC_RSP_R2;
  1808. cmd.cmdarg = 0;
  1809. err = mmc_send_cmd(mmc, &cmd, NULL);
  1810. #ifdef CONFIG_MMC_QUIRKS
  1811. if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
  1812. int retries = 4;
  1813. /*
  1814. * It has been seen that SEND_CID may fail on the first
  1815. * attempt, let's try a few more time
  1816. */
  1817. do {
  1818. err = mmc_send_cmd(mmc, &cmd, NULL);
  1819. if (!err)
  1820. break;
  1821. } while (retries--);
  1822. }
  1823. #endif
  1824. if (err)
  1825. return err;
  1826. memcpy(mmc->cid, cmd.response, 16);
  1827. /*
  1828. * For MMC cards, set the Relative Address.
  1829. * For SD cards, get the Relatvie Address.
  1830. * This also puts the cards into Standby State
  1831. */
  1832. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  1833. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  1834. cmd.cmdarg = mmc->rca << 16;
  1835. cmd.resp_type = MMC_RSP_R6;
  1836. err = mmc_send_cmd(mmc, &cmd, NULL);
  1837. if (err)
  1838. return err;
  1839. if (IS_SD(mmc))
  1840. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  1841. }
  1842. /* Get the Card-Specific Data */
  1843. cmd.cmdidx = MMC_CMD_SEND_CSD;
  1844. cmd.resp_type = MMC_RSP_R2;
  1845. cmd.cmdarg = mmc->rca << 16;
  1846. err = mmc_send_cmd(mmc, &cmd, NULL);
  1847. if (err)
  1848. return err;
  1849. mmc->csd[0] = cmd.response[0];
  1850. mmc->csd[1] = cmd.response[1];
  1851. mmc->csd[2] = cmd.response[2];
  1852. mmc->csd[3] = cmd.response[3];
  1853. if (mmc->version == MMC_VERSION_UNKNOWN) {
  1854. int version = (cmd.response[0] >> 26) & 0xf;
  1855. switch (version) {
  1856. case 0:
  1857. mmc->version = MMC_VERSION_1_2;
  1858. break;
  1859. case 1:
  1860. mmc->version = MMC_VERSION_1_4;
  1861. break;
  1862. case 2:
  1863. mmc->version = MMC_VERSION_2_2;
  1864. break;
  1865. case 3:
  1866. mmc->version = MMC_VERSION_3;
  1867. break;
  1868. case 4:
  1869. mmc->version = MMC_VERSION_4;
  1870. break;
  1871. default:
  1872. mmc->version = MMC_VERSION_1_2;
  1873. break;
  1874. }
  1875. }
  1876. /* divide frequency by 10, since the mults are 10x bigger */
  1877. freq = fbase[(cmd.response[0] & 0x7)];
  1878. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  1879. mmc->legacy_speed = freq * mult;
  1880. mmc_select_mode(mmc, MMC_LEGACY);
  1881. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  1882. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  1883. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1884. if (IS_SD(mmc))
  1885. mmc->write_bl_len = mmc->read_bl_len;
  1886. else
  1887. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  1888. #endif
  1889. if (mmc->high_capacity) {
  1890. csize = (mmc->csd[1] & 0x3f) << 16
  1891. | (mmc->csd[2] & 0xffff0000) >> 16;
  1892. cmult = 8;
  1893. } else {
  1894. csize = (mmc->csd[1] & 0x3ff) << 2
  1895. | (mmc->csd[2] & 0xc0000000) >> 30;
  1896. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  1897. }
  1898. mmc->capacity_user = (csize + 1) << (cmult + 2);
  1899. mmc->capacity_user *= mmc->read_bl_len;
  1900. mmc->capacity_boot = 0;
  1901. mmc->capacity_rpmb = 0;
  1902. for (i = 0; i < 4; i++)
  1903. mmc->capacity_gp[i] = 0;
  1904. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  1905. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1906. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1907. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  1908. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1909. #endif
  1910. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  1911. cmd.cmdidx = MMC_CMD_SET_DSR;
  1912. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  1913. cmd.resp_type = MMC_RSP_NONE;
  1914. if (mmc_send_cmd(mmc, &cmd, NULL))
  1915. pr_warn("MMC: SET_DSR failed\n");
  1916. }
  1917. /* Select the card, and put it into Transfer Mode */
  1918. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  1919. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  1920. cmd.resp_type = MMC_RSP_R1;
  1921. cmd.cmdarg = mmc->rca << 16;
  1922. err = mmc_send_cmd(mmc, &cmd, NULL);
  1923. if (err)
  1924. return err;
  1925. }
  1926. /*
  1927. * For SD, its erase group is always one sector
  1928. */
  1929. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1930. mmc->erase_grp_size = 1;
  1931. #endif
  1932. mmc->part_config = MMCPART_NOAVAILABLE;
  1933. err = mmc_startup_v4(mmc);
  1934. if (err)
  1935. return err;
  1936. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  1937. if (err)
  1938. return err;
  1939. if (IS_SD(mmc)) {
  1940. err = sd_get_capabilities(mmc);
  1941. if (err)
  1942. return err;
  1943. err = sd_select_mode_and_width(mmc, mmc->card_caps);
  1944. } else {
  1945. err = mmc_get_capabilities(mmc);
  1946. if (err)
  1947. return err;
  1948. mmc_select_mode_and_width(mmc, mmc->card_caps);
  1949. }
  1950. if (err)
  1951. return err;
  1952. mmc->best_mode = mmc->selected_mode;
  1953. /* Fix the block length for DDR mode */
  1954. if (mmc->ddr_mode) {
  1955. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1956. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1957. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1958. #endif
  1959. }
  1960. /* fill in device description */
  1961. bdesc = mmc_get_blk_desc(mmc);
  1962. bdesc->lun = 0;
  1963. bdesc->hwpart = 0;
  1964. bdesc->type = 0;
  1965. bdesc->blksz = mmc->read_bl_len;
  1966. bdesc->log2blksz = LOG2(bdesc->blksz);
  1967. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  1968. #if !defined(CONFIG_SPL_BUILD) || \
  1969. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  1970. !defined(CONFIG_USE_TINY_PRINTF))
  1971. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  1972. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  1973. (mmc->cid[3] >> 16) & 0xffff);
  1974. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  1975. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  1976. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  1977. (mmc->cid[2] >> 24) & 0xff);
  1978. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  1979. (mmc->cid[2] >> 16) & 0xf);
  1980. #else
  1981. bdesc->vendor[0] = 0;
  1982. bdesc->product[0] = 0;
  1983. bdesc->revision[0] = 0;
  1984. #endif
  1985. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
  1986. part_init(bdesc);
  1987. #endif
  1988. return 0;
  1989. }
  1990. static int mmc_send_if_cond(struct mmc *mmc)
  1991. {
  1992. struct mmc_cmd cmd;
  1993. int err;
  1994. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  1995. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  1996. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  1997. cmd.resp_type = MMC_RSP_R7;
  1998. err = mmc_send_cmd(mmc, &cmd, NULL);
  1999. if (err)
  2000. return err;
  2001. if ((cmd.response[0] & 0xff) != 0xaa)
  2002. return -EOPNOTSUPP;
  2003. else
  2004. mmc->version = SD_VERSION_2;
  2005. return 0;
  2006. }
  2007. #if !CONFIG_IS_ENABLED(DM_MMC)
  2008. /* board-specific MMC power initializations. */
  2009. __weak void board_mmc_power_init(void)
  2010. {
  2011. }
  2012. #endif
  2013. static int mmc_power_init(struct mmc *mmc)
  2014. {
  2015. #if CONFIG_IS_ENABLED(DM_MMC)
  2016. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  2017. int ret;
  2018. ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
  2019. &mmc->vmmc_supply);
  2020. if (ret)
  2021. pr_debug("%s: No vmmc supply\n", mmc->dev->name);
  2022. ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
  2023. &mmc->vqmmc_supply);
  2024. if (ret)
  2025. pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
  2026. #endif
  2027. #else /* !CONFIG_DM_MMC */
  2028. /*
  2029. * Driver model should use a regulator, as above, rather than calling
  2030. * out to board code.
  2031. */
  2032. board_mmc_power_init();
  2033. #endif
  2034. return 0;
  2035. }
  2036. /*
  2037. * put the host in the initial state:
  2038. * - turn on Vdd (card power supply)
  2039. * - configure the bus width and clock to minimal values
  2040. */
  2041. static void mmc_set_initial_state(struct mmc *mmc)
  2042. {
  2043. int err;
  2044. /* First try to set 3.3V. If it fails set to 1.8V */
  2045. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
  2046. if (err != 0)
  2047. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  2048. if (err != 0)
  2049. pr_warn("mmc: failed to set signal voltage\n");
  2050. mmc_select_mode(mmc, MMC_LEGACY);
  2051. mmc_set_bus_width(mmc, 1);
  2052. mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
  2053. }
  2054. static int mmc_power_on(struct mmc *mmc)
  2055. {
  2056. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2057. if (mmc->vmmc_supply) {
  2058. int ret = regulator_set_enable(mmc->vmmc_supply, true);
  2059. if (ret) {
  2060. puts("Error enabling VMMC supply\n");
  2061. return ret;
  2062. }
  2063. }
  2064. #endif
  2065. return 0;
  2066. }
  2067. static int mmc_power_off(struct mmc *mmc)
  2068. {
  2069. mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
  2070. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2071. if (mmc->vmmc_supply) {
  2072. int ret = regulator_set_enable(mmc->vmmc_supply, false);
  2073. if (ret) {
  2074. pr_debug("Error disabling VMMC supply\n");
  2075. return ret;
  2076. }
  2077. }
  2078. #endif
  2079. return 0;
  2080. }
  2081. static int mmc_power_cycle(struct mmc *mmc)
  2082. {
  2083. int ret;
  2084. ret = mmc_power_off(mmc);
  2085. if (ret)
  2086. return ret;
  2087. /*
  2088. * SD spec recommends at least 1ms of delay. Let's wait for 2ms
  2089. * to be on the safer side.
  2090. */
  2091. udelay(2000);
  2092. return mmc_power_on(mmc);
  2093. }
  2094. int mmc_start_init(struct mmc *mmc)
  2095. {
  2096. bool no_card;
  2097. bool uhs_en = supports_uhs(mmc->cfg->host_caps);
  2098. int err;
  2099. /*
  2100. * all hosts are capable of 1 bit bus-width and able to use the legacy
  2101. * timings.
  2102. */
  2103. mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
  2104. MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
  2105. #if !defined(CONFIG_MMC_BROKEN_CD)
  2106. /* we pretend there's no card when init is NULL */
  2107. no_card = mmc_getcd(mmc) == 0;
  2108. #else
  2109. no_card = 0;
  2110. #endif
  2111. #if !CONFIG_IS_ENABLED(DM_MMC)
  2112. no_card = no_card || (mmc->cfg->ops->init == NULL);
  2113. #endif
  2114. if (no_card) {
  2115. mmc->has_init = 0;
  2116. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2117. pr_err("MMC: no card present\n");
  2118. #endif
  2119. return -ENOMEDIUM;
  2120. }
  2121. if (mmc->has_init)
  2122. return 0;
  2123. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  2124. mmc_adapter_card_type_ident();
  2125. #endif
  2126. err = mmc_power_init(mmc);
  2127. if (err)
  2128. return err;
  2129. #ifdef CONFIG_MMC_QUIRKS
  2130. mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
  2131. MMC_QUIRK_RETRY_SEND_CID;
  2132. #endif
  2133. err = mmc_power_cycle(mmc);
  2134. if (err) {
  2135. /*
  2136. * if power cycling is not supported, we should not try
  2137. * to use the UHS modes, because we wouldn't be able to
  2138. * recover from an error during the UHS initialization.
  2139. */
  2140. pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  2141. uhs_en = false;
  2142. mmc->host_caps &= ~UHS_CAPS;
  2143. err = mmc_power_on(mmc);
  2144. }
  2145. if (err)
  2146. return err;
  2147. #if CONFIG_IS_ENABLED(DM_MMC)
  2148. /* The device has already been probed ready for use */
  2149. #else
  2150. /* made sure it's not NULL earlier */
  2151. err = mmc->cfg->ops->init(mmc);
  2152. if (err)
  2153. return err;
  2154. #endif
  2155. mmc->ddr_mode = 0;
  2156. retry:
  2157. mmc_set_initial_state(mmc);
  2158. mmc_send_init_stream(mmc);
  2159. /* Reset the Card */
  2160. err = mmc_go_idle(mmc);
  2161. if (err)
  2162. return err;
  2163. /* The internal partition reset to user partition(0) at every CMD0*/
  2164. mmc_get_blk_desc(mmc)->hwpart = 0;
  2165. /* Test for SD version 2 */
  2166. err = mmc_send_if_cond(mmc);
  2167. /* Now try to get the SD card's operating condition */
  2168. err = sd_send_op_cond(mmc, uhs_en);
  2169. if (err && uhs_en) {
  2170. uhs_en = false;
  2171. mmc_power_cycle(mmc);
  2172. goto retry;
  2173. }
  2174. /* If the command timed out, we check for an MMC card */
  2175. if (err == -ETIMEDOUT) {
  2176. err = mmc_send_op_cond(mmc);
  2177. if (err) {
  2178. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2179. pr_err("Card did not respond to voltage select!\n");
  2180. #endif
  2181. return -EOPNOTSUPP;
  2182. }
  2183. }
  2184. if (!err)
  2185. mmc->init_in_progress = 1;
  2186. return err;
  2187. }
  2188. static int mmc_complete_init(struct mmc *mmc)
  2189. {
  2190. int err = 0;
  2191. mmc->init_in_progress = 0;
  2192. if (mmc->op_cond_pending)
  2193. err = mmc_complete_op_cond(mmc);
  2194. if (!err)
  2195. err = mmc_startup(mmc);
  2196. if (err)
  2197. mmc->has_init = 0;
  2198. else
  2199. mmc->has_init = 1;
  2200. return err;
  2201. }
  2202. int mmc_init(struct mmc *mmc)
  2203. {
  2204. int err = 0;
  2205. __maybe_unused ulong start;
  2206. #if CONFIG_IS_ENABLED(DM_MMC)
  2207. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  2208. upriv->mmc = mmc;
  2209. #endif
  2210. if (mmc->has_init)
  2211. return 0;
  2212. start = get_timer(0);
  2213. if (!mmc->init_in_progress)
  2214. err = mmc_start_init(mmc);
  2215. if (!err)
  2216. err = mmc_complete_init(mmc);
  2217. if (err)
  2218. pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
  2219. return err;
  2220. }
  2221. int mmc_set_dsr(struct mmc *mmc, u16 val)
  2222. {
  2223. mmc->dsr = val;
  2224. return 0;
  2225. }
  2226. /* CPU-specific MMC initializations */
  2227. __weak int cpu_mmc_init(bd_t *bis)
  2228. {
  2229. return -1;
  2230. }
  2231. /* board-specific MMC initializations. */
  2232. __weak int board_mmc_init(bd_t *bis)
  2233. {
  2234. return -1;
  2235. }
  2236. void mmc_set_preinit(struct mmc *mmc, int preinit)
  2237. {
  2238. mmc->preinit = preinit;
  2239. }
  2240. #if CONFIG_IS_ENABLED(DM_MMC)
  2241. static int mmc_probe(bd_t *bis)
  2242. {
  2243. int ret, i;
  2244. struct uclass *uc;
  2245. struct udevice *dev;
  2246. ret = uclass_get(UCLASS_MMC, &uc);
  2247. if (ret)
  2248. return ret;
  2249. /*
  2250. * Try to add them in sequence order. Really with driver model we
  2251. * should allow holes, but the current MMC list does not allow that.
  2252. * So if we request 0, 1, 3 we will get 0, 1, 2.
  2253. */
  2254. for (i = 0; ; i++) {
  2255. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  2256. if (ret == -ENODEV)
  2257. break;
  2258. }
  2259. uclass_foreach_dev(dev, uc) {
  2260. ret = device_probe(dev);
  2261. if (ret)
  2262. pr_err("%s - probe failed: %d\n", dev->name, ret);
  2263. }
  2264. return 0;
  2265. }
  2266. #else
  2267. static int mmc_probe(bd_t *bis)
  2268. {
  2269. if (board_mmc_init(bis) < 0)
  2270. cpu_mmc_init(bis);
  2271. return 0;
  2272. }
  2273. #endif
  2274. int mmc_initialize(bd_t *bis)
  2275. {
  2276. static int initialized = 0;
  2277. int ret;
  2278. if (initialized) /* Avoid initializing mmc multiple times */
  2279. return 0;
  2280. initialized = 1;
  2281. #if !CONFIG_IS_ENABLED(BLK)
  2282. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2283. mmc_list_init();
  2284. #endif
  2285. #endif
  2286. ret = mmc_probe(bis);
  2287. if (ret)
  2288. return ret;
  2289. #ifndef CONFIG_SPL_BUILD
  2290. print_mmc_devices(',');
  2291. #endif
  2292. mmc_do_preinit();
  2293. return 0;
  2294. }
  2295. #ifdef CONFIG_CMD_BKOPS_ENABLE
  2296. int mmc_set_bkops_enable(struct mmc *mmc)
  2297. {
  2298. int err;
  2299. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  2300. err = mmc_send_ext_csd(mmc, ext_csd);
  2301. if (err) {
  2302. puts("Could not get ext_csd register values\n");
  2303. return err;
  2304. }
  2305. if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
  2306. puts("Background operations not supported on device\n");
  2307. return -EMEDIUMTYPE;
  2308. }
  2309. if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
  2310. puts("Background operations already enabled\n");
  2311. return 0;
  2312. }
  2313. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
  2314. if (err) {
  2315. puts("Failed to enable manual background operations\n");
  2316. return err;
  2317. }
  2318. puts("Enabled manual background operations\n");
  2319. return 0;
  2320. }
  2321. #endif