zynqmp.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <sata.h>
  8. #include <ahci.h>
  9. #include <scsi.h>
  10. #include <malloc.h>
  11. #include <wdt.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/arch/psu_init_gpl.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass.h>
  18. #include <usb.h>
  19. #include <dwc3-uboot.h>
  20. #include <zynqmppl.h>
  21. #include <i2c.h>
  22. #include <g_dnl.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  25. static struct udevice *watchdog_dev;
  26. #endif
  27. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  28. !defined(CONFIG_SPL_BUILD)
  29. static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  30. static const struct {
  31. u32 id;
  32. u32 ver;
  33. char *name;
  34. bool evexists;
  35. } zynqmp_devices[] = {
  36. {
  37. .id = 0x10,
  38. .name = "3eg",
  39. },
  40. {
  41. .id = 0x10,
  42. .ver = 0x2c,
  43. .name = "3cg",
  44. },
  45. {
  46. .id = 0x11,
  47. .name = "2eg",
  48. },
  49. {
  50. .id = 0x11,
  51. .ver = 0x2c,
  52. .name = "2cg",
  53. },
  54. {
  55. .id = 0x20,
  56. .name = "5ev",
  57. .evexists = 1,
  58. },
  59. {
  60. .id = 0x20,
  61. .ver = 0x100,
  62. .name = "5eg",
  63. .evexists = 1,
  64. },
  65. {
  66. .id = 0x20,
  67. .ver = 0x12c,
  68. .name = "5cg",
  69. },
  70. {
  71. .id = 0x21,
  72. .name = "4ev",
  73. .evexists = 1,
  74. },
  75. {
  76. .id = 0x21,
  77. .ver = 0x100,
  78. .name = "4eg",
  79. .evexists = 1,
  80. },
  81. {
  82. .id = 0x21,
  83. .ver = 0x12c,
  84. .name = "4cg",
  85. },
  86. {
  87. .id = 0x30,
  88. .name = "7ev",
  89. .evexists = 1,
  90. },
  91. {
  92. .id = 0x30,
  93. .ver = 0x100,
  94. .name = "7eg",
  95. .evexists = 1,
  96. },
  97. {
  98. .id = 0x30,
  99. .ver = 0x12c,
  100. .name = "7cg",
  101. },
  102. {
  103. .id = 0x38,
  104. .name = "9eg",
  105. },
  106. {
  107. .id = 0x38,
  108. .ver = 0x2c,
  109. .name = "9cg",
  110. },
  111. {
  112. .id = 0x39,
  113. .name = "6eg",
  114. },
  115. {
  116. .id = 0x39,
  117. .ver = 0x2c,
  118. .name = "6cg",
  119. },
  120. {
  121. .id = 0x40,
  122. .name = "11eg",
  123. },
  124. { /* For testing purpose only */
  125. .id = 0x50,
  126. .ver = 0x2c,
  127. .name = "15cg",
  128. },
  129. {
  130. .id = 0x50,
  131. .name = "15eg",
  132. },
  133. {
  134. .id = 0x58,
  135. .name = "19eg",
  136. },
  137. {
  138. .id = 0x59,
  139. .name = "17eg",
  140. },
  141. {
  142. .id = 0x61,
  143. .name = "21dr",
  144. },
  145. {
  146. .id = 0x63,
  147. .name = "23dr",
  148. },
  149. {
  150. .id = 0x65,
  151. .name = "25dr",
  152. },
  153. {
  154. .id = 0x64,
  155. .name = "27dr",
  156. },
  157. {
  158. .id = 0x60,
  159. .name = "28dr",
  160. },
  161. {
  162. .id = 0x62,
  163. .name = "29dr",
  164. },
  165. };
  166. #endif
  167. int chip_id(unsigned char id)
  168. {
  169. struct pt_regs regs;
  170. int val = -EINVAL;
  171. if (current_el() != 3) {
  172. regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  173. regs.regs[1] = 0;
  174. regs.regs[2] = 0;
  175. regs.regs[3] = 0;
  176. smc_call(&regs);
  177. /*
  178. * SMC returns:
  179. * regs[0][31:0] = status of the operation
  180. * regs[0][63:32] = CSU.IDCODE register
  181. * regs[1][31:0] = CSU.version register
  182. * regs[1][63:32] = CSU.IDCODE2 register
  183. */
  184. switch (id) {
  185. case IDCODE:
  186. regs.regs[0] = upper_32_bits(regs.regs[0]);
  187. regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  188. ZYNQMP_CSU_IDCODE_SVD_MASK;
  189. regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  190. val = regs.regs[0];
  191. break;
  192. case VERSION:
  193. regs.regs[1] = lower_32_bits(regs.regs[1]);
  194. regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
  195. val = regs.regs[1];
  196. break;
  197. case IDCODE2:
  198. regs.regs[1] = lower_32_bits(regs.regs[1]);
  199. regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
  200. val = regs.regs[1];
  201. break;
  202. default:
  203. printf("%s, Invalid Req:0x%x\n", __func__, id);
  204. }
  205. } else {
  206. switch (id) {
  207. case IDCODE:
  208. val = readl(ZYNQMP_CSU_IDCODE_ADDR);
  209. val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  210. ZYNQMP_CSU_IDCODE_SVD_MASK;
  211. val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  212. break;
  213. case VERSION:
  214. val = readl(ZYNQMP_CSU_VER_ADDR);
  215. val &= ZYNQMP_CSU_SILICON_VER_MASK;
  216. break;
  217. default:
  218. printf("%s, Invalid Req:0x%x\n", __func__, id);
  219. }
  220. }
  221. return val;
  222. }
  223. #define ZYNQMP_VERSION_SIZE 9
  224. #define ZYNQMP_PL_STATUS_BIT 9
  225. #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
  226. #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
  227. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  228. !defined(CONFIG_SPL_BUILD)
  229. static char *zynqmp_get_silicon_idcode_name(void)
  230. {
  231. u32 i, id, ver;
  232. char *buf;
  233. static char name[ZYNQMP_VERSION_SIZE];
  234. id = chip_id(IDCODE);
  235. ver = chip_id(IDCODE2);
  236. for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  237. if ((zynqmp_devices[i].id == id) &&
  238. (zynqmp_devices[i].ver == (ver &
  239. ZYNQMP_CSU_VERSION_MASK))) {
  240. strncat(name, "zu", 2);
  241. strncat(name, zynqmp_devices[i].name,
  242. ZYNQMP_VERSION_SIZE - 3);
  243. break;
  244. }
  245. }
  246. if (i >= ARRAY_SIZE(zynqmp_devices))
  247. return "unknown";
  248. if (!zynqmp_devices[i].evexists)
  249. return name;
  250. if (ver & ZYNQMP_PL_STATUS_MASK)
  251. return name;
  252. if (strstr(name, "eg") || strstr(name, "ev")) {
  253. buf = strstr(name, "e");
  254. *buf = '\0';
  255. }
  256. return name;
  257. }
  258. #endif
  259. int board_early_init_f(void)
  260. {
  261. int ret = 0;
  262. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
  263. zynqmp_pmufw_version();
  264. #endif
  265. #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
  266. ret = psu_init();
  267. #endif
  268. #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
  269. /* bss is not cleared at time when watchdog_reset() is called */
  270. watchdog_dev = NULL;
  271. #endif
  272. return ret;
  273. }
  274. int board_init(void)
  275. {
  276. printf("EL Level:\tEL%d\n", current_el());
  277. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  278. !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
  279. defined(CONFIG_SPL_BUILD))
  280. if (current_el() != 3) {
  281. zynqmppl.name = zynqmp_get_silicon_idcode_name();
  282. printf("Chip ID:\t%s\n", zynqmppl.name);
  283. fpga_init();
  284. fpga_add(fpga_xilinx, &zynqmppl);
  285. }
  286. #endif
  287. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  288. if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
  289. puts("Watchdog: Not found!\n");
  290. } else {
  291. wdt_start(watchdog_dev, 0, 0);
  292. puts("Watchdog: Started\n");
  293. }
  294. #endif
  295. return 0;
  296. }
  297. #ifdef CONFIG_WATCHDOG
  298. /* Called by macro WATCHDOG_RESET */
  299. void watchdog_reset(void)
  300. {
  301. # if !defined(CONFIG_SPL_BUILD)
  302. static ulong next_reset;
  303. ulong now;
  304. if (!watchdog_dev)
  305. return;
  306. now = timer_get_us();
  307. /* Do not reset the watchdog too often */
  308. if (now > next_reset) {
  309. wdt_reset(watchdog_dev);
  310. next_reset = now + 1000;
  311. }
  312. # endif
  313. }
  314. #endif
  315. int board_early_init_r(void)
  316. {
  317. u32 val;
  318. if (current_el() != 3)
  319. return 0;
  320. val = readl(&crlapb_base->timestamp_ref_ctrl);
  321. val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  322. if (!val) {
  323. val = readl(&crlapb_base->timestamp_ref_ctrl);
  324. val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  325. writel(val, &crlapb_base->timestamp_ref_ctrl);
  326. /* Program freq register in System counter */
  327. writel(zynqmp_get_system_timer_freq(),
  328. &iou_scntr_secure->base_frequency_id_register);
  329. /* And enable system counter */
  330. writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  331. &iou_scntr_secure->counter_control_register);
  332. }
  333. return 0;
  334. }
  335. int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
  336. {
  337. #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
  338. defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
  339. defined(CONFIG_ZYNQ_EEPROM_BUS)
  340. i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
  341. if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
  342. CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
  343. ethaddr, 6))
  344. printf("I2C EEPROM MAC address read failed\n");
  345. #endif
  346. return 0;
  347. }
  348. unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
  349. char * const argv[])
  350. {
  351. int ret = 0;
  352. if (current_el() > 1) {
  353. smp_kick_all_cpus();
  354. dcache_disable();
  355. armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
  356. ES_TO_AARCH64);
  357. } else {
  358. printf("FAIL: current EL is not above EL1\n");
  359. ret = EINVAL;
  360. }
  361. return ret;
  362. }
  363. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  364. int dram_init_banksize(void)
  365. {
  366. int ret;
  367. ret = fdtdec_setup_memory_banksize();
  368. if (ret)
  369. return ret;
  370. mem_map_fill();
  371. return 0;
  372. }
  373. int dram_init(void)
  374. {
  375. if (fdtdec_setup_memory_size() != 0)
  376. return -EINVAL;
  377. return 0;
  378. }
  379. #else
  380. int dram_init_banksize(void)
  381. {
  382. #if defined(CONFIG_NR_DRAM_BANKS)
  383. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  384. gd->bd->bi_dram[0].size = get_effective_memsize();
  385. #endif
  386. mem_map_fill();
  387. return 0;
  388. }
  389. int dram_init(void)
  390. {
  391. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  392. CONFIG_SYS_SDRAM_SIZE);
  393. return 0;
  394. }
  395. #endif
  396. void reset_cpu(ulong addr)
  397. {
  398. }
  399. int board_late_init(void)
  400. {
  401. u32 reg = 0;
  402. u8 bootmode;
  403. int env_targets_len = 0;
  404. const char *mode;
  405. char *new_targets;
  406. char *env_targets;
  407. int ret;
  408. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  409. debug("Saved variables - Skipping\n");
  410. return 0;
  411. }
  412. ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
  413. if (ret)
  414. return -EINVAL;
  415. if (reg >> BOOT_MODE_ALT_SHIFT)
  416. reg >>= BOOT_MODE_ALT_SHIFT;
  417. bootmode = reg & BOOT_MODES_MASK;
  418. puts("Bootmode: ");
  419. switch (bootmode) {
  420. case USB_MODE:
  421. puts("USB_MODE\n");
  422. mode = "usb";
  423. env_set("modeboot", "usb_dfu_spl");
  424. break;
  425. case JTAG_MODE:
  426. puts("JTAG_MODE\n");
  427. mode = "pxe dhcp";
  428. env_set("modeboot", "jtagboot");
  429. break;
  430. case QSPI_MODE_24BIT:
  431. case QSPI_MODE_32BIT:
  432. mode = "qspi0";
  433. puts("QSPI_MODE\n");
  434. env_set("modeboot", "qspiboot");
  435. break;
  436. case EMMC_MODE:
  437. puts("EMMC_MODE\n");
  438. mode = "mmc0";
  439. env_set("modeboot", "emmcboot");
  440. break;
  441. case SD_MODE:
  442. puts("SD_MODE\n");
  443. mode = "mmc0";
  444. env_set("modeboot", "sdboot");
  445. break;
  446. case SD1_LSHFT_MODE:
  447. puts("LVL_SHFT_");
  448. /* fall through */
  449. case SD_MODE1:
  450. puts("SD_MODE1\n");
  451. #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
  452. mode = "mmc1";
  453. env_set("sdbootdev", "1");
  454. #else
  455. mode = "mmc0";
  456. #endif
  457. env_set("modeboot", "sdboot");
  458. break;
  459. case NAND_MODE:
  460. puts("NAND_MODE\n");
  461. mode = "nand0";
  462. env_set("modeboot", "nandboot");
  463. break;
  464. default:
  465. mode = "";
  466. printf("Invalid Boot Mode:0x%x\n", bootmode);
  467. break;
  468. }
  469. /*
  470. * One terminating char + one byte for space between mode
  471. * and default boot_targets
  472. */
  473. env_targets = env_get("boot_targets");
  474. if (env_targets)
  475. env_targets_len = strlen(env_targets);
  476. new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
  477. sprintf(new_targets, "%s %s", mode,
  478. env_targets ? env_targets : "");
  479. env_set("boot_targets", new_targets);
  480. return 0;
  481. }
  482. int checkboard(void)
  483. {
  484. puts("Board: Xilinx ZynqMP\n");
  485. return 0;
  486. }
  487. #ifdef CONFIG_USB_DWC3
  488. static struct dwc3_device dwc3_device_data0 = {
  489. .maximum_speed = USB_SPEED_HIGH,
  490. .base = ZYNQMP_USB0_XHCI_BASEADDR,
  491. .dr_mode = USB_DR_MODE_PERIPHERAL,
  492. .index = 0,
  493. };
  494. static struct dwc3_device dwc3_device_data1 = {
  495. .maximum_speed = USB_SPEED_HIGH,
  496. .base = ZYNQMP_USB1_XHCI_BASEADDR,
  497. .dr_mode = USB_DR_MODE_PERIPHERAL,
  498. .index = 1,
  499. };
  500. int usb_gadget_handle_interrupts(int index)
  501. {
  502. dwc3_uboot_handle_interrupt(index);
  503. return 0;
  504. }
  505. int board_usb_init(int index, enum usb_init_type init)
  506. {
  507. debug("%s: index %x\n", __func__, index);
  508. #if defined(CONFIG_USB_GADGET_DOWNLOAD)
  509. g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
  510. #endif
  511. switch (index) {
  512. case 0:
  513. return dwc3_uboot_init(&dwc3_device_data0);
  514. case 1:
  515. return dwc3_uboot_init(&dwc3_device_data1);
  516. };
  517. return -1;
  518. }
  519. int board_usb_cleanup(int index, enum usb_init_type init)
  520. {
  521. dwc3_uboot_exit(index);
  522. return 0;
  523. }
  524. #endif