cpu.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <common.h>
  7. #include <zynqpl.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/ps7_init_gpl.h>
  12. #include <asm/arch/sys_proto.h>
  13. #define ZYNQ_SILICON_VER_MASK 0xF0000000
  14. #define ZYNQ_SILICON_VER_SHIFT 28
  15. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  16. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  17. xilinx_desc fpga = {
  18. .family = xilinx_zynq,
  19. .iface = devcfg,
  20. .operations = &zynq_op,
  21. };
  22. #endif
  23. static const struct {
  24. u8 idcode;
  25. #if defined(CONFIG_FPGA)
  26. u32 fpga_size;
  27. #endif
  28. char *devicename;
  29. } zynq_fpga_descs[] = {
  30. ZYNQ_DESC(7Z007S),
  31. ZYNQ_DESC(7Z010),
  32. ZYNQ_DESC(7Z012S),
  33. ZYNQ_DESC(7Z014S),
  34. ZYNQ_DESC(7Z015),
  35. ZYNQ_DESC(7Z020),
  36. ZYNQ_DESC(7Z030),
  37. ZYNQ_DESC(7Z035),
  38. ZYNQ_DESC(7Z045),
  39. ZYNQ_DESC(7Z100),
  40. { /* Sentinel */ },
  41. };
  42. int arch_cpu_init(void)
  43. {
  44. zynq_slcr_unlock();
  45. #ifndef CONFIG_SPL_BUILD
  46. /* Device config APB, unlock the PCAP */
  47. writel(0x757BDF0D, &devcfg_base->unlock);
  48. writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
  49. #if (CONFIG_SYS_SDRAM_BASE == 0)
  50. /* remap DDR to zero, FILTERSTART */
  51. writel(0, &scu_base->filter_start);
  52. /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
  53. writel(0x1F, &slcr_base->ocm_cfg);
  54. /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
  55. writel(0x0, &slcr_base->fpga_rst_ctrl);
  56. /* Set urgent bits with register */
  57. writel(0x0, &slcr_base->ddr_urgent_sel);
  58. /* Urgent write, ports S2/S3 */
  59. writel(0xC, &slcr_base->ddr_urgent);
  60. #endif
  61. #endif
  62. zynq_slcr_lock();
  63. return 0;
  64. }
  65. unsigned int zynq_get_silicon_version(void)
  66. {
  67. return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
  68. >> ZYNQ_SILICON_VER_SHIFT;
  69. }
  70. void reset_cpu(ulong addr)
  71. {
  72. zynq_slcr_cpu_reset();
  73. while (1)
  74. ;
  75. }
  76. #ifndef CONFIG_SYS_DCACHE_OFF
  77. void enable_caches(void)
  78. {
  79. /* Enable D-cache. I-cache is already enabled in start.S */
  80. dcache_enable();
  81. }
  82. #endif
  83. static int __maybe_unused cpu_desc_id(void)
  84. {
  85. u32 idcode;
  86. u8 i;
  87. idcode = zynq_slcr_get_idcode();
  88. for (i = 0; zynq_fpga_descs[i].idcode; i++) {
  89. if (zynq_fpga_descs[i].idcode == idcode)
  90. return i;
  91. }
  92. return -ENODEV;
  93. }
  94. #if defined(CONFIG_ARCH_EARLY_INIT_R)
  95. int arch_early_init_r(void)
  96. {
  97. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  98. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  99. int cpu_id = cpu_desc_id();
  100. if (cpu_id < 0)
  101. return 0;
  102. fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
  103. fpga.name = zynq_fpga_descs[cpu_id].devicename;
  104. fpga_init();
  105. fpga_add(fpga_xilinx, &fpga);
  106. #endif
  107. return 0;
  108. }
  109. #endif
  110. #ifdef CONFIG_DISPLAY_CPUINFO
  111. int print_cpuinfo(void)
  112. {
  113. u32 version;
  114. int cpu_id = cpu_desc_id();
  115. if (cpu_id < 0)
  116. return 0;
  117. version = zynq_get_silicon_version() << 1;
  118. if (version > (PCW_SILICON_VERSION_3 << 1))
  119. version += 1;
  120. printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
  121. printf("Silicon: v%d.%d\n", version >> 1, version & 1);
  122. return 0;
  123. }
  124. #endif