zynqmp-r5.dts 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for Xilinx ZynqMP R5
  4. *
  5. * (C) Copyright 2018, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "xlnx,zynqmp-r5";
  14. model = "Xilinx ZynqMP R5";
  15. cpus {
  16. #address-cells = <0x1>;
  17. #size-cells = <0x0>;
  18. cpu@0 {
  19. compatible = "arm,cortex-r5";
  20. device_type = "cpu";
  21. reg = <0>;
  22. };
  23. };
  24. aliases {
  25. serial0 = &uart1;
  26. };
  27. memory@0 {
  28. device_type = "memory";
  29. reg = <0x00000000 0x20000000>;
  30. };
  31. chosen {
  32. bootargs = "";
  33. stdout-path = "serial0:115200n8";
  34. };
  35. clk100: clk100 {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <100000000>;
  39. u-boot,dm-pre-reloc;
  40. };
  41. amba {
  42. u-boot,dm-pre-reloc;
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. ttc0: timer@ff110000 {
  48. compatible = "cdns,ttc";
  49. status = "okay";
  50. reg = <0xff110000 0x1000>;
  51. timer-width = <32>;
  52. clocks = <&clk100>;
  53. };
  54. uart1: serial@ff010000 {
  55. u-boot,dm-pre-reloc;
  56. compatible = "cdns,uart-r1p12", "xlnx,xuartps";
  57. reg = <0xff010000 0x1000>;
  58. clock-names = "uart_clk", "pclk";
  59. clocks = <&clk100 &clk100>;
  60. };
  61. };
  62. };