zynqmp-clk.dtsi 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Clock specification for Xilinx ZynqMP
  4. *
  5. * (C) Copyright 2015 - 2018, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. / {
  10. clk100: clk100 {
  11. compatible = "fixed-clock";
  12. #clock-cells = <0>;
  13. clock-frequency = <100000000>;
  14. u-boot,dm-pre-reloc;
  15. };
  16. clk125: clk125 {
  17. compatible = "fixed-clock";
  18. #clock-cells = <0>;
  19. clock-frequency = <125000000>;
  20. };
  21. clk200: clk200 {
  22. compatible = "fixed-clock";
  23. #clock-cells = <0>;
  24. clock-frequency = <200000000>;
  25. u-boot,dm-pre-reloc;
  26. };
  27. clk250: clk250 {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <250000000>;
  31. };
  32. clk300: clk300 {
  33. compatible = "fixed-clock";
  34. #clock-cells = <0>;
  35. clock-frequency = <300000000>;
  36. };
  37. clk600: clk600 {
  38. compatible = "fixed-clock";
  39. #clock-cells = <0>;
  40. clock-frequency = <600000000>;
  41. };
  42. dp_aclk: clock0 {
  43. compatible = "fixed-clock";
  44. #clock-cells = <0>;
  45. clock-frequency = <100000000>;
  46. clock-accuracy = <100>;
  47. };
  48. dp_aud_clk: clock1 {
  49. compatible = "fixed-clock";
  50. #clock-cells = <0>;
  51. clock-frequency = <24576000>;
  52. clock-accuracy = <100>;
  53. };
  54. dpdma_clk: dpdma_clk {
  55. compatible = "fixed-clock";
  56. #clock-cells = <0x0>;
  57. clock-frequency = <533000000>;
  58. };
  59. drm_clock: drm_clock {
  60. compatible = "fixed-clock";
  61. #clock-cells = <0x0>;
  62. clock-frequency = <262750000>;
  63. clock-accuracy = <0x64>;
  64. };
  65. };
  66. &can0 {
  67. clocks = <&clk100 &clk100>;
  68. };
  69. &can1 {
  70. clocks = <&clk100 &clk100>;
  71. };
  72. &fpd_dma_chan1 {
  73. clocks = <&clk600>, <&clk100>;
  74. };
  75. &fpd_dma_chan2 {
  76. clocks = <&clk600>, <&clk100>;
  77. };
  78. &fpd_dma_chan3 {
  79. clocks = <&clk600>, <&clk100>;
  80. };
  81. &fpd_dma_chan4 {
  82. clocks = <&clk600>, <&clk100>;
  83. };
  84. &fpd_dma_chan5 {
  85. clocks = <&clk600>, <&clk100>;
  86. };
  87. &fpd_dma_chan6 {
  88. clocks = <&clk600>, <&clk100>;
  89. };
  90. &fpd_dma_chan7 {
  91. clocks = <&clk600>, <&clk100>;
  92. };
  93. &fpd_dma_chan8 {
  94. clocks = <&clk600>, <&clk100>;
  95. };
  96. &lpd_dma_chan1 {
  97. clocks = <&clk600>, <&clk100>;
  98. };
  99. &lpd_dma_chan2 {
  100. clocks = <&clk600>, <&clk100>;
  101. };
  102. &lpd_dma_chan3 {
  103. clocks = <&clk600>, <&clk100>;
  104. };
  105. &lpd_dma_chan4 {
  106. clocks = <&clk600>, <&clk100>;
  107. };
  108. &lpd_dma_chan5 {
  109. clocks = <&clk600>, <&clk100>;
  110. };
  111. &lpd_dma_chan6 {
  112. clocks = <&clk600>, <&clk100>;
  113. };
  114. &lpd_dma_chan7 {
  115. clocks = <&clk600>, <&clk100>;
  116. };
  117. &lpd_dma_chan8 {
  118. clocks = <&clk600>, <&clk100>;
  119. };
  120. &nand0 {
  121. clocks = <&clk100 &clk100>;
  122. };
  123. &gem0 {
  124. clocks = <&clk125>, <&clk125>, <&clk125>;
  125. };
  126. &gem1 {
  127. clocks = <&clk125>, <&clk125>, <&clk125>;
  128. };
  129. &gem2 {
  130. clocks = <&clk125>, <&clk125>, <&clk125>;
  131. };
  132. &gem3 {
  133. clocks = <&clk125>, <&clk125>, <&clk125>;
  134. };
  135. &gpio {
  136. clocks = <&clk100>;
  137. };
  138. &i2c0 {
  139. clocks = <&clk100>;
  140. };
  141. &i2c1 {
  142. clocks = <&clk100>;
  143. };
  144. &qspi {
  145. clocks = <&clk300 &clk300>;
  146. };
  147. &sata {
  148. clocks = <&clk250>;
  149. };
  150. &sdhci0 {
  151. clocks = <&clk200 &clk200>;
  152. };
  153. &sdhci1 {
  154. clocks = <&clk200 &clk200>;
  155. };
  156. &spi0 {
  157. clocks = <&clk200 &clk200>;
  158. };
  159. &spi1 {
  160. clocks = <&clk200 &clk200>;
  161. };
  162. &uart0 {
  163. clocks = <&clk100 &clk100>;
  164. };
  165. &uart1 {
  166. clocks = <&clk100 &clk100>;
  167. };
  168. &usb0 {
  169. clocks = <&clk250>, <&clk250>;
  170. };
  171. &usb1 {
  172. clocks = <&clk250>, <&clk250>;
  173. };
  174. &watchdog0 {
  175. clocks = <&clk100>;
  176. };
  177. &xilinx_drm {
  178. clocks = <&drm_clock>;
  179. };
  180. &xlnx_dp {
  181. clocks = <&dp_aclk>, <&dp_aud_clk>;
  182. };
  183. &xlnx_dpdma {
  184. clocks = <&dpdma_clk>;
  185. };
  186. &xlnx_dp_snd_codec0 {
  187. clocks = <&dp_aud_clk>;
  188. };