fsl_esdhc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019-2020 NXP
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the pxa mmc code:
  8. * (C) Copyright 2003
  9. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <command.h>
  14. #include <cpu_func.h>
  15. #include <errno.h>
  16. #include <hwconfig.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <malloc.h>
  20. #include <fsl_esdhc.h>
  21. #include <fdt_support.h>
  22. #include <asm/cache.h>
  23. #include <asm/io.h>
  24. #include <dm.h>
  25. #include <dm/device_compat.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. struct fsl_esdhc {
  30. uint dsaddr; /* SDMA system address register */
  31. uint blkattr; /* Block attributes register */
  32. uint cmdarg; /* Command argument register */
  33. uint xfertyp; /* Transfer type register */
  34. uint cmdrsp0; /* Command response 0 register */
  35. uint cmdrsp1; /* Command response 1 register */
  36. uint cmdrsp2; /* Command response 2 register */
  37. uint cmdrsp3; /* Command response 3 register */
  38. uint datport; /* Buffer data port register */
  39. uint prsstat; /* Present state register */
  40. uint proctl; /* Protocol control register */
  41. uint sysctl; /* System Control Register */
  42. uint irqstat; /* Interrupt status register */
  43. uint irqstaten; /* Interrupt status enable register */
  44. uint irqsigen; /* Interrupt signal enable register */
  45. uint autoc12err; /* Auto CMD error status register */
  46. uint hostcapblt; /* Host controller capabilities register */
  47. uint wml; /* Watermark level register */
  48. char reserved1[8]; /* reserved */
  49. uint fevt; /* Force event register */
  50. uint admaes; /* ADMA error status register */
  51. uint adsaddr; /* ADMA system address register */
  52. char reserved2[160];
  53. uint hostver; /* Host controller version register */
  54. char reserved3[4]; /* reserved */
  55. uint dmaerraddr; /* DMA error address register */
  56. char reserved4[4]; /* reserved */
  57. uint dmaerrattr; /* DMA error attribute register */
  58. char reserved5[4]; /* reserved */
  59. uint hostcapblt2; /* Host controller capabilities register 2 */
  60. char reserved6[756]; /* reserved */
  61. uint esdhcctl; /* eSDHC control register */
  62. };
  63. struct fsl_esdhc_plat {
  64. struct mmc_config cfg;
  65. struct mmc mmc;
  66. };
  67. /**
  68. * struct fsl_esdhc_priv
  69. *
  70. * @esdhc_regs: registers of the sdhc controller
  71. * @sdhc_clk: Current clk of the sdhc controller
  72. * @bus_width: bus width, 1bit, 4bit or 8bit
  73. * @cfg: mmc config
  74. * @mmc: mmc
  75. * Following is used when Driver Model is enabled for MMC
  76. * @dev: pointer for the device
  77. * @cd_gpio: gpio for card detection
  78. * @wp_gpio: gpio for write protection
  79. */
  80. struct fsl_esdhc_priv {
  81. struct fsl_esdhc *esdhc_regs;
  82. unsigned int sdhc_clk;
  83. bool is_sdhc_per_clk;
  84. unsigned int clock;
  85. #if !CONFIG_IS_ENABLED(DM_MMC)
  86. struct mmc *mmc;
  87. #endif
  88. struct udevice *dev;
  89. };
  90. /* Return the XFERTYP flags for a given command and data packet */
  91. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  92. {
  93. uint xfertyp = 0;
  94. if (data) {
  95. xfertyp |= XFERTYP_DPSEL;
  96. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  97. xfertyp |= XFERTYP_DMAEN;
  98. #endif
  99. if (data->blocks > 1) {
  100. xfertyp |= XFERTYP_MSBSEL;
  101. xfertyp |= XFERTYP_BCEN;
  102. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  103. xfertyp |= XFERTYP_AC12EN;
  104. #endif
  105. }
  106. if (data->flags & MMC_DATA_READ)
  107. xfertyp |= XFERTYP_DTDSEL;
  108. }
  109. if (cmd->resp_type & MMC_RSP_CRC)
  110. xfertyp |= XFERTYP_CCCEN;
  111. if (cmd->resp_type & MMC_RSP_OPCODE)
  112. xfertyp |= XFERTYP_CICEN;
  113. if (cmd->resp_type & MMC_RSP_136)
  114. xfertyp |= XFERTYP_RSPTYP_136;
  115. else if (cmd->resp_type & MMC_RSP_BUSY)
  116. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  117. else if (cmd->resp_type & MMC_RSP_PRESENT)
  118. xfertyp |= XFERTYP_RSPTYP_48;
  119. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  120. xfertyp |= XFERTYP_CMDTYP_ABORT;
  121. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  122. }
  123. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  124. /*
  125. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  126. */
  127. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  128. struct mmc_data *data)
  129. {
  130. struct fsl_esdhc *regs = priv->esdhc_regs;
  131. uint blocks;
  132. char *buffer;
  133. uint databuf;
  134. uint size;
  135. uint irqstat;
  136. ulong start;
  137. if (data->flags & MMC_DATA_READ) {
  138. blocks = data->blocks;
  139. buffer = data->dest;
  140. while (blocks) {
  141. start = get_timer(0);
  142. size = data->blocksize;
  143. irqstat = esdhc_read32(&regs->irqstat);
  144. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  145. if (get_timer(start) > PIO_TIMEOUT) {
  146. printf("\nData Read Failed in PIO Mode.");
  147. return;
  148. }
  149. }
  150. while (size && (!(irqstat & IRQSTAT_TC))) {
  151. udelay(100); /* Wait before last byte transfer complete */
  152. irqstat = esdhc_read32(&regs->irqstat);
  153. databuf = in_le32(&regs->datport);
  154. *((uint *)buffer) = databuf;
  155. buffer += 4;
  156. size -= 4;
  157. }
  158. blocks--;
  159. }
  160. } else {
  161. blocks = data->blocks;
  162. buffer = (char *)data->src;
  163. while (blocks) {
  164. start = get_timer(0);
  165. size = data->blocksize;
  166. irqstat = esdhc_read32(&regs->irqstat);
  167. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  168. if (get_timer(start) > PIO_TIMEOUT) {
  169. printf("\nData Write Failed in PIO Mode.");
  170. return;
  171. }
  172. }
  173. while (size && (!(irqstat & IRQSTAT_TC))) {
  174. udelay(100); /* Wait before last byte transfer complete */
  175. databuf = *((uint *)buffer);
  176. buffer += 4;
  177. size -= 4;
  178. irqstat = esdhc_read32(&regs->irqstat);
  179. out_le32(&regs->datport, databuf);
  180. }
  181. blocks--;
  182. }
  183. }
  184. }
  185. #endif
  186. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  187. struct mmc_data *data)
  188. {
  189. int timeout;
  190. struct fsl_esdhc *regs = priv->esdhc_regs;
  191. #if defined(CONFIG_FSL_LAYERSCAPE)
  192. dma_addr_t addr;
  193. #endif
  194. uint wml_value;
  195. wml_value = data->blocksize/4;
  196. if (data->flags & MMC_DATA_READ) {
  197. if (wml_value > WML_RD_WML_MAX)
  198. wml_value = WML_RD_WML_MAX_VAL;
  199. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  200. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  201. #if defined(CONFIG_FSL_LAYERSCAPE)
  202. addr = virt_to_phys((void *)(data->dest));
  203. if (upper_32_bits(addr))
  204. printf("Error found for upper 32 bits\n");
  205. else
  206. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  207. #else
  208. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  209. #endif
  210. #endif
  211. } else {
  212. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  213. flush_dcache_range((ulong)data->src,
  214. (ulong)data->src+data->blocks
  215. *data->blocksize);
  216. #endif
  217. if (wml_value > WML_WR_WML_MAX)
  218. wml_value = WML_WR_WML_MAX_VAL;
  219. if (!(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
  220. printf("Can not write to locked SD card.\n");
  221. return -EINVAL;
  222. }
  223. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  224. wml_value << 16);
  225. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  226. #if defined(CONFIG_FSL_LAYERSCAPE)
  227. addr = virt_to_phys((void *)(data->src));
  228. if (upper_32_bits(addr))
  229. printf("Error found for upper 32 bits\n");
  230. else
  231. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  232. #else
  233. esdhc_write32(&regs->dsaddr, (u32)data->src);
  234. #endif
  235. #endif
  236. }
  237. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  238. /* Calculate the timeout period for data transactions */
  239. /*
  240. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  241. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  242. * So, Number of SD Clock cycles for 0.25sec should be minimum
  243. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  244. * = (mmc->clock * 1/4) SD Clock cycles
  245. * As 1) >= 2)
  246. * => (2^(timeout+13)) >= mmc->clock * 1/4
  247. * Taking log2 both the sides
  248. * => timeout + 13 >= log2(mmc->clock/4)
  249. * Rounding up to next power of 2
  250. * => timeout + 13 = log2(mmc->clock/4) + 1
  251. * => timeout + 13 = fls(mmc->clock/4)
  252. *
  253. * However, the MMC spec "It is strongly recommended for hosts to
  254. * implement more than 500ms timeout value even if the card
  255. * indicates the 250ms maximum busy length." Even the previous
  256. * value of 300ms is known to be insufficient for some cards.
  257. * So, we use
  258. * => timeout + 13 = fls(mmc->clock/2)
  259. */
  260. timeout = fls(mmc->clock/2);
  261. timeout -= 13;
  262. if (timeout > 14)
  263. timeout = 14;
  264. if (timeout < 0)
  265. timeout = 0;
  266. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  267. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  268. timeout++;
  269. #endif
  270. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  271. timeout = 0xE;
  272. #endif
  273. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  274. return 0;
  275. }
  276. static void check_and_invalidate_dcache_range
  277. (struct mmc_cmd *cmd,
  278. struct mmc_data *data) {
  279. unsigned start = 0;
  280. unsigned end = 0;
  281. unsigned size = roundup(ARCH_DMA_MINALIGN,
  282. data->blocks*data->blocksize);
  283. #if defined(CONFIG_FSL_LAYERSCAPE)
  284. dma_addr_t addr;
  285. addr = virt_to_phys((void *)(data->dest));
  286. if (upper_32_bits(addr))
  287. printf("Error found for upper 32 bits\n");
  288. else
  289. start = lower_32_bits(addr);
  290. #else
  291. start = (unsigned)data->dest;
  292. #endif
  293. end = start + size;
  294. invalidate_dcache_range(start, end);
  295. }
  296. /*
  297. * Sends a command out on the bus. Takes the mmc pointer,
  298. * a command pointer, and an optional data pointer.
  299. */
  300. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  301. struct mmc_cmd *cmd, struct mmc_data *data)
  302. {
  303. int err = 0;
  304. uint xfertyp;
  305. uint irqstat;
  306. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  307. struct fsl_esdhc *regs = priv->esdhc_regs;
  308. unsigned long start;
  309. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  310. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  311. return 0;
  312. #endif
  313. esdhc_write32(&regs->irqstat, -1);
  314. sync();
  315. /* Wait for the bus to be idle */
  316. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  317. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  318. ;
  319. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  320. ;
  321. /* Wait at least 8 SD clock cycles before the next command */
  322. /*
  323. * Note: This is way more than 8 cycles, but 1ms seems to
  324. * resolve timing issues with some cards
  325. */
  326. udelay(1000);
  327. /* Set up for a data transfer if we have one */
  328. if (data) {
  329. err = esdhc_setup_data(priv, mmc, data);
  330. if(err)
  331. return err;
  332. if (data->flags & MMC_DATA_READ)
  333. check_and_invalidate_dcache_range(cmd, data);
  334. }
  335. /* Figure out the transfer arguments */
  336. xfertyp = esdhc_xfertyp(cmd, data);
  337. /* Mask all irqs */
  338. esdhc_write32(&regs->irqsigen, 0);
  339. /* Send the command */
  340. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  341. esdhc_write32(&regs->xfertyp, xfertyp);
  342. /* Wait for the command to complete */
  343. start = get_timer(0);
  344. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  345. if (get_timer(start) > 1000) {
  346. err = -ETIMEDOUT;
  347. goto out;
  348. }
  349. }
  350. irqstat = esdhc_read32(&regs->irqstat);
  351. if (irqstat & CMD_ERR) {
  352. err = -ECOMM;
  353. goto out;
  354. }
  355. if (irqstat & IRQSTAT_CTOE) {
  356. err = -ETIMEDOUT;
  357. goto out;
  358. }
  359. /* Workaround for ESDHC errata ENGcm03648 */
  360. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  361. int timeout = 6000;
  362. /* Poll on DATA0 line for cmd with busy signal for 600 ms */
  363. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  364. PRSSTAT_DAT0)) {
  365. udelay(100);
  366. timeout--;
  367. }
  368. if (timeout <= 0) {
  369. printf("Timeout waiting for DAT0 to go high!\n");
  370. err = -ETIMEDOUT;
  371. goto out;
  372. }
  373. }
  374. /* Copy the response to the response buffer */
  375. if (cmd->resp_type & MMC_RSP_136) {
  376. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  377. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  378. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  379. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  380. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  381. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  382. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  383. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  384. cmd->response[3] = (cmdrsp0 << 8);
  385. } else
  386. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  387. /* Wait until all of the blocks are transferred */
  388. if (data) {
  389. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  390. esdhc_pio_read_write(priv, data);
  391. #else
  392. do {
  393. irqstat = esdhc_read32(&regs->irqstat);
  394. if (irqstat & IRQSTAT_DTOE) {
  395. err = -ETIMEDOUT;
  396. goto out;
  397. }
  398. if (irqstat & DATA_ERR) {
  399. err = -ECOMM;
  400. goto out;
  401. }
  402. } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
  403. /*
  404. * Need invalidate the dcache here again to avoid any
  405. * cache-fill during the DMA operations such as the
  406. * speculative pre-fetching etc.
  407. */
  408. if (data->flags & MMC_DATA_READ) {
  409. check_and_invalidate_dcache_range(cmd, data);
  410. }
  411. #endif
  412. }
  413. out:
  414. /* Reset CMD and DATA portions on error */
  415. if (err) {
  416. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  417. SYSCTL_RSTC);
  418. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  419. ;
  420. if (data) {
  421. esdhc_write32(&regs->sysctl,
  422. esdhc_read32(&regs->sysctl) |
  423. SYSCTL_RSTD);
  424. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  425. ;
  426. }
  427. }
  428. esdhc_write32(&regs->irqstat, -1);
  429. return err;
  430. }
  431. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  432. {
  433. struct fsl_esdhc *regs = priv->esdhc_regs;
  434. int div = 1;
  435. int pre_div = 2;
  436. unsigned int sdhc_clk = priv->sdhc_clk;
  437. u32 time_out;
  438. u32 value;
  439. uint clk;
  440. if (clock < mmc->cfg->f_min)
  441. clock = mmc->cfg->f_min;
  442. while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
  443. pre_div *= 2;
  444. while (sdhc_clk / (div * pre_div) > clock && div < 16)
  445. div++;
  446. pre_div >>= 1;
  447. div -= 1;
  448. clk = (pre_div << 8) | (div << 4);
  449. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  450. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  451. time_out = 20;
  452. value = PRSSTAT_SDSTB;
  453. while (!(esdhc_read32(&regs->prsstat) & value)) {
  454. if (time_out == 0) {
  455. printf("fsl_esdhc: Internal clock never stabilised.\n");
  456. break;
  457. }
  458. time_out--;
  459. mdelay(1);
  460. }
  461. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  462. }
  463. static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
  464. {
  465. struct fsl_esdhc *regs = priv->esdhc_regs;
  466. u32 value;
  467. u32 time_out;
  468. value = esdhc_read32(&regs->sysctl);
  469. if (enable)
  470. value |= SYSCTL_CKEN;
  471. else
  472. value &= ~SYSCTL_CKEN;
  473. esdhc_write32(&regs->sysctl, value);
  474. time_out = 20;
  475. value = PRSSTAT_SDSTB;
  476. while (!(esdhc_read32(&regs->prsstat) & value)) {
  477. if (time_out == 0) {
  478. printf("fsl_esdhc: Internal clock never stabilised.\n");
  479. break;
  480. }
  481. time_out--;
  482. mdelay(1);
  483. }
  484. }
  485. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  486. {
  487. struct fsl_esdhc *regs = priv->esdhc_regs;
  488. if (priv->is_sdhc_per_clk) {
  489. /* Select to use peripheral clock */
  490. esdhc_clock_control(priv, false);
  491. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
  492. esdhc_clock_control(priv, true);
  493. }
  494. /* Set the clock speed */
  495. if (priv->clock != mmc->clock)
  496. set_sysctl(priv, mmc, mmc->clock);
  497. /* Set the bus width */
  498. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  499. if (mmc->bus_width == 4)
  500. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  501. else if (mmc->bus_width == 8)
  502. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  503. return 0;
  504. }
  505. static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
  506. {
  507. #ifdef CONFIG_ARCH_MPC830X
  508. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  509. sysconf83xx_t *sysconf = &immr->sysconf;
  510. setbits_be32(&sysconf->sdhccr, 0x02000000);
  511. #else
  512. esdhc_write32(&regs->esdhcctl, 0x00000040);
  513. #endif
  514. }
  515. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  516. {
  517. struct fsl_esdhc *regs = priv->esdhc_regs;
  518. ulong start;
  519. /* Reset the entire host controller */
  520. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  521. /* Wait until the controller is available */
  522. start = get_timer(0);
  523. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  524. if (get_timer(start) > 1000)
  525. return -ETIMEDOUT;
  526. }
  527. esdhc_enable_cache_snooping(regs);
  528. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  529. /* Set the initial clock speed */
  530. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  531. /* Disable the BRR and BWR bits in IRQSTAT */
  532. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  533. /* Put the PROCTL reg back to the default */
  534. esdhc_write32(&regs->proctl, PROCTL_INIT);
  535. /* Set timout to the maximum value */
  536. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  537. return 0;
  538. }
  539. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  540. {
  541. struct fsl_esdhc *regs = priv->esdhc_regs;
  542. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  543. if (CONFIG_ESDHC_DETECT_QUIRK)
  544. return 1;
  545. #endif
  546. if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
  547. return 1;
  548. return 0;
  549. }
  550. static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
  551. struct mmc_config *cfg)
  552. {
  553. struct fsl_esdhc *regs = priv->esdhc_regs;
  554. u32 caps;
  555. caps = esdhc_read32(&regs->hostcapblt);
  556. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  557. caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
  558. #endif
  559. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  560. caps |= HOSTCAPBLT_VS33;
  561. #endif
  562. if (caps & HOSTCAPBLT_VS18)
  563. cfg->voltages |= MMC_VDD_165_195;
  564. if (caps & HOSTCAPBLT_VS30)
  565. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  566. if (caps & HOSTCAPBLT_VS33)
  567. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  568. cfg->name = "FSL_SDHC";
  569. if (caps & HOSTCAPBLT_HSS)
  570. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  571. cfg->f_min = 400000;
  572. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  573. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  574. }
  575. #ifdef CONFIG_OF_LIBFDT
  576. __weak int esdhc_status_fixup(void *blob, const char *compat)
  577. {
  578. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  579. if (!hwconfig("esdhc")) {
  580. do_fixup_by_compat(blob, compat, "status", "disabled",
  581. sizeof("disabled"), 1);
  582. return 1;
  583. }
  584. #endif
  585. return 0;
  586. }
  587. #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  588. static int fsl_esdhc_get_cd(struct udevice *dev);
  589. static void esdhc_disable_for_no_card(void *blob)
  590. {
  591. struct udevice *dev;
  592. for (uclass_first_device(UCLASS_MMC, &dev);
  593. dev;
  594. uclass_next_device(&dev)) {
  595. char esdhc_path[50];
  596. if (fsl_esdhc_get_cd(dev))
  597. continue;
  598. snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
  599. (unsigned long)dev_read_addr(dev));
  600. do_fixup_by_path(blob, esdhc_path, "status", "disabled",
  601. sizeof("disabled"), 1);
  602. }
  603. }
  604. #endif
  605. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  606. {
  607. const char *compat = "fsl,esdhc";
  608. if (esdhc_status_fixup(blob, compat))
  609. return;
  610. #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  611. esdhc_disable_for_no_card(blob);
  612. #endif
  613. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  614. gd->arch.sdhc_clk, 1);
  615. }
  616. #endif
  617. #if !CONFIG_IS_ENABLED(DM_MMC)
  618. static int esdhc_getcd(struct mmc *mmc)
  619. {
  620. struct fsl_esdhc_priv *priv = mmc->priv;
  621. return esdhc_getcd_common(priv);
  622. }
  623. static int esdhc_init(struct mmc *mmc)
  624. {
  625. struct fsl_esdhc_priv *priv = mmc->priv;
  626. return esdhc_init_common(priv, mmc);
  627. }
  628. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  629. struct mmc_data *data)
  630. {
  631. struct fsl_esdhc_priv *priv = mmc->priv;
  632. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  633. }
  634. static int esdhc_set_ios(struct mmc *mmc)
  635. {
  636. struct fsl_esdhc_priv *priv = mmc->priv;
  637. return esdhc_set_ios_common(priv, mmc);
  638. }
  639. static const struct mmc_ops esdhc_ops = {
  640. .getcd = esdhc_getcd,
  641. .init = esdhc_init,
  642. .send_cmd = esdhc_send_cmd,
  643. .set_ios = esdhc_set_ios,
  644. };
  645. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  646. {
  647. struct fsl_esdhc_plat *plat;
  648. struct fsl_esdhc_priv *priv;
  649. struct mmc_config *mmc_cfg;
  650. struct mmc *mmc;
  651. if (!cfg)
  652. return -EINVAL;
  653. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  654. if (!priv)
  655. return -ENOMEM;
  656. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  657. if (!plat) {
  658. free(priv);
  659. return -ENOMEM;
  660. }
  661. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  662. priv->sdhc_clk = cfg->sdhc_clk;
  663. if (gd->arch.sdhc_per_clk)
  664. priv->is_sdhc_per_clk = true;
  665. mmc_cfg = &plat->cfg;
  666. if (cfg->max_bus_width == 8) {
  667. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  668. MMC_MODE_8BIT;
  669. } else if (cfg->max_bus_width == 4) {
  670. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
  671. } else if (cfg->max_bus_width == 1) {
  672. mmc_cfg->host_caps |= MMC_MODE_1BIT;
  673. } else {
  674. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  675. MMC_MODE_8BIT;
  676. printf("No max bus width provided. Assume 8-bit supported.\n");
  677. }
  678. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  679. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  680. mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
  681. #endif
  682. mmc_cfg->ops = &esdhc_ops;
  683. fsl_esdhc_get_cfg_common(priv, mmc_cfg);
  684. mmc = mmc_create(mmc_cfg, priv);
  685. if (!mmc)
  686. return -EIO;
  687. priv->mmc = mmc;
  688. return 0;
  689. }
  690. int fsl_esdhc_mmc_init(struct bd_info *bis)
  691. {
  692. struct fsl_esdhc_cfg *cfg;
  693. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  694. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  695. /* Prefer peripheral clock which provides higher frequency. */
  696. if (gd->arch.sdhc_per_clk)
  697. cfg->sdhc_clk = gd->arch.sdhc_per_clk;
  698. else
  699. cfg->sdhc_clk = gd->arch.sdhc_clk;
  700. return fsl_esdhc_initialize(bis, cfg);
  701. }
  702. #else /* DM_MMC */
  703. static int fsl_esdhc_probe(struct udevice *dev)
  704. {
  705. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  706. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  707. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  708. fdt_addr_t addr;
  709. struct mmc *mmc;
  710. int ret;
  711. addr = dev_read_addr(dev);
  712. if (addr == FDT_ADDR_T_NONE)
  713. return -EINVAL;
  714. #ifdef CONFIG_PPC
  715. priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
  716. #else
  717. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  718. #endif
  719. priv->dev = dev;
  720. if (gd->arch.sdhc_per_clk) {
  721. priv->sdhc_clk = gd->arch.sdhc_per_clk;
  722. priv->is_sdhc_per_clk = true;
  723. } else {
  724. priv->sdhc_clk = gd->arch.sdhc_clk;
  725. }
  726. if (priv->sdhc_clk <= 0) {
  727. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  728. return -EINVAL;
  729. }
  730. fsl_esdhc_get_cfg_common(priv, &plat->cfg);
  731. mmc_of_parse(dev, &plat->cfg);
  732. mmc = &plat->mmc;
  733. mmc->cfg = &plat->cfg;
  734. mmc->dev = dev;
  735. upriv->mmc = mmc;
  736. ret = esdhc_init_common(priv, mmc);
  737. if (ret)
  738. return ret;
  739. #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  740. if (!fsl_esdhc_get_cd(dev))
  741. esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
  742. #endif
  743. return 0;
  744. }
  745. static int fsl_esdhc_get_cd(struct udevice *dev)
  746. {
  747. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  748. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  749. if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
  750. return 1;
  751. return esdhc_getcd_common(priv);
  752. }
  753. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  754. struct mmc_data *data)
  755. {
  756. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  757. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  758. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  759. }
  760. static int fsl_esdhc_set_ios(struct udevice *dev)
  761. {
  762. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  763. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  764. return esdhc_set_ios_common(priv, &plat->mmc);
  765. }
  766. static const struct dm_mmc_ops fsl_esdhc_ops = {
  767. .get_cd = fsl_esdhc_get_cd,
  768. .send_cmd = fsl_esdhc_send_cmd,
  769. .set_ios = fsl_esdhc_set_ios,
  770. #ifdef MMC_SUPPORTS_TUNING
  771. .execute_tuning = fsl_esdhc_execute_tuning,
  772. #endif
  773. };
  774. static const struct udevice_id fsl_esdhc_ids[] = {
  775. { .compatible = "fsl,esdhc", },
  776. { /* sentinel */ }
  777. };
  778. static int fsl_esdhc_bind(struct udevice *dev)
  779. {
  780. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  781. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  782. }
  783. U_BOOT_DRIVER(fsl_esdhc) = {
  784. .name = "fsl-esdhc-mmc",
  785. .id = UCLASS_MMC,
  786. .of_match = fsl_esdhc_ids,
  787. .ops = &fsl_esdhc_ops,
  788. .bind = fsl_esdhc_bind,
  789. .probe = fsl_esdhc_probe,
  790. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  791. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  792. };
  793. #endif