phy-j721e-wiz.c 27 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
  4. * Jean-Jacques Hiblot <jjhiblot@ti.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dm/device_compat.h>
  10. #include <asm/gpio.h>
  11. #include <dm/lists.h>
  12. #include <dm/device-internal.h>
  13. #include <regmap.h>
  14. #include <reset-uclass.h>
  15. #include <dt-bindings/phy/phy.h>
  16. #include <dt-bindings/phy/phy-ti.h>
  17. #define WIZ_MAX_INPUT_CLOCKS 4
  18. /* To include mux clocks, divider clocks and gate clocks */
  19. #define WIZ_MAX_OUTPUT_CLOCKS 32
  20. #define WIZ_MAX_LANES 4
  21. #define WIZ_MUX_NUM_CLOCKS 3
  22. #define WIZ_DIV_NUM_CLOCKS_16G 2
  23. #define WIZ_DIV_NUM_CLOCKS_10G 1
  24. #define WIZ_SERDES_CTRL 0x404
  25. #define WIZ_SERDES_TOP_CTRL 0x408
  26. #define WIZ_SERDES_RST 0x40c
  27. #define WIZ_SERDES_TYPEC 0x410
  28. #define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
  29. #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
  30. #define WIZ_MAX_LANES 4
  31. #define WIZ_MUX_NUM_CLOCKS 3
  32. #define WIZ_DIV_NUM_CLOCKS_16G 2
  33. #define WIZ_DIV_NUM_CLOCKS_10G 1
  34. #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
  35. enum wiz_lane_standard_mode {
  36. LANE_MODE_GEN1,
  37. LANE_MODE_GEN2,
  38. LANE_MODE_GEN3,
  39. LANE_MODE_GEN4,
  40. };
  41. enum wiz_refclk_mux_sel {
  42. PLL0_REFCLK,
  43. PLL1_REFCLK,
  44. REFCLK_DIG,
  45. };
  46. enum wiz_refclk_div_sel {
  47. CMN_REFCLK,
  48. CMN_REFCLK1,
  49. };
  50. enum wiz_clock_input {
  51. WIZ_CORE_REFCLK,
  52. WIZ_EXT_REFCLK,
  53. WIZ_CORE_REFCLK1,
  54. WIZ_EXT_REFCLK1,
  55. };
  56. static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  57. static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  58. static const struct reg_field pll1_refclk_mux_sel =
  59. REG_FIELD(WIZ_SERDES_RST, 29, 29);
  60. static const struct reg_field pll0_refclk_mux_sel =
  61. REG_FIELD(WIZ_SERDES_RST, 28, 28);
  62. static const struct reg_field refclk_dig_sel_16g =
  63. REG_FIELD(WIZ_SERDES_RST, 24, 25);
  64. static const struct reg_field refclk_dig_sel_10g =
  65. REG_FIELD(WIZ_SERDES_RST, 24, 24);
  66. static const struct reg_field pma_cmn_refclk_int_mode =
  67. REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
  68. static const struct reg_field pma_cmn_refclk_mode =
  69. REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
  70. static const struct reg_field pma_cmn_refclk_dig_div =
  71. REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
  72. static const struct reg_field pma_cmn_refclk1_dig_div =
  73. REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
  74. static const struct reg_field p_enable[WIZ_MAX_LANES] = {
  75. REG_FIELD(WIZ_LANECTL(0), 30, 31),
  76. REG_FIELD(WIZ_LANECTL(1), 30, 31),
  77. REG_FIELD(WIZ_LANECTL(2), 30, 31),
  78. REG_FIELD(WIZ_LANECTL(3), 30, 31),
  79. };
  80. enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
  81. static const struct reg_field p_align[WIZ_MAX_LANES] = {
  82. REG_FIELD(WIZ_LANECTL(0), 29, 29),
  83. REG_FIELD(WIZ_LANECTL(1), 29, 29),
  84. REG_FIELD(WIZ_LANECTL(2), 29, 29),
  85. REG_FIELD(WIZ_LANECTL(3), 29, 29),
  86. };
  87. static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
  88. REG_FIELD(WIZ_LANECTL(0), 28, 28),
  89. REG_FIELD(WIZ_LANECTL(1), 28, 28),
  90. REG_FIELD(WIZ_LANECTL(2), 28, 28),
  91. REG_FIELD(WIZ_LANECTL(3), 28, 28),
  92. };
  93. static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
  94. REG_FIELD(WIZ_LANECTL(0), 24, 25),
  95. REG_FIELD(WIZ_LANECTL(1), 24, 25),
  96. REG_FIELD(WIZ_LANECTL(2), 24, 25),
  97. REG_FIELD(WIZ_LANECTL(3), 24, 25),
  98. };
  99. static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
  100. REG_FIELD(WIZ_LANECTL(0), 22, 23),
  101. REG_FIELD(WIZ_LANECTL(1), 22, 23),
  102. REG_FIELD(WIZ_LANECTL(2), 22, 23),
  103. REG_FIELD(WIZ_LANECTL(3), 22, 23),
  104. };
  105. static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
  106. REG_FIELD(WIZ_LANEDIV(0), 16, 22),
  107. REG_FIELD(WIZ_LANEDIV(1), 16, 22),
  108. REG_FIELD(WIZ_LANEDIV(2), 16, 22),
  109. REG_FIELD(WIZ_LANEDIV(3), 16, 22),
  110. };
  111. static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
  112. REG_FIELD(WIZ_LANEDIV(0), 0, 8),
  113. REG_FIELD(WIZ_LANEDIV(1), 0, 8),
  114. REG_FIELD(WIZ_LANEDIV(2), 0, 8),
  115. REG_FIELD(WIZ_LANEDIV(3), 0, 8),
  116. };
  117. struct wiz_clk_mux_sel {
  118. enum wiz_refclk_mux_sel mux_sel;
  119. u32 table[WIZ_MAX_INPUT_CLOCKS];
  120. const char *node_name;
  121. u32 num_parents;
  122. u32 parents[WIZ_MAX_INPUT_CLOCKS];
  123. };
  124. struct wiz_clk_div_sel {
  125. enum wiz_refclk_div_sel div_sel;
  126. const char *node_name;
  127. };
  128. static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
  129. {
  130. /*
  131. * Mux value to be configured for each of the input clocks
  132. * in the order populated in device tree
  133. */
  134. .num_parents = 2,
  135. .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
  136. .mux_sel = PLL0_REFCLK,
  137. .table = { 1, 0 },
  138. .node_name = "pll0-refclk",
  139. },
  140. {
  141. .num_parents = 2,
  142. .parents = { WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK1 },
  143. .mux_sel = PLL1_REFCLK,
  144. .table = { 1, 0 },
  145. .node_name = "pll1-refclk",
  146. },
  147. {
  148. .num_parents = 4,
  149. .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK, WIZ_EXT_REFCLK1 },
  150. .mux_sel = REFCLK_DIG,
  151. .table = { 1, 3, 0, 2 },
  152. .node_name = "refclk-dig",
  153. },
  154. };
  155. static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
  156. {
  157. /*
  158. * Mux value to be configured for each of the input clocks
  159. * in the order populated in device tree
  160. */
  161. .num_parents = 2,
  162. .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
  163. .mux_sel = PLL0_REFCLK,
  164. .table = { 1, 0 },
  165. .node_name = "pll0-refclk",
  166. },
  167. {
  168. .num_parents = 2,
  169. .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
  170. .mux_sel = PLL1_REFCLK,
  171. .table = { 1, 0 },
  172. .node_name = "pll1-refclk",
  173. },
  174. {
  175. .num_parents = 2,
  176. .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
  177. .mux_sel = REFCLK_DIG,
  178. .table = { 1, 0 },
  179. .node_name = "refclk-dig",
  180. },
  181. };
  182. static struct wiz_clk_div_sel clk_div_sel[] = {
  183. {
  184. .div_sel = CMN_REFCLK,
  185. .node_name = "cmn-refclk-dig-div",
  186. },
  187. {
  188. .div_sel = CMN_REFCLK1,
  189. .node_name = "cmn-refclk1-dig-div",
  190. },
  191. };
  192. enum wiz_type {
  193. J721E_WIZ_16G,
  194. J721E_WIZ_10G,
  195. AM64_WIZ_10G,
  196. };
  197. #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
  198. #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
  199. struct wiz {
  200. struct regmap *regmap;
  201. enum wiz_type type;
  202. struct wiz_clk_mux_sel *clk_mux_sel;
  203. struct wiz_clk_div_sel *clk_div_sel;
  204. unsigned int clk_div_sel_num;
  205. struct regmap_field *por_en;
  206. struct regmap_field *phy_reset_n;
  207. struct regmap_field *phy_en_refclk;
  208. struct regmap_field *p_enable[WIZ_MAX_LANES];
  209. struct regmap_field *p_align[WIZ_MAX_LANES];
  210. struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
  211. struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
  212. struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
  213. struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
  214. struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
  215. struct regmap_field *pma_cmn_refclk_int_mode;
  216. struct regmap_field *pma_cmn_refclk_mode;
  217. struct regmap_field *pma_cmn_refclk_dig_div;
  218. struct regmap_field *pma_cmn_refclk1_dig_div;
  219. struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
  220. struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
  221. struct udevice *dev;
  222. u32 num_lanes;
  223. struct gpio_desc *gpio_typec_dir;
  224. u32 lane_phy_type[WIZ_MAX_LANES];
  225. struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
  226. unsigned int id;
  227. };
  228. struct wiz_div_clk {
  229. struct clk parent_clk;
  230. struct wiz *wiz;
  231. };
  232. struct wiz_mux_clk {
  233. struct clk parent_clks[4];
  234. struct wiz *wiz;
  235. };
  236. struct wiz_clk {
  237. struct wiz *wiz;
  238. };
  239. struct wiz_reset {
  240. struct wiz *wiz;
  241. };
  242. static ulong wiz_div_clk_get_rate(struct clk *clk)
  243. {
  244. struct udevice *dev = clk->dev;
  245. struct wiz_div_clk *priv = dev_get_priv(dev);
  246. struct wiz_clk_div_sel *data = dev_get_plat(dev);
  247. struct wiz *wiz = priv->wiz;
  248. ulong parent_rate = clk_get_rate(&priv->parent_clk);
  249. u32 val;
  250. regmap_field_read(wiz->div_sel_field[data->div_sel], &val);
  251. return parent_rate >> val;
  252. }
  253. static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate)
  254. {
  255. struct udevice *dev = clk->dev;
  256. struct wiz_div_clk *priv = dev_get_priv(dev);
  257. struct wiz_clk_div_sel *data = dev_get_plat(dev);
  258. struct wiz *wiz = priv->wiz;
  259. ulong parent_rate = clk_get_rate(&priv->parent_clk);
  260. u32 div = parent_rate / rate;
  261. div = __ffs(div);
  262. regmap_field_write(wiz->div_sel_field[data->div_sel], div);
  263. return parent_rate >> div;
  264. }
  265. const struct clk_ops wiz_div_clk_ops = {
  266. .get_rate = wiz_div_clk_get_rate,
  267. .set_rate = wiz_div_clk_set_rate,
  268. };
  269. int wiz_div_clk_probe(struct udevice *dev)
  270. {
  271. struct wiz_div_clk *priv = dev_get_priv(dev);
  272. struct clk parent_clk;
  273. int rc;
  274. rc = clk_get_by_index(dev, 0, &parent_clk);
  275. if (rc) {
  276. dev_err(dev, "unable to get parent clock. ret %d\n", rc);
  277. return rc;
  278. }
  279. priv->parent_clk = parent_clk;
  280. priv->wiz = dev_get_priv(dev->parent);
  281. return 0;
  282. }
  283. U_BOOT_DRIVER(wiz_div_clk) = {
  284. .name = "wiz_div_clk",
  285. .id = UCLASS_CLK,
  286. .priv_auto = sizeof(struct wiz_div_clk),
  287. .ops = &wiz_div_clk_ops,
  288. .probe = wiz_div_clk_probe,
  289. };
  290. static int wiz_clk_mux_set_parent(struct clk *clk, struct clk *parent)
  291. {
  292. struct udevice *dev = clk->dev;
  293. struct wiz_mux_clk *priv = dev_get_priv(dev);
  294. struct wiz_clk_mux_sel *data = dev_get_plat(dev);
  295. struct wiz *wiz = priv->wiz;
  296. int i;
  297. for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++)
  298. if (parent->dev == priv->parent_clks[i].dev)
  299. break;
  300. if (i == ARRAY_SIZE(priv->parent_clks))
  301. return -EINVAL;
  302. regmap_field_write(wiz->mux_sel_field[data->mux_sel], data->table[i]);
  303. return 0;
  304. }
  305. static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  306. {
  307. struct udevice *dev = clk->dev;
  308. struct wiz_mux_clk *priv = dev_get_priv(dev);
  309. struct wiz *wiz = priv->wiz;
  310. clk->id = wiz->id;
  311. return 0;
  312. }
  313. static const struct clk_ops wiz_clk_mux_ops = {
  314. .set_parent = wiz_clk_mux_set_parent,
  315. .of_xlate = wiz_clk_xlate,
  316. };
  317. int wiz_mux_clk_probe(struct udevice *dev)
  318. {
  319. struct wiz_mux_clk *priv = dev_get_priv(dev);
  320. int rc;
  321. int i;
  322. for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
  323. rc = clk_get_by_index(dev, i, &priv->parent_clks[i]);
  324. if (rc)
  325. priv->parent_clks[i].dev = NULL;
  326. }
  327. priv->wiz = dev_get_priv(dev->parent);
  328. return 0;
  329. }
  330. U_BOOT_DRIVER(wiz_mux_clk) = {
  331. .name = "wiz_mux_clk",
  332. .id = UCLASS_CLK,
  333. .priv_auto = sizeof(struct wiz_mux_clk),
  334. .ops = &wiz_clk_mux_ops,
  335. .probe = wiz_mux_clk_probe,
  336. };
  337. static int wiz_clk_set_parent(struct clk *clk, struct clk *parent)
  338. {
  339. struct udevice *dev = clk->dev;
  340. struct wiz_clk *priv = dev_get_priv(dev);
  341. const struct wiz_clk_mux_sel *mux_sel;
  342. struct wiz *wiz = priv->wiz;
  343. int num_parents;
  344. int i, j, id;
  345. id = clk->id >> 10;
  346. /* set_parent is applicable only for MUX clocks */
  347. if (id > TI_WIZ_REFCLK_DIG)
  348. return 0;
  349. for (i = 0; i < WIZ_MAX_INPUT_CLOCKS; i++)
  350. if (wiz->input_clks[i]->dev == parent->dev)
  351. break;
  352. if (i == WIZ_MAX_INPUT_CLOCKS)
  353. return -EINVAL;
  354. mux_sel = &wiz->clk_mux_sel[id];
  355. num_parents = mux_sel->num_parents;
  356. for (j = 0; j < num_parents; j++)
  357. if (mux_sel->parents[j] == i)
  358. break;
  359. if (j == num_parents)
  360. return -EINVAL;
  361. regmap_field_write(wiz->mux_sel_field[id], mux_sel->table[j]);
  362. return 0;
  363. }
  364. static int wiz_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  365. {
  366. struct udevice *dev = clk->dev;
  367. struct wiz_clk *priv = dev_get_priv(dev);
  368. struct wiz *wiz = priv->wiz;
  369. clk->id = args->args[0] << 10 | wiz->id;
  370. return 0;
  371. }
  372. static const struct clk_ops wiz_clk_ops = {
  373. .set_parent = wiz_clk_set_parent,
  374. .of_xlate = wiz_clk_of_xlate,
  375. };
  376. int wiz_clk_probe(struct udevice *dev)
  377. {
  378. struct wiz_clk *priv = dev_get_priv(dev);
  379. priv->wiz = dev_get_priv(dev->parent);
  380. return 0;
  381. }
  382. U_BOOT_DRIVER(wiz_clk) = {
  383. .name = "wiz_clk",
  384. .id = UCLASS_CLK,
  385. .priv_auto = sizeof(struct wiz_clk),
  386. .ops = &wiz_clk_ops,
  387. .probe = wiz_clk_probe,
  388. };
  389. static int wiz_reset_request(struct reset_ctl *reset_ctl)
  390. {
  391. return 0;
  392. }
  393. static int wiz_reset_free(struct reset_ctl *reset_ctl)
  394. {
  395. return 0;
  396. }
  397. static int wiz_reset_assert(struct reset_ctl *reset_ctl)
  398. {
  399. struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
  400. struct wiz *wiz = priv->wiz;
  401. int ret;
  402. int id = reset_ctl->id;
  403. if (id == 0) {
  404. ret = regmap_field_write(wiz->phy_reset_n, false);
  405. return ret;
  406. }
  407. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
  408. return ret;
  409. }
  410. static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
  411. {
  412. if (wiz->type != AM64_WIZ_10G)
  413. return 0;
  414. if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
  415. return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
  416. return 0;
  417. }
  418. static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
  419. {
  420. struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
  421. struct wiz *wiz = priv->wiz;
  422. int ret;
  423. int id = reset_ctl->id;
  424. ret = wiz_phy_fullrt_div(wiz, id - 1);
  425. if (ret)
  426. return ret;
  427. /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
  428. if (id == 0 && wiz->gpio_typec_dir) {
  429. if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
  430. regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
  431. WIZ_SERDES_TYPEC_LN10_SWAP,
  432. WIZ_SERDES_TYPEC_LN10_SWAP);
  433. } else {
  434. regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
  435. WIZ_SERDES_TYPEC_LN10_SWAP, 0);
  436. }
  437. }
  438. if (id == 0) {
  439. ret = regmap_field_write(wiz->phy_reset_n, true);
  440. return ret;
  441. }
  442. if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE)
  443. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
  444. else
  445. ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
  446. return ret;
  447. }
  448. static struct reset_ops wiz_reset_ops = {
  449. .request = wiz_reset_request,
  450. .rfree = wiz_reset_free,
  451. .rst_assert = wiz_reset_assert,
  452. .rst_deassert = wiz_reset_deassert,
  453. };
  454. int wiz_reset_probe(struct udevice *dev)
  455. {
  456. struct wiz_reset *priv = dev_get_priv(dev);
  457. priv->wiz = dev_get_priv(dev->parent);
  458. return 0;
  459. }
  460. U_BOOT_DRIVER(wiz_reset) = {
  461. .name = "wiz-reset",
  462. .id = UCLASS_RESET,
  463. .probe = wiz_reset_probe,
  464. .ops = &wiz_reset_ops,
  465. .flags = DM_FLAG_LEAVE_PD_ON,
  466. };
  467. static int wiz_reset(struct wiz *wiz)
  468. {
  469. int ret;
  470. ret = regmap_field_write(wiz->por_en, 0x1);
  471. if (ret)
  472. return ret;
  473. mdelay(1);
  474. ret = regmap_field_write(wiz->por_en, 0x0);
  475. if (ret)
  476. return ret;
  477. return 0;
  478. }
  479. static int wiz_p_mac_div_sel(struct wiz *wiz)
  480. {
  481. u32 num_lanes = wiz->num_lanes;
  482. int ret;
  483. int i;
  484. for (i = 0; i < num_lanes; i++) {
  485. if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
  486. ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
  487. if (ret)
  488. return ret;
  489. ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
  490. if (ret)
  491. return ret;
  492. }
  493. }
  494. return 0;
  495. }
  496. static int wiz_mode_select(struct wiz *wiz)
  497. {
  498. u32 num_lanes = wiz->num_lanes;
  499. int ret;
  500. int i;
  501. for (i = 0; i < num_lanes; i++) {
  502. if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
  503. ret = regmap_field_write(wiz->p_standard_mode[i],
  504. LANE_MODE_GEN2);
  505. if (ret)
  506. return ret;
  507. }
  508. }
  509. return 0;
  510. }
  511. static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
  512. {
  513. u32 num_lanes = wiz->num_lanes;
  514. int i;
  515. int ret;
  516. for (i = 0; i < num_lanes; i++) {
  517. ret = regmap_field_write(wiz->p_align[i], enable);
  518. if (ret)
  519. return ret;
  520. ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
  521. if (ret)
  522. return ret;
  523. }
  524. return 0;
  525. }
  526. static int wiz_init(struct wiz *wiz)
  527. {
  528. struct udevice *dev = wiz->dev;
  529. int ret;
  530. ret = wiz_reset(wiz);
  531. if (ret) {
  532. dev_err(dev, "WIZ reset failed\n");
  533. return ret;
  534. }
  535. ret = wiz_mode_select(wiz);
  536. if (ret) {
  537. dev_err(dev, "WIZ mode select failed\n");
  538. return ret;
  539. }
  540. ret = wiz_p_mac_div_sel(wiz);
  541. if (ret) {
  542. dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
  543. return ret;
  544. }
  545. ret = wiz_init_raw_interface(wiz, true);
  546. if (ret) {
  547. dev_err(dev, "WIZ interface initialization failed\n");
  548. return ret;
  549. }
  550. return 0;
  551. }
  552. static int wiz_regfield_init(struct wiz *wiz)
  553. {
  554. struct regmap *regmap = wiz->regmap;
  555. int num_lanes = wiz->num_lanes;
  556. struct udevice *dev = wiz->dev;
  557. enum wiz_type type;
  558. int i;
  559. wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
  560. if (IS_ERR(wiz->por_en)) {
  561. dev_err(dev, "POR_EN reg field init failed\n");
  562. return PTR_ERR(wiz->por_en);
  563. }
  564. wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
  565. phy_reset_n);
  566. if (IS_ERR(wiz->phy_reset_n)) {
  567. dev_err(dev, "PHY_RESET_N reg field init failed\n");
  568. return PTR_ERR(wiz->phy_reset_n);
  569. }
  570. wiz->pma_cmn_refclk_int_mode =
  571. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
  572. if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
  573. dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
  574. return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
  575. }
  576. wiz->pma_cmn_refclk_mode =
  577. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
  578. if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
  579. dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
  580. return PTR_ERR(wiz->pma_cmn_refclk_mode);
  581. }
  582. wiz->div_sel_field[CMN_REFCLK] =
  583. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
  584. if (IS_ERR(wiz->div_sel_field[CMN_REFCLK])) {
  585. dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
  586. return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
  587. }
  588. wiz->div_sel_field[CMN_REFCLK1] =
  589. devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div);
  590. if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
  591. dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
  592. return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
  593. }
  594. wiz->mux_sel_field[PLL0_REFCLK] =
  595. devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
  596. if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
  597. dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
  598. return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
  599. }
  600. wiz->mux_sel_field[PLL1_REFCLK] =
  601. devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
  602. if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
  603. dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
  604. return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
  605. }
  606. type = dev_get_driver_data(dev);
  607. if (type == J721E_WIZ_10G || type == AM64_WIZ_10G)
  608. wiz->mux_sel_field[REFCLK_DIG] =
  609. devm_regmap_field_alloc(dev, regmap,
  610. refclk_dig_sel_10g);
  611. else
  612. wiz->mux_sel_field[REFCLK_DIG] =
  613. devm_regmap_field_alloc(dev, regmap,
  614. refclk_dig_sel_16g);
  615. if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
  616. dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
  617. return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
  618. }
  619. for (i = 0; i < num_lanes; i++) {
  620. wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
  621. p_enable[i]);
  622. if (IS_ERR(wiz->p_enable[i])) {
  623. dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
  624. return PTR_ERR(wiz->p_enable[i]);
  625. }
  626. wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
  627. p_align[i]);
  628. if (IS_ERR(wiz->p_align[i])) {
  629. dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
  630. return PTR_ERR(wiz->p_align[i]);
  631. }
  632. wiz->p_raw_auto_start[i] =
  633. devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
  634. if (IS_ERR(wiz->p_raw_auto_start[i])) {
  635. dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
  636. i);
  637. return PTR_ERR(wiz->p_raw_auto_start[i]);
  638. }
  639. wiz->p_standard_mode[i] =
  640. devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
  641. if (IS_ERR(wiz->p_standard_mode[i])) {
  642. dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
  643. i);
  644. return PTR_ERR(wiz->p_standard_mode[i]);
  645. }
  646. wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
  647. if (IS_ERR(wiz->p0_fullrt_div[i])) {
  648. dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
  649. return PTR_ERR(wiz->p0_fullrt_div[i]);
  650. }
  651. wiz->p_mac_div_sel0[i] =
  652. devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
  653. if (IS_ERR(wiz->p_mac_div_sel0[i])) {
  654. dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
  655. i);
  656. return PTR_ERR(wiz->p_mac_div_sel0[i]);
  657. }
  658. wiz->p_mac_div_sel1[i] =
  659. devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
  660. if (IS_ERR(wiz->p_mac_div_sel1[i])) {
  661. dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
  662. i);
  663. return PTR_ERR(wiz->p_mac_div_sel1[i]);
  664. }
  665. }
  666. return 0;
  667. }
  668. static int wiz_clock_init(struct wiz *wiz)
  669. {
  670. struct udevice *dev = wiz->dev;
  671. unsigned long rate;
  672. struct clk *clk;
  673. int ret;
  674. clk = devm_clk_get(dev, "core_ref_clk");
  675. if (IS_ERR(clk)) {
  676. dev_err(dev, "core_ref_clk clock not found\n");
  677. ret = PTR_ERR(clk);
  678. return ret;
  679. }
  680. wiz->input_clks[WIZ_CORE_REFCLK] = clk;
  681. /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
  682. wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
  683. rate = clk_get_rate(clk);
  684. if (rate >= 100000000)
  685. regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
  686. else
  687. regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
  688. clk = devm_clk_get(dev, "ext_ref_clk");
  689. if (IS_ERR(clk)) {
  690. dev_err(dev, "ext_ref_clk clock not found\n");
  691. ret = PTR_ERR(clk);
  692. return ret;
  693. }
  694. wiz->input_clks[WIZ_EXT_REFCLK] = clk;
  695. /* Initialize EXT_REFCLK1 to the same clock reference to maintain old DT compatibility */
  696. wiz->input_clks[WIZ_EXT_REFCLK1] = clk;
  697. rate = clk_get_rate(clk);
  698. if (rate >= 100000000)
  699. regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
  700. else
  701. regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
  702. return 0;
  703. }
  704. static ofnode get_child_by_name(struct udevice *dev, const char *name)
  705. {
  706. int l = strlen(name);
  707. ofnode node = dev_read_first_subnode(dev);
  708. while (ofnode_valid(node)) {
  709. const char *child_name = ofnode_get_name(node);
  710. if (!strncmp(child_name, name, l)) {
  711. if (child_name[l] == '\0' || child_name[l] == '@')
  712. return node;
  713. }
  714. node = dev_read_next_subnode(node);
  715. }
  716. return node;
  717. }
  718. static int j721e_wiz_bind_clocks(struct wiz *wiz)
  719. {
  720. struct udevice *dev = wiz->dev;
  721. struct driver *wiz_clk_drv;
  722. int i, rc;
  723. wiz_clk_drv = lists_driver_lookup_name("wiz_clk");
  724. if (!wiz_clk_drv) {
  725. dev_err(dev, "Cannot find driver 'wiz_clk'\n");
  726. return -ENOENT;
  727. }
  728. for (i = 0; i < WIZ_DIV_NUM_CLOCKS_10G; i++) {
  729. rc = device_bind(dev, wiz_clk_drv, clk_div_sel[i].node_name,
  730. &clk_div_sel[i], dev_ofnode(dev), NULL);
  731. if (rc) {
  732. dev_err(dev, "cannot bind driver for clock %s\n",
  733. clk_div_sel[i].node_name);
  734. }
  735. }
  736. for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
  737. rc = device_bind(dev, wiz_clk_drv, clk_mux_sel_10g[i].node_name,
  738. &clk_mux_sel_10g[i], dev_ofnode(dev), NULL);
  739. if (rc) {
  740. dev_err(dev, "cannot bind driver for clock %s\n",
  741. clk_mux_sel_10g[i].node_name);
  742. }
  743. }
  744. return 0;
  745. }
  746. static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
  747. {
  748. struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
  749. struct udevice *dev = wiz->dev;
  750. enum wiz_type type = wiz->type;
  751. struct driver *div_clk_drv;
  752. struct driver *mux_clk_drv;
  753. ofnode node;
  754. int i, rc;
  755. if (type == AM64_WIZ_10G)
  756. return j721e_wiz_bind_clocks(wiz);
  757. div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
  758. if (!div_clk_drv) {
  759. dev_err(dev, "Cannot find driver 'wiz_div_clk'\n");
  760. return -ENOENT;
  761. }
  762. mux_clk_drv = lists_driver_lookup_name("wiz_mux_clk");
  763. if (!mux_clk_drv) {
  764. dev_err(dev, "Cannot find driver 'wiz_mux_clk'\n");
  765. return -ENOENT;
  766. }
  767. for (i = 0; i < wiz->clk_div_sel_num; i++) {
  768. node = get_child_by_name(dev, clk_div_sel[i].node_name);
  769. if (!ofnode_valid(node)) {
  770. dev_err(dev, "cannot find node for clock %s\n",
  771. clk_div_sel[i].node_name);
  772. continue;
  773. }
  774. rc = device_bind(dev, div_clk_drv, clk_div_sel[i].node_name,
  775. &clk_div_sel[i], node, NULL);
  776. if (rc) {
  777. dev_err(dev, "cannot bind driver for clock %s\n",
  778. clk_div_sel[i].node_name);
  779. }
  780. }
  781. for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
  782. node = get_child_by_name(dev, clk_mux_sel[i].node_name);
  783. if (!ofnode_valid(node)) {
  784. dev_err(dev, "cannot find node for clock %s\n",
  785. clk_mux_sel[i].node_name);
  786. continue;
  787. }
  788. rc = device_bind(dev, mux_clk_drv, clk_mux_sel[i].node_name,
  789. &clk_mux_sel[i], node, NULL);
  790. if (rc) {
  791. dev_err(dev, "cannot bind driver for clock %s\n",
  792. clk_mux_sel[i].node_name);
  793. }
  794. }
  795. return 0;
  796. }
  797. static int j721e_wiz_bind_reset(struct udevice *dev)
  798. {
  799. int rc;
  800. struct driver *drv;
  801. drv = lists_driver_lookup_name("wiz-reset");
  802. if (!drv) {
  803. dev_err(dev, "Cannot find driver 'wiz-reset'\n");
  804. return -ENOENT;
  805. }
  806. rc = device_bind(dev, drv, "wiz-reset", NULL, dev_ofnode(dev), NULL);
  807. if (rc) {
  808. dev_err(dev, "cannot bind driver for wiz-reset\n");
  809. return rc;
  810. }
  811. return 0;
  812. }
  813. static int j721e_wiz_bind(struct udevice *dev)
  814. {
  815. dm_scan_fdt_dev(dev);
  816. return 0;
  817. }
  818. static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
  819. {
  820. ofnode child, serdes;
  821. serdes = get_child_by_name(dev, "serdes");
  822. if (!ofnode_valid(serdes)) {
  823. dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
  824. return -EINVAL;
  825. }
  826. ofnode_for_each_subnode(child, serdes) {
  827. u32 reg, num_lanes = 1, phy_type = PHY_NONE;
  828. int ret, i;
  829. ret = ofnode_read_u32(child, "reg", &reg);
  830. if (ret) {
  831. dev_err(dev, "%s: Reading \"reg\" from failed: %d\n",
  832. __func__, ret);
  833. return ret;
  834. }
  835. ofnode_read_u32(child, "cdns,num-lanes", &num_lanes);
  836. ofnode_read_u32(child, "cdns,phy-type", &phy_type);
  837. dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
  838. reg, reg + num_lanes - 1, phy_type);
  839. for (i = reg; i < reg + num_lanes; i++)
  840. wiz->lane_phy_type[i] = phy_type;
  841. }
  842. return 0;
  843. }
  844. static int j721e_wiz_probe(struct udevice *dev)
  845. {
  846. struct wiz *wiz = dev_get_priv(dev);
  847. struct ofnode_phandle_args args;
  848. unsigned int val;
  849. int rc, i;
  850. ofnode node;
  851. struct regmap *regmap;
  852. u32 num_lanes;
  853. node = get_child_by_name(dev, "serdes");
  854. if (!ofnode_valid(node)) {
  855. dev_err(dev, "Failed to get SERDES child DT node\n");
  856. return -ENODEV;
  857. }
  858. rc = regmap_init_mem(node, &regmap);
  859. if (rc) {
  860. dev_err(dev, "Failed to get memory resource\n");
  861. return rc;
  862. }
  863. rc = dev_read_u32(dev, "num-lanes", &num_lanes);
  864. if (rc) {
  865. dev_err(dev, "Failed to read num-lanes property\n");
  866. goto err_addr_to_resource;
  867. }
  868. if (num_lanes > WIZ_MAX_LANES) {
  869. dev_err(dev, "Cannot support %d lanes\n", num_lanes);
  870. goto err_addr_to_resource;
  871. }
  872. wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
  873. GPIOD_IS_IN);
  874. if (IS_ERR(wiz->gpio_typec_dir)) {
  875. rc = PTR_ERR(wiz->gpio_typec_dir);
  876. dev_err(dev, "Failed to request typec-dir gpio: %d\n", rc);
  877. goto err_addr_to_resource;
  878. }
  879. rc = dev_read_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0, 0, &args);
  880. if (rc) {
  881. dev_err(dev, "Failed to get power domain: %d\n", rc);
  882. goto err_addr_to_resource;
  883. }
  884. wiz->id = args.args[0];
  885. wiz->regmap = regmap;
  886. wiz->num_lanes = num_lanes;
  887. wiz->dev = dev;
  888. wiz->clk_div_sel = clk_div_sel;
  889. wiz->type = dev_get_driver_data(dev);
  890. if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) {
  891. wiz->clk_mux_sel = clk_mux_sel_10g;
  892. wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
  893. } else {
  894. wiz->clk_mux_sel = clk_mux_sel_16g;
  895. wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
  896. }
  897. rc = wiz_get_lane_phy_types(dev, wiz);
  898. if (rc) {
  899. dev_err(dev, "Failed to get lane PHY types\n");
  900. goto err_addr_to_resource;
  901. }
  902. rc = wiz_regfield_init(wiz);
  903. if (rc) {
  904. dev_err(dev, "Failed to initialize regfields\n");
  905. goto err_addr_to_resource;
  906. }
  907. for (i = 0; i < wiz->num_lanes; i++) {
  908. regmap_field_read(wiz->p_enable[i], &val);
  909. if (val & (P_ENABLE | P_ENABLE_FORCE)) {
  910. dev_err(dev, "SERDES already configured\n");
  911. rc = -EBUSY;
  912. goto err_addr_to_resource;
  913. }
  914. }
  915. rc = j721e_wiz_bind_of_clocks(wiz);
  916. if (rc) {
  917. dev_err(dev, "Failed to bind clocks\n");
  918. goto err_addr_to_resource;
  919. }
  920. rc = j721e_wiz_bind_reset(dev);
  921. if (rc) {
  922. dev_err(dev, "Failed to bind reset\n");
  923. goto err_addr_to_resource;
  924. }
  925. rc = wiz_clock_init(wiz);
  926. if (rc) {
  927. dev_warn(dev, "Failed to initialize clocks\n");
  928. goto err_addr_to_resource;
  929. }
  930. rc = wiz_init(wiz);
  931. if (rc) {
  932. dev_err(dev, "WIZ initialization failed\n");
  933. goto err_addr_to_resource;
  934. }
  935. return 0;
  936. err_addr_to_resource:
  937. free(regmap);
  938. return rc;
  939. }
  940. static int j721e_wiz_remove(struct udevice *dev)
  941. {
  942. struct wiz *wiz = dev_get_priv(dev);
  943. if (wiz->regmap)
  944. free(wiz->regmap);
  945. return 0;
  946. }
  947. static const struct udevice_id j721e_wiz_ids[] = {
  948. {
  949. .compatible = "ti,j721e-wiz-16g", .data = J721E_WIZ_16G,
  950. },
  951. {
  952. .compatible = "ti,j721e-wiz-10g", .data = J721E_WIZ_10G,
  953. },
  954. {
  955. .compatible = "ti,am64-wiz-10g", .data = AM64_WIZ_10G,
  956. },
  957. {}
  958. };
  959. U_BOOT_DRIVER(phy_j721e_wiz) = {
  960. .name = "phy-j721e-wiz",
  961. .id = UCLASS_NOP,
  962. .of_match = j721e_wiz_ids,
  963. .bind = j721e_wiz_bind,
  964. .probe = j721e_wiz_probe,
  965. .remove = j721e_wiz_remove,
  966. .priv_auto = sizeof(struct wiz),
  967. .flags = DM_FLAG_LEAVE_PD_ON,
  968. };