sdhci.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <mmc.h>
  16. #include <sdhci.h>
  17. #include <asm/cache.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <linux/dma-mapping.h>
  21. #include <phys2bus.h>
  22. #include <power/regulator.h>
  23. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  24. {
  25. unsigned long timeout;
  26. /* Wait max 100 ms */
  27. timeout = 100;
  28. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30. if (timeout == 0) {
  31. printf("%s: Reset 0x%x never completed.\n",
  32. __func__, (int)mask);
  33. return;
  34. }
  35. timeout--;
  36. udelay(1000);
  37. }
  38. }
  39. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  40. {
  41. int i;
  42. if (cmd->resp_type & MMC_RSP_136) {
  43. /* CRC is stripped so we need to do some shifting. */
  44. for (i = 0; i < 4; i++) {
  45. cmd->response[i] = sdhci_readl(host,
  46. SDHCI_RESPONSE + (3-i)*4) << 8;
  47. if (i != 3)
  48. cmd->response[i] |= sdhci_readb(host,
  49. SDHCI_RESPONSE + (3-i)*4-1);
  50. }
  51. } else {
  52. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  53. }
  54. }
  55. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  56. {
  57. int i;
  58. char *offs;
  59. for (i = 0; i < data->blocksize; i += 4) {
  60. offs = data->dest + i;
  61. if (data->flags == MMC_DATA_READ)
  62. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  63. else
  64. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  65. }
  66. }
  67. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  68. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  69. int *is_aligned, int trans_bytes)
  70. {
  71. dma_addr_t dma_addr;
  72. unsigned char ctrl;
  73. void *buf;
  74. if (data->flags == MMC_DATA_READ)
  75. buf = data->dest;
  76. else
  77. buf = (void *)data->src;
  78. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  79. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  80. if (host->flags & USE_ADMA64)
  81. ctrl |= SDHCI_CTRL_ADMA64;
  82. else if (host->flags & USE_ADMA)
  83. ctrl |= SDHCI_CTRL_ADMA32;
  84. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  85. if (host->flags & USE_SDMA &&
  86. (host->force_align_buffer ||
  87. (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  88. ((unsigned long)buf & 0x7) != 0x0))) {
  89. *is_aligned = 0;
  90. if (data->flags != MMC_DATA_READ)
  91. memcpy(host->align_buffer, buf, trans_bytes);
  92. buf = host->align_buffer;
  93. }
  94. host->start_addr = dma_map_single(buf, trans_bytes,
  95. mmc_get_dma_dir(data));
  96. if (host->flags & USE_SDMA) {
  97. dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
  98. sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
  99. }
  100. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  101. else if (host->flags & (USE_ADMA | USE_ADMA64)) {
  102. sdhci_prepare_adma_table(host->adma_desc_table, data,
  103. host->start_addr);
  104. sdhci_writel(host, lower_32_bits(host->adma_addr),
  105. SDHCI_ADMA_ADDRESS);
  106. if (host->flags & USE_ADMA64)
  107. sdhci_writel(host, upper_32_bits(host->adma_addr),
  108. SDHCI_ADMA_ADDRESS_HI);
  109. }
  110. #endif
  111. }
  112. #else
  113. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  114. int *is_aligned, int trans_bytes)
  115. {}
  116. #endif
  117. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
  118. {
  119. dma_addr_t start_addr = host->start_addr;
  120. unsigned int stat, rdy, mask, timeout, block = 0;
  121. bool transfer_done = false;
  122. timeout = 1000000;
  123. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  124. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  125. do {
  126. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  127. if (stat & SDHCI_INT_ERROR) {
  128. pr_debug("%s: Error detected in status(0x%X)!\n",
  129. __func__, stat);
  130. return -EIO;
  131. }
  132. if (!transfer_done && (stat & rdy)) {
  133. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  134. continue;
  135. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  136. sdhci_transfer_pio(host, data);
  137. data->dest += data->blocksize;
  138. if (++block >= data->blocks) {
  139. /* Keep looping until the SDHCI_INT_DATA_END is
  140. * cleared, even if we finished sending all the
  141. * blocks.
  142. */
  143. transfer_done = true;
  144. continue;
  145. }
  146. }
  147. if ((host->flags & USE_DMA) && !transfer_done &&
  148. (stat & SDHCI_INT_DMA_END)) {
  149. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  150. if (host->flags & USE_SDMA) {
  151. start_addr &=
  152. ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  153. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  154. start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
  155. start_addr);
  156. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  157. }
  158. }
  159. if (timeout-- > 0)
  160. udelay(10);
  161. else {
  162. printf("%s: Transfer data timeout\n", __func__);
  163. return -ETIMEDOUT;
  164. }
  165. } while (!(stat & SDHCI_INT_DATA_END));
  166. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  167. dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
  168. mmc_get_dma_dir(data));
  169. #endif
  170. return 0;
  171. }
  172. /*
  173. * No command will be sent by driver if card is busy, so driver must wait
  174. * for card ready state.
  175. * Every time when card is busy after timeout then (last) timeout value will be
  176. * increased twice but only if it doesn't exceed global defined maximum.
  177. * Each function call will use last timeout value.
  178. */
  179. #define SDHCI_CMD_MAX_TIMEOUT 3200
  180. #define SDHCI_CMD_DEFAULT_TIMEOUT 100
  181. #define SDHCI_READ_STATUS_TIMEOUT 1000
  182. #ifdef CONFIG_DM_MMC
  183. static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
  184. struct mmc_data *data)
  185. {
  186. struct mmc *mmc = mmc_get_mmc_dev(dev);
  187. #else
  188. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  189. struct mmc_data *data)
  190. {
  191. #endif
  192. struct sdhci_host *host = mmc->priv;
  193. unsigned int stat = 0;
  194. int ret = 0;
  195. int trans_bytes = 0, is_aligned = 1;
  196. u32 mask, flags, mode;
  197. unsigned int time = 0;
  198. int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
  199. ulong start = get_timer(0);
  200. host->start_addr = 0;
  201. /* Timeout unit - ms */
  202. static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
  203. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  204. /* We shouldn't wait for data inihibit for stop commands, even
  205. though they might use busy signaling */
  206. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  207. ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  208. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
  209. mask &= ~SDHCI_DATA_INHIBIT;
  210. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  211. if (time >= cmd_timeout) {
  212. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  213. if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
  214. cmd_timeout += cmd_timeout;
  215. printf("timeout increasing to: %u ms.\n",
  216. cmd_timeout);
  217. } else {
  218. puts("timeout.\n");
  219. return -ECOMM;
  220. }
  221. }
  222. time++;
  223. udelay(1000);
  224. }
  225. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  226. mask = SDHCI_INT_RESPONSE;
  227. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  228. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
  229. mask = SDHCI_INT_DATA_AVAIL;
  230. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  231. flags = SDHCI_CMD_RESP_NONE;
  232. else if (cmd->resp_type & MMC_RSP_136)
  233. flags = SDHCI_CMD_RESP_LONG;
  234. else if (cmd->resp_type & MMC_RSP_BUSY) {
  235. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  236. if (data)
  237. mask |= SDHCI_INT_DATA_END;
  238. } else
  239. flags = SDHCI_CMD_RESP_SHORT;
  240. if (cmd->resp_type & MMC_RSP_CRC)
  241. flags |= SDHCI_CMD_CRC;
  242. if (cmd->resp_type & MMC_RSP_OPCODE)
  243. flags |= SDHCI_CMD_INDEX;
  244. if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  245. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  246. flags |= SDHCI_CMD_DATA;
  247. /* Set Transfer mode regarding to data flag */
  248. if (data) {
  249. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  250. mode = SDHCI_TRNS_BLK_CNT_EN;
  251. trans_bytes = data->blocks * data->blocksize;
  252. if (data->blocks > 1)
  253. mode |= SDHCI_TRNS_MULTI;
  254. if (data->flags == MMC_DATA_READ)
  255. mode |= SDHCI_TRNS_READ;
  256. if (host->flags & USE_DMA) {
  257. mode |= SDHCI_TRNS_DMA;
  258. sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
  259. }
  260. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  261. data->blocksize),
  262. SDHCI_BLOCK_SIZE);
  263. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  264. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  265. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  266. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  267. }
  268. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  269. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  270. start = get_timer(0);
  271. do {
  272. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  273. if (stat & SDHCI_INT_ERROR)
  274. break;
  275. if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
  276. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
  277. return 0;
  278. } else {
  279. printf("%s: Timeout for status update!\n",
  280. __func__);
  281. return -ETIMEDOUT;
  282. }
  283. }
  284. } while ((stat & mask) != mask);
  285. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  286. sdhci_cmd_done(host, cmd);
  287. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  288. } else
  289. ret = -1;
  290. if (!ret && data)
  291. ret = sdhci_transfer_data(host, data);
  292. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  293. udelay(1000);
  294. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  295. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  296. if (!ret) {
  297. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  298. !is_aligned && (data->flags == MMC_DATA_READ))
  299. memcpy(data->dest, host->align_buffer, trans_bytes);
  300. return 0;
  301. }
  302. sdhci_reset(host, SDHCI_RESET_CMD);
  303. sdhci_reset(host, SDHCI_RESET_DATA);
  304. if (stat & SDHCI_INT_TIMEOUT)
  305. return -ETIMEDOUT;
  306. else
  307. return -ECOMM;
  308. }
  309. #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  310. static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  311. {
  312. int err;
  313. struct mmc *mmc = mmc_get_mmc_dev(dev);
  314. struct sdhci_host *host = mmc->priv;
  315. debug("%s\n", __func__);
  316. if (host->ops && host->ops->platform_execute_tuning) {
  317. err = host->ops->platform_execute_tuning(mmc, opcode);
  318. if (err)
  319. return err;
  320. return 0;
  321. }
  322. return 0;
  323. }
  324. #endif
  325. int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  326. {
  327. struct sdhci_host *host = mmc->priv;
  328. unsigned int div, clk = 0, timeout;
  329. /* Wait max 20 ms */
  330. timeout = 200;
  331. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  332. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  333. if (timeout == 0) {
  334. printf("%s: Timeout to wait cmd & data inhibit\n",
  335. __func__);
  336. return -EBUSY;
  337. }
  338. timeout--;
  339. udelay(100);
  340. }
  341. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  342. if (clock == 0)
  343. return 0;
  344. if (host->ops && host->ops->set_delay)
  345. host->ops->set_delay(host);
  346. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  347. /*
  348. * Check if the Host Controller supports Programmable Clock
  349. * Mode.
  350. */
  351. if (host->clk_mul) {
  352. for (div = 1; div <= 1024; div++) {
  353. if ((host->max_clk / div) <= clock)
  354. break;
  355. }
  356. /*
  357. * Set Programmable Clock Mode in the Clock
  358. * Control register.
  359. */
  360. clk = SDHCI_PROG_CLOCK_MODE;
  361. div--;
  362. } else {
  363. /* Version 3.00 divisors must be a multiple of 2. */
  364. if (host->max_clk <= clock) {
  365. div = 1;
  366. } else {
  367. for (div = 2;
  368. div < SDHCI_MAX_DIV_SPEC_300;
  369. div += 2) {
  370. if ((host->max_clk / div) <= clock)
  371. break;
  372. }
  373. }
  374. div >>= 1;
  375. }
  376. } else {
  377. /* Version 2.00 divisors must be a power of 2. */
  378. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  379. if ((host->max_clk / div) <= clock)
  380. break;
  381. }
  382. div >>= 1;
  383. }
  384. if (host->ops && host->ops->set_clock)
  385. host->ops->set_clock(host, div);
  386. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  387. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  388. << SDHCI_DIVIDER_HI_SHIFT;
  389. clk |= SDHCI_CLOCK_INT_EN;
  390. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  391. /* Wait max 20 ms */
  392. timeout = 20;
  393. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  394. & SDHCI_CLOCK_INT_STABLE)) {
  395. if (timeout == 0) {
  396. printf("%s: Internal clock never stabilised.\n",
  397. __func__);
  398. return -EBUSY;
  399. }
  400. timeout--;
  401. udelay(1000);
  402. }
  403. clk |= SDHCI_CLOCK_CARD_EN;
  404. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  405. return 0;
  406. }
  407. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  408. {
  409. u8 pwr = 0;
  410. if (power != (unsigned short)-1) {
  411. switch (1 << power) {
  412. case MMC_VDD_165_195:
  413. pwr = SDHCI_POWER_180;
  414. break;
  415. case MMC_VDD_29_30:
  416. case MMC_VDD_30_31:
  417. pwr = SDHCI_POWER_300;
  418. break;
  419. case MMC_VDD_32_33:
  420. case MMC_VDD_33_34:
  421. pwr = SDHCI_POWER_330;
  422. break;
  423. }
  424. }
  425. if (pwr == 0) {
  426. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  427. return;
  428. }
  429. pwr |= SDHCI_POWER_ON;
  430. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  431. }
  432. void sdhci_set_uhs_timing(struct sdhci_host *host)
  433. {
  434. struct mmc *mmc = host->mmc;
  435. u32 reg;
  436. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  437. reg &= ~SDHCI_CTRL_UHS_MASK;
  438. switch (mmc->selected_mode) {
  439. case UHS_SDR50:
  440. case MMC_HS_52:
  441. reg |= SDHCI_CTRL_UHS_SDR50;
  442. break;
  443. case UHS_DDR50:
  444. case MMC_DDR_52:
  445. reg |= SDHCI_CTRL_UHS_DDR50;
  446. break;
  447. case UHS_SDR104:
  448. case MMC_HS_200:
  449. reg |= SDHCI_CTRL_UHS_SDR104;
  450. break;
  451. case MMC_HS_400:
  452. reg |= SDHCI_CTRL_HS400;
  453. break;
  454. default:
  455. reg |= SDHCI_CTRL_UHS_SDR12;
  456. }
  457. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  458. }
  459. static void sdhci_set_voltage(struct sdhci_host *host)
  460. {
  461. if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
  462. struct mmc *mmc = (struct mmc *)host->mmc;
  463. u32 ctrl;
  464. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  465. switch (mmc->signal_voltage) {
  466. case MMC_SIGNAL_VOLTAGE_330:
  467. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  468. if (mmc->vqmmc_supply) {
  469. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
  470. pr_err("failed to disable vqmmc-supply\n");
  471. return;
  472. }
  473. if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
  474. pr_err("failed to set vqmmc-voltage to 3.3V\n");
  475. return;
  476. }
  477. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
  478. pr_err("failed to enable vqmmc-supply\n");
  479. return;
  480. }
  481. }
  482. #endif
  483. if (IS_SD(mmc)) {
  484. ctrl &= ~SDHCI_CTRL_VDD_180;
  485. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  486. }
  487. /* Wait for 5ms */
  488. mdelay(5);
  489. /* 3.3V regulator output should be stable within 5 ms */
  490. if (IS_SD(mmc)) {
  491. if (ctrl & SDHCI_CTRL_VDD_180) {
  492. pr_err("3.3V regulator output did not become stable\n");
  493. return;
  494. }
  495. }
  496. break;
  497. case MMC_SIGNAL_VOLTAGE_180:
  498. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  499. if (mmc->vqmmc_supply) {
  500. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
  501. pr_err("failed to disable vqmmc-supply\n");
  502. return;
  503. }
  504. if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
  505. pr_err("failed to set vqmmc-voltage to 1.8V\n");
  506. return;
  507. }
  508. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
  509. pr_err("failed to enable vqmmc-supply\n");
  510. return;
  511. }
  512. }
  513. #endif
  514. if (IS_SD(mmc)) {
  515. ctrl |= SDHCI_CTRL_VDD_180;
  516. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  517. }
  518. /* Wait for 5 ms */
  519. mdelay(5);
  520. /* 1.8V regulator output has to be stable within 5 ms */
  521. if (IS_SD(mmc)) {
  522. if (!(ctrl & SDHCI_CTRL_VDD_180)) {
  523. pr_err("1.8V regulator output did not become stable\n");
  524. return;
  525. }
  526. }
  527. break;
  528. default:
  529. /* No signal voltage switch required */
  530. return;
  531. }
  532. }
  533. }
  534. void sdhci_set_control_reg(struct sdhci_host *host)
  535. {
  536. sdhci_set_voltage(host);
  537. sdhci_set_uhs_timing(host);
  538. }
  539. #ifdef CONFIG_DM_MMC
  540. static int sdhci_set_ios(struct udevice *dev)
  541. {
  542. struct mmc *mmc = mmc_get_mmc_dev(dev);
  543. #else
  544. static int sdhci_set_ios(struct mmc *mmc)
  545. {
  546. #endif
  547. u32 ctrl;
  548. struct sdhci_host *host = mmc->priv;
  549. bool no_hispd_bit = false;
  550. if (host->ops && host->ops->set_control_reg)
  551. host->ops->set_control_reg(host);
  552. if (mmc->clock != host->clock)
  553. sdhci_set_clock(mmc, mmc->clock);
  554. if (mmc->clk_disable)
  555. sdhci_set_clock(mmc, 0);
  556. /* Set bus width */
  557. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  558. if (mmc->bus_width == 8) {
  559. ctrl &= ~SDHCI_CTRL_4BITBUS;
  560. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  561. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  562. ctrl |= SDHCI_CTRL_8BITBUS;
  563. } else {
  564. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  565. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  566. ctrl &= ~SDHCI_CTRL_8BITBUS;
  567. if (mmc->bus_width == 4)
  568. ctrl |= SDHCI_CTRL_4BITBUS;
  569. else
  570. ctrl &= ~SDHCI_CTRL_4BITBUS;
  571. }
  572. if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
  573. (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
  574. ctrl &= ~SDHCI_CTRL_HISPD;
  575. no_hispd_bit = true;
  576. }
  577. if (!no_hispd_bit) {
  578. if (mmc->selected_mode == MMC_HS ||
  579. mmc->selected_mode == SD_HS ||
  580. mmc->selected_mode == MMC_DDR_52 ||
  581. mmc->selected_mode == MMC_HS_200 ||
  582. mmc->selected_mode == MMC_HS_400 ||
  583. mmc->selected_mode == UHS_SDR25 ||
  584. mmc->selected_mode == UHS_SDR50 ||
  585. mmc->selected_mode == UHS_SDR104 ||
  586. mmc->selected_mode == UHS_DDR50)
  587. ctrl |= SDHCI_CTRL_HISPD;
  588. else
  589. ctrl &= ~SDHCI_CTRL_HISPD;
  590. }
  591. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  592. /* If available, call the driver specific "post" set_ios() function */
  593. if (host->ops && host->ops->set_ios_post)
  594. return host->ops->set_ios_post(host);
  595. return 0;
  596. }
  597. static int sdhci_init(struct mmc *mmc)
  598. {
  599. struct sdhci_host *host = mmc->priv;
  600. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
  601. struct udevice *dev = mmc->dev;
  602. gpio_request_by_name(dev, "cd-gpios", 0,
  603. &host->cd_gpio, GPIOD_IS_IN);
  604. #endif
  605. sdhci_reset(host, SDHCI_RESET_ALL);
  606. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  607. host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  608. /*
  609. * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
  610. * is defined.
  611. */
  612. host->force_align_buffer = true;
  613. #else
  614. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
  615. host->align_buffer = memalign(8, 512 * 1024);
  616. if (!host->align_buffer) {
  617. printf("%s: Aligned buffer alloc failed!!!\n",
  618. __func__);
  619. return -ENOMEM;
  620. }
  621. }
  622. #endif
  623. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  624. if (host->ops && host->ops->get_cd)
  625. host->ops->get_cd(host);
  626. /* Enable only interrupts served by the SD controller */
  627. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  628. SDHCI_INT_ENABLE);
  629. /* Mask all sdhci interrupt sources */
  630. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  631. return 0;
  632. }
  633. #ifdef CONFIG_DM_MMC
  634. int sdhci_probe(struct udevice *dev)
  635. {
  636. struct mmc *mmc = mmc_get_mmc_dev(dev);
  637. return sdhci_init(mmc);
  638. }
  639. static int sdhci_deferred_probe(struct udevice *dev)
  640. {
  641. int err;
  642. struct mmc *mmc = mmc_get_mmc_dev(dev);
  643. struct sdhci_host *host = mmc->priv;
  644. if (host->ops && host->ops->deferred_probe) {
  645. err = host->ops->deferred_probe(host);
  646. if (err)
  647. return err;
  648. }
  649. return 0;
  650. }
  651. static int sdhci_get_cd(struct udevice *dev)
  652. {
  653. struct mmc *mmc = mmc_get_mmc_dev(dev);
  654. struct sdhci_host *host = mmc->priv;
  655. int value;
  656. /* If nonremovable, assume that the card is always present. */
  657. if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
  658. return 1;
  659. /* If polling, assume that the card is always present. */
  660. if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
  661. return 1;
  662. #if CONFIG_IS_ENABLED(DM_GPIO)
  663. value = dm_gpio_get_value(&host->cd_gpio);
  664. if (value >= 0) {
  665. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  666. return !value;
  667. else
  668. return value;
  669. }
  670. #endif
  671. value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
  672. SDHCI_CARD_PRESENT);
  673. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  674. return !value;
  675. else
  676. return value;
  677. }
  678. const struct dm_mmc_ops sdhci_ops = {
  679. .send_cmd = sdhci_send_command,
  680. .set_ios = sdhci_set_ios,
  681. .get_cd = sdhci_get_cd,
  682. .deferred_probe = sdhci_deferred_probe,
  683. #ifdef MMC_SUPPORTS_TUNING
  684. .execute_tuning = sdhci_execute_tuning,
  685. #endif
  686. };
  687. #else
  688. static const struct mmc_ops sdhci_ops = {
  689. .send_cmd = sdhci_send_command,
  690. .set_ios = sdhci_set_ios,
  691. .init = sdhci_init,
  692. };
  693. #endif
  694. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  695. u32 f_max, u32 f_min)
  696. {
  697. u32 caps, caps_1 = 0;
  698. #if CONFIG_IS_ENABLED(DM_MMC)
  699. u64 dt_caps, dt_caps_mask;
  700. dt_caps_mask = dev_read_u64_default(host->mmc->dev,
  701. "sdhci-caps-mask", 0);
  702. dt_caps = dev_read_u64_default(host->mmc->dev,
  703. "sdhci-caps", 0);
  704. caps = ~lower_32_bits(dt_caps_mask) &
  705. sdhci_readl(host, SDHCI_CAPABILITIES);
  706. caps |= lower_32_bits(dt_caps);
  707. #else
  708. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  709. #endif
  710. debug("%s, caps: 0x%x\n", __func__, caps);
  711. #ifdef CONFIG_MMC_SDHCI_SDMA
  712. if ((caps & SDHCI_CAN_DO_SDMA)) {
  713. host->flags |= USE_SDMA;
  714. } else {
  715. debug("%s: Your controller doesn't support SDMA!!\n",
  716. __func__);
  717. }
  718. #endif
  719. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  720. if (!(caps & SDHCI_CAN_DO_ADMA2)) {
  721. printf("%s: Your controller doesn't support SDMA!!\n",
  722. __func__);
  723. return -EINVAL;
  724. }
  725. host->adma_desc_table = sdhci_adma_init();
  726. host->adma_addr = (dma_addr_t)host->adma_desc_table;
  727. #ifdef CONFIG_DMA_ADDR_T_64BIT
  728. host->flags |= USE_ADMA64;
  729. #else
  730. host->flags |= USE_ADMA;
  731. #endif
  732. #endif
  733. if (host->quirks & SDHCI_QUIRK_REG32_RW)
  734. host->version =
  735. sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
  736. else
  737. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  738. cfg->name = host->name;
  739. #ifndef CONFIG_DM_MMC
  740. cfg->ops = &sdhci_ops;
  741. #endif
  742. /* Check whether the clock multiplier is supported or not */
  743. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  744. #if CONFIG_IS_ENABLED(DM_MMC)
  745. caps_1 = ~upper_32_bits(dt_caps_mask) &
  746. sdhci_readl(host, SDHCI_CAPABILITIES_1);
  747. caps_1 |= upper_32_bits(dt_caps);
  748. #else
  749. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  750. #endif
  751. debug("%s, caps_1: 0x%x\n", __func__, caps_1);
  752. host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
  753. SDHCI_CLOCK_MUL_SHIFT;
  754. }
  755. if (host->max_clk == 0) {
  756. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  757. host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
  758. SDHCI_CLOCK_BASE_SHIFT;
  759. else
  760. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
  761. SDHCI_CLOCK_BASE_SHIFT;
  762. host->max_clk *= 1000000;
  763. if (host->clk_mul)
  764. host->max_clk *= host->clk_mul;
  765. }
  766. if (host->max_clk == 0) {
  767. printf("%s: Hardware doesn't specify base clock frequency\n",
  768. __func__);
  769. return -EINVAL;
  770. }
  771. if (f_max && (f_max < host->max_clk))
  772. cfg->f_max = f_max;
  773. else
  774. cfg->f_max = host->max_clk;
  775. if (f_min)
  776. cfg->f_min = f_min;
  777. else {
  778. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  779. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
  780. else
  781. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
  782. }
  783. cfg->voltages = 0;
  784. if (caps & SDHCI_CAN_VDD_330)
  785. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  786. if (caps & SDHCI_CAN_VDD_300)
  787. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  788. if (caps & SDHCI_CAN_VDD_180)
  789. cfg->voltages |= MMC_VDD_165_195;
  790. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  791. cfg->voltages |= host->voltages;
  792. if (caps & SDHCI_CAN_DO_HISPD)
  793. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  794. cfg->host_caps |= MMC_MODE_4BIT;
  795. /* Since Host Controller Version3.0 */
  796. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  797. if (!(caps & SDHCI_CAN_DO_8BIT))
  798. cfg->host_caps &= ~MMC_MODE_8BIT;
  799. }
  800. if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
  801. cfg->host_caps &= ~MMC_MODE_HS;
  802. cfg->host_caps &= ~MMC_MODE_HS_52MHz;
  803. }
  804. if (!(cfg->voltages & MMC_VDD_165_195) ||
  805. (host->quirks & SDHCI_QUIRK_NO_1_8_V))
  806. caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  807. SDHCI_SUPPORT_DDR50);
  808. if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  809. SDHCI_SUPPORT_DDR50))
  810. cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  811. if (caps_1 & SDHCI_SUPPORT_SDR104) {
  812. cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  813. /*
  814. * SD3.0: SDR104 is supported so (for eMMC) the caps2
  815. * field can be promoted to support HS200.
  816. */
  817. cfg->host_caps |= MMC_CAP(MMC_HS_200);
  818. } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  819. cfg->host_caps |= MMC_CAP(UHS_SDR50);
  820. }
  821. if (caps_1 & SDHCI_SUPPORT_DDR50)
  822. cfg->host_caps |= MMC_CAP(UHS_DDR50);
  823. if (host->host_caps)
  824. cfg->host_caps |= host->host_caps;
  825. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  826. return 0;
  827. }
  828. #ifdef CONFIG_BLK
  829. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  830. {
  831. return mmc_bind(dev, mmc, cfg);
  832. }
  833. #else
  834. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
  835. {
  836. int ret;
  837. ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
  838. if (ret)
  839. return ret;
  840. host->mmc = mmc_create(&host->cfg, host);
  841. if (host->mmc == NULL) {
  842. printf("%s: mmc create fail!\n", __func__);
  843. return -ENOMEM;
  844. }
  845. return 0;
  846. }
  847. #endif