mux-k2g.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * K2G EVM: Pinmux configuration
  4. *
  5. * (C) Copyright 2015
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <hang.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/mux-k2g.h>
  12. #include <asm/arch/hardware.h>
  13. #include "board.h"
  14. struct pin_cfg k2g_generic_pin_cfg[] = {
  15. /* UART0 */
  16. { 115, MODE(0) }, /* SOC_UART0_RXD */
  17. { 116, MODE(0) }, /* SOC_UART0_TXD */
  18. /* I2C 0 */
  19. { 223, MODE(0) }, /* SOC_I2C0_SCL */
  20. { 224, MODE(0) }, /* SOC_I2C0_SDA */
  21. /* I2C 1 */
  22. { 225, MODE(0) }, /* SOC_I2C1_SCL */
  23. { 226, MODE(0) }, /* SOC_I2C1_SDA */
  24. { MAX_PIN_N, }
  25. };
  26. struct pin_cfg k2g_evm_pin_cfg[] = {
  27. /* GPMC */
  28. { 0, MODE(0) }, /* GPMCAD0 */
  29. { 1, MODE(0) }, /* GPMCAD1 */
  30. { 2, MODE(0) }, /* GPMCAD2 */
  31. { 3, MODE(0) }, /* GPMCAD3 */
  32. { 4, MODE(0) }, /* GPMCAD4 */
  33. { 5, MODE(0) }, /* GPMCAD5 */
  34. { 6, MODE(0) }, /* GPMCAD6 */
  35. { 7, MODE(0) }, /* GPMCAD7 */
  36. { 8, MODE(0) }, /* GPMCAD8 */
  37. { 9, MODE(0) }, /* GPMCAD9 */
  38. { 10, MODE(0) }, /* GPMCAD10 */
  39. { 11, MODE(0) }, /* GPMCAD11 */
  40. { 12, MODE(0) }, /* GPMCAD12 */
  41. { 13, MODE(0) }, /* GPMCAD13 */
  42. { 14, MODE(0) }, /* GPMCAD14 */
  43. { 15, MODE(0) }, /* GPMCAD15 */
  44. { 17, MODE(0) }, /* GPMCADVNALE */
  45. { 18, MODE(0) }, /* GPMCOENREN */
  46. { 19, MODE(0) }, /* GPMCWEN */
  47. { 20, MODE(0) }, /* GPMCBE0NCLE */
  48. { 22, MODE(0) }, /* GPMCWAIT0 */
  49. { 24, MODE(0) }, /* GPMCWPN */
  50. { 26, MODE(0) }, /* GPMCCSN0 */
  51. /* GPIOs */
  52. { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */
  53. { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */
  54. { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */
  55. { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */
  56. { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */
  57. { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */
  58. { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */
  59. { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */
  60. { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */
  61. { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */
  62. { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */
  63. { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */
  64. { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/
  65. { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */
  66. { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */
  67. { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */
  68. { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */
  69. { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */
  70. /* MLB */
  71. { 23, MODE(2) }, /* SOC_MLBCLK */
  72. { 25, MODE(2) }, /* SOC_MLBSIG */
  73. { 27, MODE(2) }, /* SOC_MLBDAT */
  74. /* DSS */
  75. { 30, MODE(0) }, /* SOC_DSSDATA23 */
  76. { 31, MODE(0) }, /* SOC_DSSDATA22 */
  77. { 32, MODE(0) }, /* SOC_DSSDATA21 */
  78. { 33, MODE(0) }, /* SOC_DSSDATA20 */
  79. { 34, MODE(0) }, /* SOC_DSSDATA19 */
  80. { 35, MODE(0) }, /* SOC_DSSDATA18 */
  81. { 36, MODE(0) }, /* SOC_DSSDATA17 */
  82. { 37, MODE(0) }, /* SOC_DSSDATA16 */
  83. { 38, MODE(0) }, /* SOC_DSSDATA15 */
  84. { 39, MODE(0) }, /* SOC_DSSDATA14 */
  85. { 40, MODE(0) }, /* SOC_DSSDATA13 */
  86. { 41, MODE(0) }, /* SOC_DSSDATA12 */
  87. { 42, MODE(0) }, /* SOC_DSSDATA11 */
  88. { 43, MODE(0) }, /* SOC_DSSDATA10 */
  89. { 44, MODE(0) }, /* SOC_DSSDATA9 */
  90. { 45, MODE(0) }, /* SOC_DSSDATA8 */
  91. { 46, MODE(0) }, /* SOC_DSSDATA7 */
  92. { 47, MODE(0) }, /* SOC_DSSDATA6 */
  93. { 48, MODE(0) }, /* SOC_DSSDATA5 */
  94. { 49, MODE(0) }, /* SOC_DSSDATA4 */
  95. { 50, MODE(0) }, /* SOC_DSSDATA3 */
  96. { 51, MODE(0) }, /* SOC_DSSDATA2 */
  97. { 52, MODE(0) }, /* SOC_DSSDATA1 */
  98. { 53, MODE(0) }, /* SOC_DSSDATA0 */
  99. { 54, MODE(0) }, /* SOC_DSSVSYNC */
  100. { 55, MODE(0) }, /* SOC_DSSHSYNC */
  101. { 56, MODE(0) }, /* SOC_DSSPCLK */
  102. { 57, MODE(0) }, /* SOC_DSS_DE */
  103. { 58, MODE(0) }, /* SOC_DSS_FID */
  104. { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */
  105. /* MMC1 */
  106. { 59, MODE(0) }, /* SOC_MMC1_DAT7 */
  107. { 60, MODE(0) }, /* SOC_MMC1_DAT6 */
  108. { 61, MODE(0) }, /* SOC_MMC1_DAT5 */
  109. { 62, MODE(0) }, /* SOC_MMC1_DAT4 */
  110. { 63, MODE(0) }, /* SOC_MMC1_DAT3 */
  111. { 64, MODE(0) }, /* SOC_MMC1_DAT2 */
  112. { 65, MODE(0) }, /* SOC_MMC1_DAT1 */
  113. { 66, MODE(0) }, /* SOC_MMC1_DAT0 */
  114. { 67, MODE(0) }, /* SOC_MMC1_CLK */
  115. { 68, MODE(0) }, /* SOC_MMC1_CMD */
  116. { 69, MODE(0) }, /* MMC1SDCD TP125 */
  117. { 70, MODE(0) }, /* SOC_MMC1_SDWP */
  118. { 71, MODE(0) }, /* MMC1POW TP124 */
  119. /* EMAC */
  120. { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
  121. { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
  122. { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
  123. { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
  124. { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
  125. { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
  126. { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
  127. { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
  128. { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
  129. { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
  130. { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
  131. { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
  132. /* MDIO */
  133. { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
  134. { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
  135. /* PWM */
  136. { 73, MODE(4) }, /* SOC_EHRPWM3A */
  137. { 74, MODE(4) }, /* SOC_EHRPWM3B */
  138. { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */
  139. { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */
  140. { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */
  141. { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */
  142. { 199, MODE(4) }, /* SOC_EHRPWM4A */
  143. { 200, MODE(4) }, /* SOC_EHRPWM4B */
  144. { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */
  145. { 219, MODE(4) }, /* SOC_EHRPWM5A */
  146. { 220, MODE(4) }, /* SOC_EHRPWM5B */
  147. { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */
  148. /* SPI3 */
  149. { 86, MODE(1) }, /* SOC_SPI3_SCS0 */
  150. { 88, MODE(1) }, /* SOC_SPI3_CLK */
  151. { 89, MODE(1) }, /* SOC_SPI3_MISO */
  152. { 90, MODE(1) }, /* SOC_SPI3_MOSI */
  153. /* CLK */
  154. { 97, MODE(0) }, /* SMD - TP132 */
  155. /* SPI0 */
  156. { 100, MODE(0) }, /* SOC_SPI0_SCS0 */
  157. { 101, MODE(0) }, /* SOC_SPI0_SCS1 */
  158. { 102, MODE(0) }, /* SOC_SPI0_CLK */
  159. { 103, MODE(0) }, /* SOC_SPI0_MISO */
  160. { 104, MODE(0) }, /* SOC_SPI0_MOSI */
  161. /* SPI1 NORFLASH */
  162. { 105, MODE(0) }, /* SOC_SPI1_SCS0 */
  163. { 107, MODE(0) }, /* SOC_SPI1_CLK */
  164. { 108, MODE(0) }, /* SOC_SPI1_MISO */
  165. { 109, MODE(0) }, /* SOC_SPI1_MOSI */
  166. /* SPI2 */
  167. { 110, MODE(0) }, /* SOC_SPI2_SCS0 */
  168. { 111, MODE(1) }, /* SOC_HOUT */
  169. { 112, MODE(0) }, /* SOC_SPI2_CLK */
  170. { 113, MODE(0) }, /* SOC_SPI2_MISO */
  171. { 114, MODE(0) }, /* SOC_SPI2_MOSI */
  172. /* UART0 */
  173. { 115, MODE(0) }, /* SOC_UART0_RXD */
  174. { 116, MODE(0) }, /* SOC_UART0_TXD */
  175. { 117, MODE(0) }, /* SOC_UART0_CTSn */
  176. { 118, MODE(0) }, /* SOC_UART0_RTSn */
  177. /* UART1 */
  178. { 119, MODE(0) }, /* SOC_UART1_RXD */
  179. { 120, MODE(0) }, /* SOC_UART1_TXD */
  180. { 121, MODE(0) }, /* SOC_UART1_CTSn */
  181. { 122, MODE(0) }, /* SOC_UART1_RTSn */
  182. /* UART2 */
  183. { 123, MODE(0) }, /* SOC_UART2_RXD */
  184. { 124, MODE(0) }, /* SOC_UART2_TXD */
  185. { 125, MODE(0) }, /* UART0_TXVR_EN */
  186. { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */
  187. /* DCAN */
  188. { 127, MODE(0) }, /* SOC_DCAN0_TX */
  189. { 128, MODE(0) }, /* SOC_DCAN0_RX */
  190. { 137, MODE(1) }, /* SOC_DCAN1_TX */
  191. { 138, MODE(1) }, /* SOC_DCAN1_RX */
  192. /* QSPI */
  193. { 129, MODE(0) }, /* SOC_QSPI_CLK */
  194. { 130, MODE(0) }, /* SOC_QSPI_RTCLK */
  195. { 131, MODE(0) }, /* SOC_QSPI_D0 */
  196. { 132, MODE(0) }, /* SOC_QSPI_D1 */
  197. { 133, MODE(0) }, /* SOC_QSPI_D2 */
  198. { 134, MODE(0) }, /* SOC_QSPI_D3 */
  199. { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
  200. { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */
  201. /* MCASP2 */
  202. { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
  203. { 140, MODE(4) }, /* SOC_MCASP2AXR1 */
  204. { 141, MODE(4) }, /* SOC_MCASP2AXR2 */
  205. { 142, MODE(4) }, /* SOC_MCASP2AXR3 */
  206. { 143, MODE(4) }, /* SOC_MCASP2AXR4 */
  207. { 144, MODE(4) }, /* SOC_MCASP2AXR5 */
  208. { 145, MODE(4) }, /* SOC_McASP2ACLKR */
  209. { 146, MODE(4) }, /* SOC_McASP2FSR */
  210. { 147, MODE(4) }, /* SOC_McASP2AHCLKR */
  211. { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */
  212. { 149, MODE(4) }, /* SOC_McASP2FSX */
  213. { 150, MODE(4) }, /* SOC_McASP2AHCLKX */
  214. { 151, MODE(4) }, /* SOC_McASP2ACLKX */
  215. /* MCASP1 */
  216. { 152, MODE(4) }, /* SOC_MCASP1ACLKR */
  217. { 153, MODE(4) }, /* SOC_MCASP1FSR */
  218. { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */
  219. { 155, MODE(4) }, /* SOC_MCASP1ACLKX */
  220. { 156, MODE(4) }, /* SOC_MCASP1FSX */
  221. { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */
  222. { 158, MODE(4) }, /* SOC_MCASP1AMUTE */
  223. { 159, MODE(4) }, /* SOC_MCASP1AXR0 */
  224. { 160, MODE(4) }, /* SOC_MCASP1AXR1 */
  225. { 161, MODE(4) }, /* SOC_MCASP1AXR2 */
  226. { 162, MODE(4) }, /* SOC_MCASP1AXR3 */
  227. { 163, MODE(4) }, /* SOC_MCASP1AXR4 */
  228. { 164, MODE(4) }, /* SOC_MCASP1AXR5 */
  229. { 165, MODE(4) }, /* SOC_MCASP1AXR6 */
  230. { 166, MODE(4) }, /* SOC_MCASP1AXR7 */
  231. { 167, MODE(4) }, /* SOC_MCASP1AXR8 */
  232. { 168, MODE(4) }, /* SOC_MCASP1AXR9 */
  233. /* MCASP0 */
  234. { 169, MODE(4) }, /* SOC_MCASP0AMUTE */
  235. { 170, MODE(4) }, /* SOC_MCASP0ACLKR */
  236. { 171, MODE(4) }, /* SOC_MCASP0FSR */
  237. { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */
  238. { 173, MODE(4) }, /* SOC_MCASP0ACLKX */
  239. { 174, MODE(4) }, /* SOC_MCASP0FSX */
  240. { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */
  241. { 176, MODE(4) }, /* SOC_MCASP0AXR0 */
  242. { 177, MODE(4) }, /* SOC_MCASP0AXR1 */
  243. { 178, MODE(4) }, /* SOC_MCASP0AXR2 */
  244. { 179, MODE(4) }, /* SOC_MCASP0AXR3 */
  245. { 180, MODE(4) }, /* SOC_MCASP0AXR4 */
  246. { 181, MODE(4) }, /* SOC_MCASP0AXR5 */
  247. { 182, MODE(4) }, /* SOC_MCASP0AXR6 */
  248. { 183, MODE(4) }, /* SOC_MCASP0AXR7 */
  249. { 184, MODE(4) }, /* SOC_MCASP0AXR8 */
  250. { 185, MODE(4) }, /* SOC_MCASP0AXR9 */
  251. { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
  252. { 188, MODE(4) }, /* SOC_MCASP0AXR12 */
  253. { 189, MODE(4) }, /* SOC_MCASP0AXR13 */
  254. { 190, MODE(4) }, /* SOC_MCASP0AXR14 */
  255. { 191, MODE(4) }, /* SOC_MCASP0AXR15 */
  256. /* MMC0 */
  257. { 192, MODE(2) }, /* SOC_MMC0_DAT3 */
  258. { 193, MODE(2) }, /* SOC_MMC0_DAT2 */
  259. { 194, MODE(2) }, /* SOC_MMC0_DAT1 */
  260. { 195, MODE(2) }, /* SOC_MMC0_DAT0 */
  261. { 196, MODE(2) }, /* SOC_MMC0_CLK */
  262. { 197, MODE(2) }, /* SOC_MMC0_CMD */
  263. { 187, MODE(2) }, /* SOC_MMC0_SDCD */
  264. /* McBSP */
  265. { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */
  266. { 29, MODE(2) }, /* SOC_TIMO1 */
  267. { 210, MODE(2) }, /* SOC_MCBSPDR */
  268. { 211, MODE(2) }, /* SOC_MCBSPDX */
  269. { 212, MODE(2) }, /* SOC_MCBSPFSX */
  270. { 213, MODE(2) }, /* SOC_MCBSPCLKX */
  271. { 214, MODE(2) }, /* SOC_MCBSPFSR */
  272. { 215, MODE(2) }, /* SOC_MCBSPCLKR */
  273. /* I2C */
  274. { 223, MODE(0) }, /* SOC_I2C0_SCL */
  275. { 224, MODE(0) }, /* SOC_I2C0_SDA */
  276. { 225, MODE(0) }, /* SOC_I2C1_SCL */
  277. { 226, MODE(0) }, /* SOC_I2C1_SDA */
  278. { 227, MODE(0) }, /* SOC_I2C2_SCL */
  279. { 228, MODE(0) }, /* SOC_I2C2_SDA */
  280. { 229, MODE(0) }, /* NMIz */
  281. { 230, MODE(0) }, /* LRESETz */
  282. { 231, MODE(0) }, /* LRESETNMIENz */
  283. { 235, MODE(0) },
  284. { 236, MODE(0) },
  285. { 237, MODE(0) },
  286. { 238, MODE(0) },
  287. { 239, MODE(0) },
  288. { 240, MODE(0) },
  289. { 241, MODE(0) },
  290. { 242, MODE(0) },
  291. { 243, MODE(0) },
  292. { 244, MODE(0) },
  293. { 258, MODE(0) }, /* USB0DRVVBUS */
  294. { 259, MODE(0) }, /* USB1DRVVBUS */
  295. { MAX_PIN_N, }
  296. };
  297. struct pin_cfg k2g_ice_evm_pin_cfg[] = {
  298. /* MMC 1 */
  299. { 63, MODE(0) | PIN_PTD }, /* MMC1_DAT3.MMC1_DAT3 */
  300. { 64, MODE(0) | PIN_PTU }, /* MMC1_DAT2.MMC1_DAT2 */
  301. { 65, MODE(0) | PIN_PTU }, /* MMC1_DAT1.MMC1_DAT1 */
  302. { 66, MODE(0) | PIN_PTD }, /* MMC1_DAT0.MMC1_DAT0 */
  303. { 67, MODE(0) | PIN_PTD }, /* MMC1_CLK.MMC1_CLK */
  304. { 68, MODE(0) | PIN_PTD }, /* MMC1_CMD.MMC1_CMD */
  305. { 69, MODE(3) | PIN_PTU }, /* MMC1_SDCD.GPIO0_69 */
  306. { 70, MODE(0) | PIN_PTU }, /* MMC1_SDWP.MMC1_SDWP */
  307. { 71, MODE(0) | PIN_PTD }, /* MMC1_POW.MMC1_POW */
  308. /* I2C 0 */
  309. { 223, MODE(0) }, /* SOC_I2C0_SCL */
  310. { 224, MODE(0) }, /* SOC_I2C0_SDA */
  311. /* QSPI */
  312. { 129, MODE(0) }, /* SOC_QSPI_CLK */
  313. { 130, MODE(0) }, /* SOC_QSPI_RTCLK */
  314. { 131, MODE(0) }, /* SOC_QSPI_D0 */
  315. { 132, MODE(0) }, /* SOC_QSPI_D1 */
  316. { 133, MODE(0) }, /* SOC_QSPI_D2 */
  317. { 134, MODE(0) }, /* SOC_QSPI_D3 */
  318. { 135, MODE(0) }, /* SOC_QSPI_CSN0 */
  319. /* EMAC */
  320. { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
  321. { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
  322. { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
  323. { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
  324. { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
  325. { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
  326. { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
  327. { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
  328. { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
  329. { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
  330. { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
  331. { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
  332. /* MDIO */
  333. { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
  334. { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
  335. /* ICSS1 Padconf Workaround */
  336. { 202, MODE(1) | PIN_PDIS }, /* PR1_PRU1_GPO1.PR1_PRU1_GPI1 (PR1_MII1_RXD1) */
  337. { MAX_PIN_N, }
  338. };
  339. void k2g_mux_config(void)
  340. {
  341. if (!board_ti_was_eeprom_read()) {
  342. configure_pin_mux(k2g_generic_pin_cfg);
  343. } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
  344. configure_pin_mux(k2g_evm_pin_cfg);
  345. } else if (board_is_k2g_ice() || board_is_k2g_i1()) {
  346. configure_pin_mux(k2g_ice_evm_pin_cfg);
  347. } else {
  348. puts("Unknown board, cannot configure pinmux.");
  349. hang();
  350. }
  351. }