k3-j721e-r5-common-proc-board.dts 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "k3-j721e-som-p0.dtsi"
  7. #include "k3-j721e-ddr-evm-lp4-4266.dtsi"
  8. #include "k3-j721e-ddr.dtsi"
  9. / {
  10. aliases {
  11. remoteproc0 = &sysctrler;
  12. remoteproc1 = &a72_0;
  13. };
  14. chosen {
  15. stdout-path = "serial2:115200n8";
  16. tick-timer = &timer1;
  17. };
  18. a72_0: a72@0 {
  19. compatible = "ti,am654-rproc";
  20. reg = <0x0 0x00a90000 0x0 0x10>;
  21. power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  22. <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
  23. resets = <&k3_reset 202 0>;
  24. clocks = <&k3_clks 61 1>;
  25. assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
  26. assigned-clock-rates = <2000000000>, <200000000>;
  27. ti,sci = <&dmsc>;
  28. ti,sci-proc-id = <32>;
  29. ti,sci-host-id = <10>;
  30. u-boot,dm-spl;
  31. };
  32. clk_200mhz: dummy_clock_200mhz {
  33. compatible = "fixed-clock";
  34. #clock-cells = <0>;
  35. clock-frequency = <200000000>;
  36. u-boot,dm-spl;
  37. };
  38. clk_19_2mhz: dummy_clock_19_2mhz {
  39. compatible = "fixed-clock";
  40. #clock-cells = <0>;
  41. clock-frequency = <19200000>;
  42. u-boot,dm-spl;
  43. };
  44. };
  45. &cbass_mcu_wakeup {
  46. mcu_secproxy: secproxy@28380000 {
  47. u-boot,dm-spl;
  48. compatible = "ti,am654-secure-proxy";
  49. reg = <0x0 0x2a380000 0x0 0x80000>,
  50. <0x0 0x2a400000 0x0 0x80000>,
  51. <0x0 0x2a480000 0x0 0x80000>;
  52. reg-names = "rt", "scfg", "target_data";
  53. #mbox-cells = <1>;
  54. };
  55. sysctrler: sysctrler {
  56. u-boot,dm-spl;
  57. compatible = "ti,am654-system-controller";
  58. mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
  59. mbox-names = "tx", "rx";
  60. };
  61. wkup_vtm0: wkup_vtm@42040000 {
  62. compatible = "ti,am654-vtm", "ti,j721e-avs";
  63. reg = <0x0 0x42040000 0x0 0x330>;
  64. power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  65. #thermal-sensor-cells = <1>;
  66. };
  67. dm_tifs: dm-tifs {
  68. compatible = "ti,j721e-dm-sci";
  69. ti,host-id = <3>;
  70. ti,secure-host;
  71. mbox-names = "rx", "tx";
  72. mboxes= <&mcu_secproxy 21>,
  73. <&mcu_secproxy 23>;
  74. u-boot,dm-spl;
  75. };
  76. };
  77. &cbass_main {
  78. main_esm: esm@700000 {
  79. compatible = "ti,j721e-esm";
  80. reg = <0x0 0x700000 0x0 0x1000>;
  81. ti,esm-pins = <344>, <345>;
  82. u-boot,dm-spl;
  83. };
  84. };
  85. &dmsc {
  86. mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
  87. mbox-names = "tx", "rx", "notify";
  88. ti,host-id = <4>;
  89. ti,secure-host;
  90. };
  91. &wkup_pmx0 {
  92. wkup_uart0_pins_default: wkup_uart0_pins_default {
  93. u-boot,dm-spl;
  94. pinctrl-single,pins = <
  95. J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
  96. J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
  97. >;
  98. };
  99. mcu_uart0_pins_default: mcu_uart0_pins_default {
  100. u-boot,dm-spl;
  101. pinctrl-single,pins = <
  102. J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
  103. J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
  104. J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
  105. J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
  106. >;
  107. };
  108. wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  109. pinctrl-single,pins = <
  110. J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
  111. J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
  112. >;
  113. };
  114. mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  115. pinctrl-single,pins = <
  116. J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
  117. J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
  118. J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
  119. J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
  120. J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
  121. J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
  122. J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
  123. J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
  124. J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
  125. J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
  126. J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
  127. >;
  128. };
  129. mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
  130. u-boot,dm-spl;
  131. pinctrl-single,pins = <
  132. J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
  133. J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
  134. J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
  135. J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
  136. J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
  137. J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
  138. J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
  139. J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
  140. >;
  141. };
  142. };
  143. &main_pmx0 {
  144. main_uart0_pins_default: main_uart0_pins_default {
  145. u-boot,dm-spl;
  146. pinctrl-single,pins = <
  147. J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
  148. J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
  149. J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
  150. J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
  151. >;
  152. };
  153. main_usbss0_pins_default: main_usbss0_pins_default {
  154. pinctrl-single,pins = <
  155. J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
  156. J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
  157. >;
  158. };
  159. main_mmc1_pins_default: main_mmc1_pins_default {
  160. pinctrl-single,pins = <
  161. J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
  162. J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
  163. J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
  164. J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
  165. J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
  166. J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
  167. J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
  168. J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
  169. J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
  170. >;
  171. };
  172. main_i2c0_pins_default: main-i2c0-pins-default {
  173. pinctrl-single,pins = <
  174. J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
  175. J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
  176. >;
  177. };
  178. };
  179. &wkup_uart0 {
  180. u-boot,dm-spl;
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&wkup_uart0_pins_default>;
  183. status = "okay";
  184. };
  185. &mcu_uart0 {
  186. /delete-property/ power-domains;
  187. /delete-property/ clocks;
  188. /delete-property/ clock-names;
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&mcu_uart0_pins_default>;
  191. status = "okay";
  192. clock-frequency = <48000000>;
  193. };
  194. &main_uart0 {
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&main_uart0_pins_default>;
  197. status = "okay";
  198. power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  199. };
  200. &main_sdhci0 {
  201. /delete-property/ power-domains;
  202. /delete-property/ assigned-clocks;
  203. /delete-property/ assigned-clock-parents;
  204. clock-names = "clk_xin";
  205. clocks = <&clk_200mhz>;
  206. ti,driver-strength-ohm = <50>;
  207. non-removable;
  208. bus-width = <8>;
  209. };
  210. &main_sdhci1 {
  211. /delete-property/ power-domains;
  212. /delete-property/ assigned-clocks;
  213. /delete-property/ assigned-clock-parents;
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&main_mmc1_pins_default>;
  216. clock-names = "clk_xin";
  217. clocks = <&clk_200mhz>;
  218. ti,driver-strength-ohm = <50>;
  219. };
  220. &wkup_i2c0 {
  221. u-boot,dm-spl;
  222. tps659413a: tps659413a@48 {
  223. reg = <0x48>;
  224. compatible = "ti,tps659413";
  225. u-boot,dm-spl;
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&wkup_i2c0_pins_default>;
  228. clock-frequency = <400000>;
  229. regulators: regulators {
  230. u-boot,dm-spl;
  231. buck12_reg: buck12 {
  232. /*VDD_MPU*/
  233. regulator-name = "buck12";
  234. regulator-min-microvolt = <800000>;
  235. regulator-max-microvolt = <1250000>;
  236. regulator-always-on;
  237. regulator-boot-on;
  238. u-boot,dm-spl;
  239. };
  240. };
  241. };
  242. };
  243. &wkup_vtm0 {
  244. vdd-supply-2 = <&buck12_reg>;
  245. u-boot,dm-spl;
  246. };
  247. &usbss0 {
  248. /delete-property/ power-domains;
  249. /delete-property/ assigned-clocks;
  250. /delete-property/ assigned-clock-parents;
  251. clocks = <&clk_19_2mhz>;
  252. clock-names = "usb2_refclk";
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&main_usbss0_pins_default>;
  255. ti,vbus-divider;
  256. };
  257. &main_i2c0 {
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&main_i2c0_pins_default>;
  260. clock-frequency = <400000>;
  261. exp1: gpio@20 {
  262. compatible = "ti,tca6416";
  263. reg = <0x20>;
  264. gpio-controller;
  265. #gpio-cells = <2>;
  266. };
  267. exp2: gpio@22 {
  268. compatible = "ti,tca6424";
  269. reg = <0x22>;
  270. gpio-controller;
  271. #gpio-cells = <2>;
  272. };
  273. };
  274. &ospi0 {
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
  277. reg = <0x0 0x47040000 0x0 0x100>,
  278. <0x0 0x50000000 0x0 0x8000000>;
  279. flash@0{
  280. compatible = "jedec,spi-nor";
  281. reg = <0x0>;
  282. spi-tx-bus-width = <1>;
  283. spi-rx-bus-width = <8>;
  284. spi-max-frequency = <50000000>;
  285. cdns,tshsl-ns = <60>;
  286. cdns,tsd2d-ns = <60>;
  287. cdns,tchsh-ns = <60>;
  288. cdns,tslch-ns = <60>;
  289. cdns,read-delay = <0>;
  290. #address-cells = <1>;
  291. #size-cells = <1>;
  292. };
  293. };
  294. &ospi1 {
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
  297. u-boot,dm-spl;
  298. reg = <0x0 0x47050000 0x0 0x100>,
  299. <0x0 0x58000000 0x0 0x8000000>;
  300. flash@0{
  301. compatible = "jedec,spi-nor";
  302. reg = <0x0>;
  303. spi-tx-bus-width = <1>;
  304. spi-rx-bus-width = <4>;
  305. spi-max-frequency = <40000000>;
  306. cdns,tshsl-ns = <60>;
  307. cdns,tsd2d-ns = <60>;
  308. cdns,tchsh-ns = <60>;
  309. cdns,tslch-ns = <60>;
  310. cdns,read-delay = <2>;
  311. #address-cells = <1>;
  312. #size-cells = <1>;
  313. u-boot,dm-spl;
  314. };
  315. };
  316. &mcu_ringacc {
  317. ti,sci = <&dm_tifs>;
  318. };
  319. &mcu_udmap {
  320. ti,sci = <&dm_tifs>;
  321. };