k3-j7200-main.dtsi 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J7200 SoC Family Main Domain peripherals
  4. *
  5. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. / {
  8. serdes_refclk: serdes-refclk {
  9. #clock-cells = <0>;
  10. compatible = "fixed-clock";
  11. };
  12. };
  13. &cbass_main {
  14. msmc_ram: sram@70000000 {
  15. compatible = "mmio-sram";
  16. reg = <0x00 0x70000000 0x00 0x100000>;
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. ranges = <0x00 0x00 0x70000000 0x100000>;
  20. atf-sram@0 {
  21. reg = <0x00 0x20000>;
  22. };
  23. };
  24. scm_conf: scm-conf@100000 {
  25. compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  26. reg = <0x00 0x00100000 0x00 0x1c000>;
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. ranges = <0x00 0x00 0x00100000 0x1c000>;
  30. serdes_ln_ctrl: serdes-ln-ctrl@4080 {
  31. compatible = "mmio-mux";
  32. #mux-control-cells = <1>;
  33. mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  34. <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
  35. };
  36. usb_serdes_mux: mux-controller@4000 {
  37. compatible = "mmio-mux";
  38. #mux-control-cells = <1>;
  39. mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  40. };
  41. };
  42. gic500: interrupt-controller@1800000 {
  43. compatible = "arm,gic-v3";
  44. #address-cells = <2>;
  45. #size-cells = <2>;
  46. ranges;
  47. #interrupt-cells = <3>;
  48. interrupt-controller;
  49. reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
  50. <0x00 0x01900000 0x00 0x100000>; /* GICR */
  51. /* vcpumntirq: virtual CPU interface maintenance interrupt */
  52. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  53. gic_its: msi-controller@1820000 {
  54. compatible = "arm,gic-v3-its";
  55. reg = <0x00 0x01820000 0x00 0x10000>;
  56. socionext,synquacer-pre-its = <0x1000000 0x400000>;
  57. msi-controller;
  58. #msi-cells = <1>;
  59. };
  60. };
  61. main_gpio_intr: interrupt-controller0 {
  62. compatible = "ti,sci-intr";
  63. ti,intr-trigger-type = <1>;
  64. interrupt-controller;
  65. interrupt-parent = <&gic500>;
  66. #interrupt-cells = <1>;
  67. ti,sci = <&dmsc>;
  68. ti,sci-dev-id = <131>;
  69. ti,interrupt-ranges = <8 392 56>;
  70. };
  71. main_navss: bus@30000000 {
  72. compatible = "simple-mfd";
  73. #address-cells = <2>;
  74. #size-cells = <2>;
  75. ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  76. ti,sci-dev-id = <199>;
  77. main_navss_intr: interrupt-controller1 {
  78. compatible = "ti,sci-intr";
  79. ti,intr-trigger-type = <4>;
  80. interrupt-controller;
  81. interrupt-parent = <&gic500>;
  82. #interrupt-cells = <1>;
  83. ti,sci = <&dmsc>;
  84. ti,sci-dev-id = <213>;
  85. ti,interrupt-ranges = <0 64 64>,
  86. <64 448 64>,
  87. <128 672 64>;
  88. };
  89. main_udmass_inta: msi-controller@33d00000 {
  90. compatible = "ti,sci-inta";
  91. reg = <0x00 0x33d00000 0x00 0x100000>;
  92. interrupt-controller;
  93. #interrupt-cells = <0>;
  94. interrupt-parent = <&main_navss_intr>;
  95. msi-controller;
  96. ti,sci = <&dmsc>;
  97. ti,sci-dev-id = <209>;
  98. ti,interrupt-ranges = <0 0 256>;
  99. };
  100. secure_proxy_main: mailbox@32c00000 {
  101. compatible = "ti,am654-secure-proxy";
  102. #mbox-cells = <1>;
  103. reg-names = "target_data", "rt", "scfg";
  104. reg = <0x00 0x32c00000 0x00 0x100000>,
  105. <0x00 0x32400000 0x00 0x100000>,
  106. <0x00 0x32800000 0x00 0x100000>;
  107. interrupt-names = "rx_011";
  108. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  109. };
  110. hwspinlock: spinlock@30e00000 {
  111. compatible = "ti,am654-hwspinlock";
  112. reg = <0x00 0x30e00000 0x00 0x1000>;
  113. #hwlock-cells = <1>;
  114. };
  115. mailbox0_cluster0: mailbox@31f80000 {
  116. compatible = "ti,am654-mailbox";
  117. reg = <0x00 0x31f80000 0x00 0x200>;
  118. #mbox-cells = <1>;
  119. ti,mbox-num-users = <4>;
  120. ti,mbox-num-fifos = <16>;
  121. interrupt-parent = <&main_navss_intr>;
  122. };
  123. mailbox0_cluster1: mailbox@31f81000 {
  124. compatible = "ti,am654-mailbox";
  125. reg = <0x00 0x31f81000 0x00 0x200>;
  126. #mbox-cells = <1>;
  127. ti,mbox-num-users = <4>;
  128. ti,mbox-num-fifos = <16>;
  129. interrupt-parent = <&main_navss_intr>;
  130. };
  131. mailbox0_cluster2: mailbox@31f82000 {
  132. compatible = "ti,am654-mailbox";
  133. reg = <0x00 0x31f82000 0x00 0x200>;
  134. #mbox-cells = <1>;
  135. ti,mbox-num-users = <4>;
  136. ti,mbox-num-fifos = <16>;
  137. interrupt-parent = <&main_navss_intr>;
  138. };
  139. mailbox0_cluster3: mailbox@31f83000 {
  140. compatible = "ti,am654-mailbox";
  141. reg = <0x00 0x31f83000 0x00 0x200>;
  142. #mbox-cells = <1>;
  143. ti,mbox-num-users = <4>;
  144. ti,mbox-num-fifos = <16>;
  145. interrupt-parent = <&main_navss_intr>;
  146. };
  147. mailbox0_cluster4: mailbox@31f84000 {
  148. compatible = "ti,am654-mailbox";
  149. reg = <0x00 0x31f84000 0x00 0x200>;
  150. #mbox-cells = <1>;
  151. ti,mbox-num-users = <4>;
  152. ti,mbox-num-fifos = <16>;
  153. interrupt-parent = <&main_navss_intr>;
  154. };
  155. mailbox0_cluster5: mailbox@31f85000 {
  156. compatible = "ti,am654-mailbox";
  157. reg = <0x00 0x31f85000 0x00 0x200>;
  158. #mbox-cells = <1>;
  159. ti,mbox-num-users = <4>;
  160. ti,mbox-num-fifos = <16>;
  161. interrupt-parent = <&main_navss_intr>;
  162. };
  163. mailbox0_cluster6: mailbox@31f86000 {
  164. compatible = "ti,am654-mailbox";
  165. reg = <0x00 0x31f86000 0x00 0x200>;
  166. #mbox-cells = <1>;
  167. ti,mbox-num-users = <4>;
  168. ti,mbox-num-fifos = <16>;
  169. interrupt-parent = <&main_navss_intr>;
  170. };
  171. mailbox0_cluster7: mailbox@31f87000 {
  172. compatible = "ti,am654-mailbox";
  173. reg = <0x00 0x31f87000 0x00 0x200>;
  174. #mbox-cells = <1>;
  175. ti,mbox-num-users = <4>;
  176. ti,mbox-num-fifos = <16>;
  177. interrupt-parent = <&main_navss_intr>;
  178. };
  179. mailbox0_cluster8: mailbox@31f88000 {
  180. compatible = "ti,am654-mailbox";
  181. reg = <0x00 0x31f88000 0x00 0x200>;
  182. #mbox-cells = <1>;
  183. ti,mbox-num-users = <4>;
  184. ti,mbox-num-fifos = <16>;
  185. interrupt-parent = <&main_navss_intr>;
  186. };
  187. mailbox0_cluster9: mailbox@31f89000 {
  188. compatible = "ti,am654-mailbox";
  189. reg = <0x00 0x31f89000 0x00 0x200>;
  190. #mbox-cells = <1>;
  191. ti,mbox-num-users = <4>;
  192. ti,mbox-num-fifos = <16>;
  193. interrupt-parent = <&main_navss_intr>;
  194. };
  195. mailbox0_cluster10: mailbox@31f8a000 {
  196. compatible = "ti,am654-mailbox";
  197. reg = <0x00 0x31f8a000 0x00 0x200>;
  198. #mbox-cells = <1>;
  199. ti,mbox-num-users = <4>;
  200. ti,mbox-num-fifos = <16>;
  201. interrupt-parent = <&main_navss_intr>;
  202. };
  203. mailbox0_cluster11: mailbox@31f8b000 {
  204. compatible = "ti,am654-mailbox";
  205. reg = <0x00 0x31f8b000 0x00 0x200>;
  206. #mbox-cells = <1>;
  207. ti,mbox-num-users = <4>;
  208. ti,mbox-num-fifos = <16>;
  209. interrupt-parent = <&main_navss_intr>;
  210. };
  211. main_ringacc: ringacc@3c000000 {
  212. compatible = "ti,am654-navss-ringacc";
  213. reg = <0x00 0x3c000000 0x00 0x400000>,
  214. <0x00 0x38000000 0x00 0x400000>,
  215. <0x00 0x31120000 0x00 0x100>,
  216. <0x00 0x33000000 0x00 0x40000>;
  217. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  218. ti,num-rings = <1024>;
  219. ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
  220. ti,sci = <&dmsc>;
  221. ti,sci-dev-id = <211>;
  222. msi-parent = <&main_udmass_inta>;
  223. };
  224. main_udmap: dma-controller@31150000 {
  225. compatible = "ti,j721e-navss-main-udmap";
  226. reg = <0x00 0x31150000 0x00 0x100>,
  227. <0x00 0x34000000 0x00 0x100000>,
  228. <0x00 0x35000000 0x00 0x100000>;
  229. reg-names = "gcfg", "rchanrt", "tchanrt";
  230. msi-parent = <&main_udmass_inta>;
  231. #dma-cells = <1>;
  232. ti,sci = <&dmsc>;
  233. ti,sci-dev-id = <212>;
  234. ti,ringacc = <&main_ringacc>;
  235. ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
  236. <0x0f>, /* TX_HCHAN */
  237. <0x10>; /* TX_UHCHAN */
  238. ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
  239. <0x0b>, /* RX_HCHAN */
  240. <0x0c>; /* RX_UHCHAN */
  241. ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
  242. };
  243. cpts@310d0000 {
  244. compatible = "ti,j721e-cpts";
  245. reg = <0x00 0x310d0000 0x00 0x400>;
  246. reg-names = "cpts";
  247. clocks = <&k3_clks 201 1>;
  248. clock-names = "cpts";
  249. interrupts-extended = <&main_navss_intr 391>;
  250. interrupt-names = "cpts";
  251. ti,cpts-periodic-outputs = <6>;
  252. ti,cpts-ext-ts-inputs = <8>;
  253. };
  254. };
  255. main_pmx0: pinctrl@11c000 {
  256. compatible = "pinctrl-single";
  257. /* Proxy 0 addressing */
  258. reg = <0x00 0x11c000 0x00 0x2b4>;
  259. #pinctrl-cells = <1>;
  260. pinctrl-single,register-width = <32>;
  261. pinctrl-single,function-mask = <0xffffffff>;
  262. };
  263. main_uart0: serial@2800000 {
  264. compatible = "ti,j721e-uart", "ti,am654-uart";
  265. reg = <0x00 0x02800000 0x00 0x100>;
  266. reg-shift = <2>;
  267. reg-io-width = <4>;
  268. interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  269. clock-frequency = <48000000>;
  270. current-speed = <115200>;
  271. power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  272. clocks = <&k3_clks 146 2>;
  273. clock-names = "fclk";
  274. };
  275. main_uart1: serial@2810000 {
  276. compatible = "ti,j721e-uart", "ti,am654-uart";
  277. reg = <0x00 0x02810000 0x00 0x100>;
  278. reg-shift = <2>;
  279. reg-io-width = <4>;
  280. interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  281. clock-frequency = <48000000>;
  282. current-speed = <115200>;
  283. power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  284. clocks = <&k3_clks 278 2>;
  285. clock-names = "fclk";
  286. };
  287. main_uart2: serial@2820000 {
  288. compatible = "ti,j721e-uart", "ti,am654-uart";
  289. reg = <0x00 0x02820000 0x00 0x100>;
  290. reg-shift = <2>;
  291. reg-io-width = <4>;
  292. interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  293. clock-frequency = <48000000>;
  294. current-speed = <115200>;
  295. power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
  296. clocks = <&k3_clks 279 2>;
  297. clock-names = "fclk";
  298. };
  299. main_uart3: serial@2830000 {
  300. compatible = "ti,j721e-uart", "ti,am654-uart";
  301. reg = <0x00 0x02830000 0x00 0x100>;
  302. reg-shift = <2>;
  303. reg-io-width = <4>;
  304. interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
  305. clock-frequency = <48000000>;
  306. current-speed = <115200>;
  307. power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
  308. clocks = <&k3_clks 280 2>;
  309. clock-names = "fclk";
  310. };
  311. main_uart4: serial@2840000 {
  312. compatible = "ti,j721e-uart", "ti,am654-uart";
  313. reg = <0x00 0x02840000 0x00 0x100>;
  314. reg-shift = <2>;
  315. reg-io-width = <4>;
  316. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  317. clock-frequency = <48000000>;
  318. current-speed = <115200>;
  319. power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
  320. clocks = <&k3_clks 281 2>;
  321. clock-names = "fclk";
  322. };
  323. main_uart5: serial@2850000 {
  324. compatible = "ti,j721e-uart", "ti,am654-uart";
  325. reg = <0x00 0x02850000 0x00 0x100>;
  326. reg-shift = <2>;
  327. reg-io-width = <4>;
  328. interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  329. clock-frequency = <48000000>;
  330. current-speed = <115200>;
  331. power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
  332. clocks = <&k3_clks 282 2>;
  333. clock-names = "fclk";
  334. };
  335. main_uart6: serial@2860000 {
  336. compatible = "ti,j721e-uart", "ti,am654-uart";
  337. reg = <0x00 0x02860000 0x00 0x100>;
  338. reg-shift = <2>;
  339. reg-io-width = <4>;
  340. interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
  341. clock-frequency = <48000000>;
  342. current-speed = <115200>;
  343. power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
  344. clocks = <&k3_clks 283 2>;
  345. clock-names = "fclk";
  346. };
  347. main_uart7: serial@2870000 {
  348. compatible = "ti,j721e-uart", "ti,am654-uart";
  349. reg = <0x00 0x02870000 0x00 0x100>;
  350. reg-shift = <2>;
  351. reg-io-width = <4>;
  352. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
  353. clock-frequency = <48000000>;
  354. current-speed = <115200>;
  355. power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
  356. clocks = <&k3_clks 284 2>;
  357. clock-names = "fclk";
  358. };
  359. main_uart8: serial@2880000 {
  360. compatible = "ti,j721e-uart", "ti,am654-uart";
  361. reg = <0x00 0x02880000 0x00 0x100>;
  362. reg-shift = <2>;
  363. reg-io-width = <4>;
  364. interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
  365. clock-frequency = <48000000>;
  366. current-speed = <115200>;
  367. power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
  368. clocks = <&k3_clks 285 2>;
  369. clock-names = "fclk";
  370. };
  371. main_uart9: serial@2890000 {
  372. compatible = "ti,j721e-uart", "ti,am654-uart";
  373. reg = <0x00 0x02890000 0x00 0x100>;
  374. reg-shift = <2>;
  375. reg-io-width = <4>;
  376. interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
  377. clock-frequency = <48000000>;
  378. current-speed = <115200>;
  379. power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
  380. clocks = <&k3_clks 286 2>;
  381. clock-names = "fclk";
  382. };
  383. main_sdhci0: sdhci@4f80000 {
  384. compatible = "ti,j721e-sdhci-8bit";
  385. reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
  386. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  387. power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
  388. clock-names = "clk_xin", "clk_ahb";
  389. clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
  390. ti,otap-del-sel-legacy = <0x0>;
  391. ti,otap-del-sel-mmc-hs = <0x0>;
  392. ti,otap-del-sel-ddr52 = <0x6>;
  393. ti,otap-del-sel-hs200 = <0x8>;
  394. ti,otap-del-sel-hs400 = <0x5>;
  395. ti,itap-del-sel-legacy = <0x10>;
  396. ti,itap-del-sel-mmc-hs = <0xa>;
  397. ti,strobe-sel = <0x77>;
  398. ti,clkbuf-sel = <0x7>;
  399. ti,trm-icp = <0x8>;
  400. bus-width = <8>;
  401. mmc-hs400-1_8v;
  402. mmc-hs200-1_8v;
  403. mmc-ddr-1_8v;
  404. dma-coherent;
  405. };
  406. main_sdhci1: sdhci@4fb0000 {
  407. compatible = "ti,j721e-sdhci-4bit";
  408. reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
  409. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  410. power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
  411. clock-names = "clk_xin", "clk_ahb";
  412. clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
  413. ti,otap-del-sel-legacy = <0x0>;
  414. ti,otap-del-sel-sd-hs = <0x0>;
  415. ti,otap-del-sel-sdr12 = <0xf>;
  416. ti,otap-del-sel-sdr25 = <0xf>;
  417. ti,otap-del-sel-sdr50 = <0xc>;
  418. ti,otap-del-sel-sdr104 = <0x5>;
  419. ti,otap-del-sel-ddr50 = <0xc>;
  420. ti,itap-del-sel-legacy = <0x0>;
  421. ti,itap-del-sel-sd-hs = <0x0>;
  422. ti,itap-del-sel-sdr12 = <0x0>;
  423. ti,itap-del-sel-sdr25 = <0x0>;
  424. ti,clkbuf-sel = <0x7>;
  425. ti,trm-icp = <0x8>;
  426. dma-coherent;
  427. };
  428. main_i2c0: i2c@2000000 {
  429. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  430. reg = <0x00 0x2000000 0x00 0x100>;
  431. interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. clock-names = "fck";
  435. clocks = <&k3_clks 187 1>;
  436. power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
  437. };
  438. main_i2c1: i2c@2010000 {
  439. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  440. reg = <0x00 0x2010000 0x00 0x100>;
  441. interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
  442. #address-cells = <1>;
  443. #size-cells = <0>;
  444. clock-names = "fck";
  445. clocks = <&k3_clks 188 1>;
  446. power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
  447. };
  448. main_i2c2: i2c@2020000 {
  449. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  450. reg = <0x00 0x2020000 0x00 0x100>;
  451. interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
  452. #address-cells = <1>;
  453. #size-cells = <0>;
  454. clock-names = "fck";
  455. clocks = <&k3_clks 189 1>;
  456. power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
  457. };
  458. main_i2c3: i2c@2030000 {
  459. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  460. reg = <0x00 0x2030000 0x00 0x100>;
  461. interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
  462. #address-cells = <1>;
  463. #size-cells = <0>;
  464. clock-names = "fck";
  465. clocks = <&k3_clks 190 1>;
  466. power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
  467. };
  468. main_i2c4: i2c@2040000 {
  469. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  470. reg = <0x00 0x2040000 0x00 0x100>;
  471. interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
  472. #address-cells = <1>;
  473. #size-cells = <0>;
  474. clock-names = "fck";
  475. clocks = <&k3_clks 191 1>;
  476. power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
  477. };
  478. main_i2c5: i2c@2050000 {
  479. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  480. reg = <0x00 0x2050000 0x00 0x100>;
  481. interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  482. #address-cells = <1>;
  483. #size-cells = <0>;
  484. clock-names = "fck";
  485. clocks = <&k3_clks 192 1>;
  486. power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
  487. };
  488. main_i2c6: i2c@2060000 {
  489. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  490. reg = <0x00 0x2060000 0x00 0x100>;
  491. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  492. #address-cells = <1>;
  493. #size-cells = <0>;
  494. clock-names = "fck";
  495. clocks = <&k3_clks 193 1>;
  496. power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
  497. };
  498. main_gpio0: gpio@600000 {
  499. compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  500. reg = <0x0 0x00600000 0x0 0x100>;
  501. gpio-controller;
  502. #gpio-cells = <2>;
  503. interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
  504. <105 1 IRQ_TYPE_EDGE_RISING>,
  505. <105 2 IRQ_TYPE_EDGE_RISING>,
  506. <105 3 IRQ_TYPE_EDGE_RISING>,
  507. <105 4 IRQ_TYPE_EDGE_RISING>,
  508. <105 5 IRQ_TYPE_EDGE_RISING>,
  509. <105 6 IRQ_TYPE_EDGE_RISING>,
  510. <105 7 IRQ_TYPE_EDGE_RISING>;
  511. interrupt-controller;
  512. #interrupt-cells = <2>;
  513. ti,ngpio = <69>;
  514. ti,davinci-gpio-unbanked = <0>;
  515. power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
  516. clocks = <&k3_clks 105 0>;
  517. clock-names = "gpio";
  518. };
  519. serdes_wiz0: wiz@5060000 {
  520. compatible = "ti,j721e-wiz-10g";
  521. #address-cells = <1>;
  522. #size-cells = <1>;
  523. power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
  524. clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
  525. clock-names = "fck", "core_ref_clk", "ext_ref_clk";
  526. num-lanes = <4>;
  527. #reset-cells = <1>;
  528. ranges = <0x5060000 0x0 0x5060000 0x10000>;
  529. assigned-clocks = <&k3_clks 292 85>;
  530. assigned-clock-parents = <&k3_clks 292 89>;
  531. wiz0_pll0_refclk: pll0-refclk {
  532. clocks = <&k3_clks 292 85>, <&serdes_refclk>;
  533. clock-output-names = "wiz0_pll0_refclk";
  534. #clock-cells = <0>;
  535. assigned-clocks = <&wiz0_pll0_refclk>;
  536. assigned-clock-parents = <&k3_clks 292 85>;
  537. };
  538. wiz0_pll1_refclk: pll1-refclk {
  539. clocks = <&k3_clks 292 85>, <&serdes_refclk>;
  540. clock-output-names = "wiz0_pll1_refclk";
  541. #clock-cells = <0>;
  542. assigned-clocks = <&wiz0_pll1_refclk>;
  543. assigned-clock-parents = <&k3_clks 292 85>;
  544. };
  545. wiz0_refclk_dig: refclk-dig {
  546. clocks = <&k3_clks 292 85>, <&serdes_refclk>;
  547. clock-output-names = "wiz0_refclk_dig";
  548. #clock-cells = <0>;
  549. assigned-clocks = <&wiz0_refclk_dig>;
  550. assigned-clock-parents = <&k3_clks 292 85>;
  551. };
  552. wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
  553. clocks = <&wiz0_refclk_dig>;
  554. #clock-cells = <0>;
  555. };
  556. serdes0: serdes@5060000 {
  557. compatible = "ti,j721e-serdes-10g";
  558. reg = <0x05060000 0x00010000>;
  559. reg-names = "torrent_phy";
  560. resets = <&serdes_wiz0 0>;
  561. reset-names = "torrent_reset";
  562. clocks = <&wiz0_pll0_refclk>;
  563. clock-names = "refclk";
  564. #address-cells = <1>;
  565. #size-cells = <0>;
  566. };
  567. };
  568. usbss0: cdns-usb@4104000 {
  569. compatible = "ti,j721e-usb";
  570. reg = <0x00 0x4104000 0x00 0x100>;
  571. dma-coherent;
  572. power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
  573. clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
  574. clock-names = "ref", "lpm";
  575. assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
  576. assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
  577. #address-cells = <2>;
  578. #size-cells = <2>;
  579. ranges;
  580. usb0: usb@6000000 {
  581. compatible = "cdns,usb3";
  582. reg = <0x00 0x6000000 0x00 0x10000>,
  583. <0x00 0x6010000 0x00 0x10000>,
  584. <0x00 0x6020000 0x00 0x10000>;
  585. reg-names = "otg", "xhci", "dev";
  586. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
  587. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
  588. <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
  589. interrupt-names = "host",
  590. "peripheral",
  591. "otg";
  592. maximum-speed = "super-speed";
  593. dr_mode = "otg";
  594. };
  595. };
  596. main_r5fss0: r5fss@5c00000 {
  597. compatible = "ti,j7200-r5fss";
  598. ti,cluster-mode = <0>;
  599. #address-cells = <1>;
  600. #size-cells = <1>;
  601. ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
  602. <0x5d00000 0x00 0x5d00000 0x20000>;
  603. power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
  604. main_r5fss0_core0: r5f@5c00000 {
  605. compatible = "ti,j7200-r5f";
  606. reg = <0x5c00000 0x00010000>,
  607. <0x5c10000 0x00010000>;
  608. reg-names = "atcm", "btcm";
  609. ti,sci = <&dmsc>;
  610. ti,sci-dev-id = <245>;
  611. ti,sci-proc-ids = <0x06 0xFF>;
  612. resets = <&k3_reset 245 1>;
  613. firmware-name = "j7200-main-r5f0_0-fw";
  614. ti,atcm-enable = <1>;
  615. ti,btcm-enable = <1>;
  616. ti,loczrama = <1>;
  617. };
  618. main_r5fss0_core1: r5f@5d00000 {
  619. compatible = "ti,j7200-r5f";
  620. reg = <0x5d00000 0x00008000>,
  621. <0x5d10000 0x00008000>;
  622. reg-names = "atcm", "btcm";
  623. ti,sci = <&dmsc>;
  624. ti,sci-dev-id = <246>;
  625. ti,sci-proc-ids = <0x07 0xFF>;
  626. resets = <&k3_reset 246 1>;
  627. firmware-name = "j7200-main-r5f0_1-fw";
  628. ti,atcm-enable = <1>;
  629. ti,btcm-enable = <1>;
  630. ti,loczrama = <1>;
  631. };
  632. };
  633. };