k3-j7200-common-proc-board.dts 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "k3-j7200-som-p0.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/net/ti-dp83867.h>
  9. #include <dt-bindings/mux/ti-serdes.h>
  10. #include <dt-bindings/phy/phy.h>
  11. / {
  12. chosen {
  13. stdout-path = "serial2:115200n8";
  14. bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  15. };
  16. aliases {
  17. remoteproc0 = &mcu_r5fss0_core0;
  18. remoteproc1 = &mcu_r5fss0_core1;
  19. remoteproc2 = &main_r5fss0_core0;
  20. remoteproc3 = &main_r5fss0_core1;
  21. };
  22. vdd_mmc1: fixedregulator-sd {
  23. compatible = "regulator-fixed";
  24. regulator-name = "vdd_mmc1";
  25. regulator-min-microvolt = <3300000>;
  26. regulator-max-microvolt = <3300000>;
  27. regulator-boot-on;
  28. enable-active-high;
  29. gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
  30. };
  31. vdd_sd_dv: gpio-regulator-vdd-sd-dv {
  32. compatible = "regulator-gpio";
  33. regulator-name = "vdd_sd_dv";
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&vdd_sd_dv_pins_default>;
  36. regulator-min-microvolt = <1800000>;
  37. regulator-max-microvolt = <3300000>;
  38. regulator-boot-on;
  39. gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
  40. states = <1800000 0x0
  41. 3300000 0x1>;
  42. };
  43. };
  44. &wkup_pmx0 {
  45. wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  46. pinctrl-single,pins = <
  47. J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
  48. J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
  49. >;
  50. };
  51. wkup_gpio_pins_default: wkup-gpio-pins-default {
  52. pinctrl-single,pins = <
  53. J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
  54. >;
  55. };
  56. mcu_cpsw_pins_default: mcu-cpsw-pins-default {
  57. pinctrl-single,pins = <
  58. J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
  59. J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
  60. J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
  61. J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
  62. J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
  63. J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
  64. J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
  65. J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
  66. J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
  67. J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
  68. J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
  69. J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
  70. >;
  71. };
  72. mcu_mdio_pins_default: mcu-mdio1-pins-default {
  73. pinctrl-single,pins = <
  74. J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  75. J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  76. >;
  77. };
  78. };
  79. &main_pmx0 {
  80. main_i2c0_pins_default: main-i2c0-pins-default {
  81. pinctrl-single,pins = <
  82. J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
  83. J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
  84. >;
  85. };
  86. main_i2c1_pins_default: main-i2c1-pins-default {
  87. pinctrl-single,pins = <
  88. J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
  89. J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
  90. >;
  91. };
  92. main_mmc1_pins_default: main-mmc1-pins-default {
  93. pinctrl-single,pins = <
  94. J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
  95. J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
  96. J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
  97. J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
  98. J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
  99. J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
  100. J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
  101. J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
  102. >;
  103. };
  104. vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
  105. pinctrl-single,pins = <
  106. J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
  107. >;
  108. };
  109. main_usbss0_pins_default: main-usbss0-pins-default {
  110. pinctrl-single,pins = <
  111. J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
  112. >;
  113. };
  114. };
  115. &wkup_uart0 {
  116. /* Wakeup UART is used by System firmware */
  117. status = "reserved";
  118. };
  119. &main_uart0 {
  120. /* Shared with ATF on this platform */
  121. power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  122. };
  123. &main_uart2 {
  124. /* MAIN UART 2 is used by R5F firmware */
  125. status = "reserved";
  126. };
  127. &main_uart3 {
  128. /* UART not brought out */
  129. status = "disabled";
  130. };
  131. &main_uart4 {
  132. /* UART not brought out */
  133. status = "disabled";
  134. };
  135. &main_uart5 {
  136. /* UART not brought out */
  137. status = "disabled";
  138. };
  139. &main_uart6 {
  140. /* UART not brought out */
  141. status = "disabled";
  142. };
  143. &main_uart7 {
  144. /* UART not brought out */
  145. status = "disabled";
  146. };
  147. &main_uart8 {
  148. /* UART not brought out */
  149. status = "disabled";
  150. };
  151. &main_uart9 {
  152. /* UART not brought out */
  153. status = "disabled";
  154. };
  155. &mcu_cpsw {
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  158. };
  159. &davinci_mdio {
  160. phy0: ethernet-phy@0 {
  161. reg = <0>;
  162. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  163. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  164. };
  165. };
  166. &cpsw_port1 {
  167. phy-mode = "rgmii-rxid";
  168. phy-handle = <&phy0>;
  169. };
  170. &main_i2c0 {
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&main_i2c0_pins_default>;
  173. clock-frequency = <400000>;
  174. exp1: gpio@20 {
  175. compatible = "ti,tca6416";
  176. reg = <0x20>;
  177. gpio-controller;
  178. #gpio-cells = <2>;
  179. };
  180. exp2: gpio@22 {
  181. compatible = "ti,tca6424";
  182. reg = <0x22>;
  183. gpio-controller;
  184. #gpio-cells = <2>;
  185. };
  186. };
  187. /*
  188. * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
  189. * swapped on the CPB.
  190. *
  191. * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
  192. * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
  193. */
  194. &main_i2c1 {
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&main_i2c1_pins_default>;
  197. clock-frequency = <400000>;
  198. exp3: gpio@20 {
  199. compatible = "ti,tca6408";
  200. reg = <0x20>;
  201. gpio-controller;
  202. #gpio-cells = <2>;
  203. gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
  204. "UB926_LOCK", "UB926_PWR_SW_CNTRL",
  205. "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
  206. };
  207. };
  208. &main_sdhci0 {
  209. /* eMMC */
  210. non-removable;
  211. ti,driver-strength-ohm = <50>;
  212. disable-wp;
  213. };
  214. &main_sdhci1 {
  215. /* SD card */
  216. pinctrl-0 = <&main_mmc1_pins_default>;
  217. pinctrl-names = "default";
  218. vmmc-supply = <&vdd_mmc1>;
  219. vqmmc-supply = <&vdd_sd_dv>;
  220. ti,driver-strength-ohm = <50>;
  221. disable-wp;
  222. };
  223. &serdes_ln_ctrl {
  224. idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
  225. <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
  226. };
  227. &usb_serdes_mux {
  228. idle-states = <1>; /* USB0 to SERDES lane 3 */
  229. };
  230. &usbss0 {
  231. pinctrl-names = "default";
  232. pinctrl-0 = <&main_usbss0_pins_default>;
  233. ti,vbus-divider;
  234. ti,usb2-only;
  235. };
  236. &usb0 {
  237. dr_mode = "otg";
  238. maximum-speed = "high-speed";
  239. };
  240. &tscadc0 {
  241. adc {
  242. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  243. };
  244. };
  245. &serdes_refclk {
  246. clock-frequency = <100000000>;
  247. };
  248. &serdes0 {
  249. serdes0_pcie_link: link@0 {
  250. reg = <0>;
  251. cdns,num-lanes = <2>;
  252. #phy-cells = <0>;
  253. cdns,phy-type = <PHY_TYPE_PCIE>;
  254. resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
  255. };
  256. serdes0_qsgmii_link: link@1 {
  257. reg = <2>;
  258. cdns,num-lanes = <1>;
  259. #phy-cells = <0>;
  260. cdns,phy-type = <PHY_TYPE_QSGMII>;
  261. resets = <&serdes_wiz0 3>;
  262. };
  263. };