k3-j7200-common-proc-board-u-boot.dtsi 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. / {
  6. chosen {
  7. stdout-path = "serial2:115200n8";
  8. tick-timer = &timer1;
  9. };
  10. aliases {
  11. ethernet0 = &cpsw_port1;
  12. i2c0 = &wkup_i2c0;
  13. i2c1 = &mcu_i2c0;
  14. i2c2 = &mcu_i2c1;
  15. i2c3 = &main_i2c0;
  16. };
  17. };
  18. &cbass_main {
  19. u-boot,dm-spl;
  20. };
  21. &main_navss {
  22. u-boot,dm-spl;
  23. };
  24. &cbass_mcu_wakeup {
  25. u-boot,dm-spl;
  26. timer1: timer@40400000 {
  27. compatible = "ti,omap5430-timer";
  28. reg = <0x0 0x40400000 0x0 0x80>;
  29. ti,timer-alwon;
  30. clock-frequency = <250000000>;
  31. u-boot,dm-spl;
  32. };
  33. chipid@43000014 {
  34. u-boot,dm-spl;
  35. };
  36. mcu-navss{
  37. u-boot,dm-spl;
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. ringacc@2b800000 {
  41. reg = <0x0 0x2b800000 0x0 0x400000>,
  42. <0x0 0x2b000000 0x0 0x400000>,
  43. <0x0 0x28590000 0x0 0x100>,
  44. <0x0 0x2a500000 0x0 0x40000>,
  45. <0x0 0x28440000 0x0 0x40000>;
  46. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
  47. u-boot,dm-spl;
  48. };
  49. dma-controller@285c0000 {
  50. reg = <0x0 0x285c0000 0x0 0x100>,
  51. <0x0 0x284c0000 0x0 0x4000>,
  52. <0x0 0x2a800000 0x0 0x40000>,
  53. <0x0 0x284a0000 0x0 0x4000>,
  54. <0x0 0x2aa00000 0x0 0x40000>,
  55. <0x0 0x28400000 0x0 0x2000>;
  56. reg-names = "gcfg", "rchan", "rchanrt", "tchan",
  57. "tchanrt", "rflow";
  58. u-boot,dm-spl;
  59. };
  60. };
  61. };
  62. &secure_proxy_main {
  63. u-boot,dm-spl;
  64. };
  65. &dmsc {
  66. u-boot,dm-spl;
  67. k3_sysreset: sysreset-controller {
  68. compatible = "ti,sci-sysreset";
  69. u-boot,dm-spl;
  70. };
  71. };
  72. &k3_pds {
  73. u-boot,dm-spl;
  74. };
  75. &k3_clks {
  76. u-boot,dm-spl;
  77. };
  78. &k3_reset {
  79. u-boot,dm-spl;
  80. };
  81. &wkup_pmx0 {
  82. u-boot,dm-spl;
  83. };
  84. &main_pmx0 {
  85. u-boot,dm-spl;
  86. };
  87. &main_uart0 {
  88. u-boot,dm-spl;
  89. };
  90. &mcu_uart0 {
  91. u-boot,dm-spl;
  92. };
  93. &main_sdhci0 {
  94. u-boot,dm-spl;
  95. };
  96. &main_sdhci1 {
  97. u-boot,dm-spl;
  98. };
  99. &wkup_i2c0_pins_default {
  100. u-boot,dm-spl;
  101. };
  102. &wkup_i2c0 {
  103. u-boot,dm-spl;
  104. };
  105. &main_i2c0 {
  106. u-boot,dm-spl;
  107. };
  108. &main_i2c0_pins_default {
  109. u-boot,dm-spl;
  110. };
  111. &exp2 {
  112. u-boot,dm-spl;
  113. };
  114. &mcu_cpsw {
  115. reg = <0x0 0x46000000 0x0 0x200000>,
  116. <0x0 0x40f00200 0x0 0x8>;
  117. reg-names = "cpsw_nuss", "mac_efuse";
  118. /delete-property/ ranges;
  119. cpsw-phy-sel@40f04040 {
  120. compatible = "ti,am654-cpsw-phy-sel";
  121. reg= <0x0 0x40f04040 0x0 0x4>;
  122. reg-names = "gmii-sel";
  123. };
  124. };
  125. &main_usbss0_pins_default {
  126. u-boot,dm-spl;
  127. };
  128. &usbss0 {
  129. u-boot,dm-spl;
  130. ti,usb2-only;
  131. };
  132. &usb0 {
  133. dr_mode = "peripheral";
  134. u-boot,dm-spl;
  135. };
  136. &wkup_gpio_pins_default {
  137. u-boot,dm-spl;
  138. };
  139. &mcu_fss0_hpb0_pins_default {
  140. u-boot,dm-spl;
  141. };
  142. &fss {
  143. u-boot,dm-spl;
  144. };
  145. &hbmc {
  146. u-boot,dm-spl;
  147. flash@0,0 {
  148. u-boot,dm-spl;
  149. };
  150. };
  151. &hbmc_mux {
  152. u-boot,dm-spl;
  153. };
  154. &serdes_ln_ctrl {
  155. u-boot,mux-autoprobe;
  156. };
  157. &usb_serdes_mux {
  158. u-boot,mux-autoprobe;
  159. };
  160. &serdes0 {
  161. u-boot,dm-spl;
  162. };