cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  4. * (C) Copyright 2002, 2003 Motorola Inc.
  5. * Xianghua Xiao (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <irq_func.h>
  14. #include <vsprintf.h>
  15. #include <watchdog.h>
  16. #include <command.h>
  17. #include <fsl_esdhc.h>
  18. #include <asm/cache.h>
  19. #include <asm/io.h>
  20. #include <asm/mmu.h>
  21. #include <fsl_ifc.h>
  22. #include <asm/fsl_law.h>
  23. #include <asm/fsl_lbc.h>
  24. #include <post.h>
  25. #include <asm/processor.h>
  26. #include <fsl_ddr_sdram.h>
  27. #include <asm/ppc.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. /*
  30. * Default board reset function
  31. */
  32. static void
  33. __board_reset(void)
  34. {
  35. /* Do nothing */
  36. }
  37. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  38. int checkcpu (void)
  39. {
  40. sys_info_t sysinfo;
  41. uint pvr, svr;
  42. uint ver;
  43. uint major, minor;
  44. struct cpu_type *cpu;
  45. char buf1[32], buf2[32];
  46. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  47. ccsr_gur_t __iomem *gur =
  48. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49. #endif
  50. /*
  51. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  52. * mode. Previous platform use ddr ratio to do the same. This
  53. * information is only for display here.
  54. */
  55. #ifdef CONFIG_FSL_CORENET
  56. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  57. u32 ddr_sync = 0; /* only async mode is supported */
  58. #else
  59. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  60. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  61. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  62. #else /* CONFIG_FSL_CORENET */
  63. #ifdef CONFIG_DDR_CLK_FREQ
  64. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  65. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  66. #else
  67. u32 ddr_ratio = 0;
  68. #endif /* CONFIG_DDR_CLK_FREQ */
  69. #endif /* CONFIG_FSL_CORENET */
  70. unsigned int i, core, nr_cores = cpu_numcores();
  71. u32 mask = cpu_mask();
  72. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  73. unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
  74. u32 dsp_mask = cpu_dsp_mask();
  75. #endif
  76. svr = get_svr();
  77. major = SVR_MAJ(svr);
  78. minor = SVR_MIN(svr);
  79. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  80. if (SVR_SOC_VER(svr) == SVR_T4080) {
  81. ccsr_rcpm_t *rcpm =
  82. (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  83. setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  84. FSL_CORENET_DEVDISR2_DTSEC1_9);
  85. setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  86. setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  87. /* It needs SW to disable core4~7 as HW design sake on T4080 */
  88. for (i = 4; i < 8; i++)
  89. cpu_disable(i);
  90. /* request core4~7 into PH20 state, prior to entering PCL10
  91. * state, all cores in cluster should be placed in PH20 state.
  92. */
  93. setbits_be32(&rcpm->pcph20setr, 0xf0);
  94. /* put the 2nd cluster into PCL10 state */
  95. setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  96. }
  97. #endif
  98. if (cpu_numcores() > 1) {
  99. #ifndef CONFIG_MP
  100. puts("Unicore software on multiprocessor system!!\n"
  101. "To enable mutlticore build define CONFIG_MP\n");
  102. #endif
  103. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  104. printf("CPU%d: ", pic->whoami);
  105. } else {
  106. puts("CPU: ");
  107. }
  108. cpu = gd->arch.cpu;
  109. puts(cpu->name);
  110. if (IS_E_PROCESSOR(svr))
  111. puts("E");
  112. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  113. pvr = get_pvr();
  114. ver = PVR_VER(pvr);
  115. major = PVR_MAJ(pvr);
  116. minor = PVR_MIN(pvr);
  117. printf("Core: ");
  118. switch(ver) {
  119. case PVR_VER_E500_V1:
  120. case PVR_VER_E500_V2:
  121. puts("e500");
  122. break;
  123. case PVR_VER_E500MC:
  124. puts("e500mc");
  125. break;
  126. case PVR_VER_E5500:
  127. puts("e5500");
  128. break;
  129. case PVR_VER_E6500:
  130. puts("e6500");
  131. break;
  132. default:
  133. puts("Unknown");
  134. break;
  135. }
  136. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  137. if (nr_cores > CONFIG_MAX_CPUS) {
  138. panic("\nUnexpected number of cores: %d, max is %d\n",
  139. nr_cores, CONFIG_MAX_CPUS);
  140. }
  141. get_sys_info(&sysinfo);
  142. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  143. if (sysinfo.diff_sysclk == 1)
  144. puts("Single Source Clock Configuration\n");
  145. #endif
  146. puts("Clock Configuration:");
  147. for_each_cpu(i, core, nr_cores, mask) {
  148. if (!(i & 3))
  149. printf ("\n ");
  150. printf("CPU%d:%-4s MHz, ", core,
  151. strmhz(buf1, sysinfo.freq_processor[core]));
  152. }
  153. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  154. for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
  155. if (!(j & 3))
  156. printf("\n ");
  157. printf("DSP CPU%d:%-4s MHz, ", j,
  158. strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  159. }
  160. #endif
  161. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  162. printf("\n");
  163. #ifdef CONFIG_FSL_CORENET
  164. if (ddr_sync == 1) {
  165. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  166. "(Synchronous), ",
  167. strmhz(buf1, sysinfo.freq_ddrbus/2),
  168. strmhz(buf2, sysinfo.freq_ddrbus));
  169. } else {
  170. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  171. "(Asynchronous), ",
  172. strmhz(buf1, sysinfo.freq_ddrbus/2),
  173. strmhz(buf2, sysinfo.freq_ddrbus));
  174. }
  175. #else
  176. switch (ddr_ratio) {
  177. case 0x0:
  178. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  179. strmhz(buf1, sysinfo.freq_ddrbus/2),
  180. strmhz(buf2, sysinfo.freq_ddrbus));
  181. break;
  182. case 0x7:
  183. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  184. "(Synchronous), ",
  185. strmhz(buf1, sysinfo.freq_ddrbus/2),
  186. strmhz(buf2, sysinfo.freq_ddrbus));
  187. break;
  188. default:
  189. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  190. "(Asynchronous), ",
  191. strmhz(buf1, sysinfo.freq_ddrbus/2),
  192. strmhz(buf2, sysinfo.freq_ddrbus));
  193. break;
  194. }
  195. #endif
  196. #if defined(CONFIG_FSL_LBC)
  197. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  198. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  199. } else {
  200. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  201. sysinfo.freq_localbus);
  202. }
  203. #endif
  204. #if defined(CONFIG_FSL_IFC)
  205. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  206. #endif
  207. #ifdef CONFIG_CPM2
  208. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  209. #endif
  210. #ifdef CONFIG_QE
  211. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  212. #endif
  213. #if defined(CONFIG_SYS_CPRI)
  214. printf(" ");
  215. printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
  216. #endif
  217. #if defined(CONFIG_SYS_MAPLE)
  218. printf("\n ");
  219. printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
  220. printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
  221. printf("MAPLE-eTVPE:%-4s MHz\n",
  222. strmhz(buf1, sysinfo.freq_maple_etvpe));
  223. #endif
  224. #ifdef CONFIG_SYS_DPAA_FMAN
  225. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  226. printf(" FMAN%d: %s MHz\n", i + 1,
  227. strmhz(buf1, sysinfo.freq_fman[i]));
  228. }
  229. #endif
  230. #ifdef CONFIG_SYS_DPAA_QBMAN
  231. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  232. #endif
  233. #ifdef CONFIG_SYS_DPAA_PME
  234. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  235. #endif
  236. puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
  237. #ifdef CONFIG_FSL_CORENET
  238. /* Display the RCW, so that no one gets confused as to what RCW
  239. * we're actually using for this boot.
  240. */
  241. puts("Reset Configuration Word (RCW):");
  242. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  243. u32 rcw = in_be32(&gur->rcwsr[i]);
  244. if ((i % 4) == 0)
  245. printf("\n %08x:", i * 4);
  246. printf(" %08x", rcw);
  247. }
  248. puts("\n");
  249. #endif
  250. return 0;
  251. }
  252. /* ------------------------------------------------------------------------- */
  253. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  254. {
  255. /* Everything after the first generation of PQ3 parts has RSTCR */
  256. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  257. defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
  258. unsigned long val, msr;
  259. /*
  260. * Initiate hard reset in debug control register DBCR0
  261. * Make sure MSR[DE] = 1. This only resets the core.
  262. */
  263. msr = mfmsr ();
  264. msr |= MSR_DE;
  265. mtmsr (msr);
  266. val = mfspr(DBCR0);
  267. val |= 0x70000000;
  268. mtspr(DBCR0,val);
  269. #else
  270. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  271. /* Attempt board-specific reset */
  272. board_reset();
  273. /* Next try asserting HRESET_REQ */
  274. out_be32(&gur->rstcr, 0x2);
  275. udelay(100);
  276. #endif
  277. return 1;
  278. }
  279. /*
  280. * Get timebase clock frequency
  281. */
  282. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  283. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  284. #endif
  285. __weak unsigned long get_tbclk (void)
  286. {
  287. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  288. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  289. }
  290. #if defined(CONFIG_WATCHDOG)
  291. #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
  292. void
  293. init_85xx_watchdog(void)
  294. {
  295. mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
  296. TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
  297. }
  298. void
  299. reset_85xx_watchdog(void)
  300. {
  301. /*
  302. * Clear TSR(WIS) bit by writing 1
  303. */
  304. mtspr(SPRN_TSR, TSR_WIS);
  305. }
  306. void
  307. watchdog_reset(void)
  308. {
  309. int re_enable = disable_interrupts();
  310. reset_85xx_watchdog();
  311. if (re_enable)
  312. enable_interrupts();
  313. }
  314. #endif /* CONFIG_WATCHDOG */
  315. /*
  316. * Initializes on-chip MMC controllers.
  317. * to override, implement board_mmc_init()
  318. */
  319. int cpu_mmc_init(bd_t *bis)
  320. {
  321. #ifdef CONFIG_FSL_ESDHC
  322. return fsl_esdhc_mmc_init(bis);
  323. #else
  324. return 0;
  325. #endif
  326. }
  327. /*
  328. * Print out the state of various machine registers.
  329. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  330. * parameters for IFC and TLBs
  331. */
  332. void print_reginfo(void)
  333. {
  334. print_tlbcam();
  335. print_laws();
  336. #if defined(CONFIG_FSL_LBC)
  337. print_lbc_regs();
  338. #endif
  339. #ifdef CONFIG_FSL_IFC
  340. print_ifc_regs();
  341. #endif
  342. }
  343. /* Common ddr init for non-corenet fsl 85xx platforms */
  344. #ifndef CONFIG_FSL_CORENET
  345. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  346. !defined(CONFIG_SYS_INIT_L2_ADDR)
  347. int dram_init(void)
  348. {
  349. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
  350. defined(CONFIG_ARCH_QEMU_E500)
  351. gd->ram_size = fsl_ddr_sdram_size();
  352. #else
  353. gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  354. #endif
  355. return 0;
  356. }
  357. #else /* CONFIG_SYS_RAMBOOT */
  358. int dram_init(void)
  359. {
  360. phys_size_t dram_size = 0;
  361. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  362. {
  363. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  364. unsigned int x = 10;
  365. unsigned int i;
  366. /*
  367. * Work around to stabilize DDR DLL
  368. */
  369. out_be32(&gur->ddrdllcr, 0x81000000);
  370. asm("sync;isync;msync");
  371. udelay(200);
  372. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  373. setbits_be32(&gur->devdisr, 0x00010000);
  374. for (i = 0; i < x; i++)
  375. ;
  376. clrbits_be32(&gur->devdisr, 0x00010000);
  377. x++;
  378. }
  379. }
  380. #endif
  381. #if defined(CONFIG_SPD_EEPROM) || \
  382. defined(CONFIG_DDR_SPD) || \
  383. defined(CONFIG_SYS_DDR_RAW_TIMING)
  384. dram_size = fsl_ddr_sdram();
  385. #else
  386. dram_size = fixed_sdram();
  387. #endif
  388. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  389. dram_size *= 0x100000;
  390. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  391. /*
  392. * Initialize and enable DDR ECC.
  393. */
  394. ddr_enable_ecc(dram_size);
  395. #endif
  396. #if defined(CONFIG_FSL_LBC)
  397. /* Some boards also have sdram on the lbc */
  398. lbc_sdram_init();
  399. #endif
  400. debug("DDR: ");
  401. gd->ram_size = dram_size;
  402. return 0;
  403. }
  404. #endif /* CONFIG_SYS_RAMBOOT */
  405. #endif
  406. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  407. /* Board-specific functions defined in each board's ddr.c */
  408. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  409. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  410. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  411. phys_addr_t *rpn);
  412. unsigned int
  413. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  414. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  415. static void dump_spd_ddr_reg(void)
  416. {
  417. int i, j, k, m;
  418. u8 *p_8;
  419. u32 *p_32;
  420. struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
  421. generic_spd_eeprom_t
  422. spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  423. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  424. fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
  425. puts("SPD data of all dimms (zero value is omitted)...\n");
  426. puts("Byte (hex) ");
  427. k = 1;
  428. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  429. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  430. printf("Dimm%d ", k++);
  431. }
  432. puts("\n");
  433. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  434. m = 0;
  435. printf("%3d (0x%02x) ", k, k);
  436. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  437. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  438. p_8 = (u8 *) &spd[i][j];
  439. if (p_8[k]) {
  440. printf("0x%02x ", p_8[k]);
  441. m++;
  442. } else
  443. puts(" ");
  444. }
  445. }
  446. if (m)
  447. puts("\n");
  448. else
  449. puts("\r");
  450. }
  451. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  452. switch (i) {
  453. case 0:
  454. ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  455. break;
  456. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  457. case 1:
  458. ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  459. break;
  460. #endif
  461. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  462. case 2:
  463. ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  464. break;
  465. #endif
  466. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  467. case 3:
  468. ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  469. break;
  470. #endif
  471. default:
  472. printf("%s unexpected controller number = %u\n",
  473. __func__, i);
  474. return;
  475. }
  476. }
  477. printf("DDR registers dump for all controllers "
  478. "(zero value is omitted)...\n");
  479. puts("Offset (hex) ");
  480. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  481. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  482. puts("\n");
  483. for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
  484. m = 0;
  485. printf("%6d (0x%04x)", k * 4, k * 4);
  486. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  487. p_32 = (u32 *) ddr[i];
  488. if (p_32[k]) {
  489. printf(" 0x%08x", p_32[k]);
  490. m++;
  491. } else
  492. puts(" ");
  493. }
  494. if (m)
  495. puts("\n");
  496. else
  497. puts("\r");
  498. }
  499. puts("\n");
  500. }
  501. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  502. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  503. {
  504. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  505. unsigned long epn;
  506. u32 tsize, valid, ptr;
  507. int ddr_esel;
  508. clear_ddr_tlbs_phys(p_addr, size>>20);
  509. /* Setup new tlb to cover the physical address */
  510. setup_ddr_tlbs_phys(p_addr, size>>20);
  511. ptr = vstart;
  512. ddr_esel = find_tlb_idx((void *)ptr, 1);
  513. if (ddr_esel != -1) {
  514. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  515. } else {
  516. printf("TLB error in function %s\n", __func__);
  517. return -1;
  518. }
  519. return 0;
  520. }
  521. /*
  522. * slide the testing window up to test another area
  523. * for 32_bit system, the maximum testable memory is limited to
  524. * CONFIG_MAX_MEM_MAPPED
  525. */
  526. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  527. {
  528. phys_addr_t test_cap, p_addr;
  529. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  530. #if !defined(CONFIG_PHYS_64BIT) || \
  531. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  532. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  533. test_cap = p_size;
  534. #else
  535. test_cap = gd->ram_size;
  536. #endif
  537. p_addr = (*vstart) + (*size) + (*phys_offset);
  538. if (p_addr < test_cap - 1) {
  539. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  540. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  541. return -1;
  542. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  543. *size = (u32) p_size;
  544. printf("Testing 0x%08llx - 0x%08llx\n",
  545. (u64)(*vstart) + (*phys_offset),
  546. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  547. } else
  548. return 1;
  549. return 0;
  550. }
  551. /* initialization for testing area */
  552. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  553. {
  554. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  555. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  556. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  557. *phys_offset = 0;
  558. #if !defined(CONFIG_PHYS_64BIT) || \
  559. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  560. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  561. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  562. puts("Cannot test more than ");
  563. print_size(CONFIG_MAX_MEM_MAPPED,
  564. " without proper 36BIT support.\n");
  565. }
  566. #endif
  567. printf("Testing 0x%08llx - 0x%08llx\n",
  568. (u64)(*vstart) + (*phys_offset),
  569. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  570. return 0;
  571. }
  572. /* invalid TLBs for DDR and remap as normal after testing */
  573. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  574. {
  575. unsigned long epn;
  576. u32 tsize, valid, ptr;
  577. phys_addr_t rpn = 0;
  578. int ddr_esel;
  579. /* disable the TLBs for this testing */
  580. ptr = *vstart;
  581. while (ptr < (*vstart) + (*size)) {
  582. ddr_esel = find_tlb_idx((void *)ptr, 1);
  583. if (ddr_esel != -1) {
  584. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  585. disable_tlb(ddr_esel);
  586. }
  587. ptr += TSIZE_TO_BYTES(tsize);
  588. }
  589. puts("Remap DDR ");
  590. setup_ddr_tlbs(gd->ram_size>>20);
  591. puts("\n");
  592. return 0;
  593. }
  594. void arch_memory_failure_handle(void)
  595. {
  596. dump_spd_ddr_reg();
  597. }
  598. #endif