cpu.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * CPU specific code for the MPC83xx family.
  7. *
  8. * Derived from the MPC8260 and MPC85xx.
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <irq_func.h>
  13. #include <vsprintf.h>
  14. #include <watchdog.h>
  15. #include <command.h>
  16. #include <mpc83xx.h>
  17. #include <asm/processor.h>
  18. #include <linux/libfdt.h>
  19. #include <tsec.h>
  20. #include <netdev.h>
  21. #include <fsl_esdhc.h>
  22. #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
  23. #include <linux/immap_qe.h>
  24. #include <asm/io.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #ifndef CONFIG_CPU_MPC83XX
  28. int checkcpu(void)
  29. {
  30. volatile immap_t *immr;
  31. ulong clock = gd->cpu_clk;
  32. u32 pvr = get_pvr();
  33. u32 spridr;
  34. char buf[32];
  35. int ret;
  36. int i;
  37. const struct cpu_type {
  38. char name[15];
  39. u32 partid;
  40. } cpu_type_list [] = {
  41. CPU_TYPE_ENTRY(8308),
  42. CPU_TYPE_ENTRY(8309),
  43. CPU_TYPE_ENTRY(8311),
  44. CPU_TYPE_ENTRY(8313),
  45. CPU_TYPE_ENTRY(8314),
  46. CPU_TYPE_ENTRY(8315),
  47. CPU_TYPE_ENTRY(8321),
  48. CPU_TYPE_ENTRY(8323),
  49. CPU_TYPE_ENTRY(8343),
  50. CPU_TYPE_ENTRY(8347_TBGA_),
  51. CPU_TYPE_ENTRY(8347_PBGA_),
  52. CPU_TYPE_ENTRY(8349),
  53. CPU_TYPE_ENTRY(8358_TBGA_),
  54. CPU_TYPE_ENTRY(8358_PBGA_),
  55. CPU_TYPE_ENTRY(8360),
  56. CPU_TYPE_ENTRY(8377),
  57. CPU_TYPE_ENTRY(8378),
  58. CPU_TYPE_ENTRY(8379),
  59. };
  60. immr = (immap_t *)CONFIG_SYS_IMMR;
  61. ret = prt_83xx_rsr();
  62. if (ret)
  63. return ret;
  64. puts("CPU: ");
  65. switch (pvr & 0xffff0000) {
  66. case PVR_E300C1:
  67. printf("e300c1, ");
  68. break;
  69. case PVR_E300C2:
  70. printf("e300c2, ");
  71. break;
  72. case PVR_E300C3:
  73. printf("e300c3, ");
  74. break;
  75. case PVR_E300C4:
  76. printf("e300c4, ");
  77. break;
  78. default:
  79. printf("Unknown core, ");
  80. }
  81. spridr = immr->sysconf.spridr;
  82. for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  83. if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  84. puts("MPC");
  85. puts(cpu_type_list[i].name);
  86. if (IS_E_PROCESSOR(spridr))
  87. puts("E");
  88. if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
  89. SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
  90. REVID_MAJOR(spridr) >= 2)
  91. puts("A");
  92. printf(", Rev: %d.%d", REVID_MAJOR(spridr),
  93. REVID_MINOR(spridr));
  94. break;
  95. }
  96. if (i == ARRAY_SIZE(cpu_type_list))
  97. printf("(SPRIDR %08x unknown), ", spridr);
  98. printf(" at %s MHz, ", strmhz(buf, clock));
  99. printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
  100. return 0;
  101. }
  102. #endif
  103. #ifndef CONFIG_SYSRESET
  104. int
  105. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  106. {
  107. ulong msr;
  108. #ifndef MPC83xx_RESET
  109. ulong addr;
  110. #endif
  111. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  112. puts("Resetting the board.\n");
  113. #ifdef MPC83xx_RESET
  114. /* Interrupts and MMU off */
  115. msr = mfmsr();
  116. msr &= ~(MSR_EE | MSR_IR | MSR_DR);
  117. mtmsr(msr);
  118. /* enable Reset Control Reg */
  119. immap->reset.rpr = 0x52535445;
  120. sync();
  121. isync();
  122. /* confirm Reset Control Reg is enabled */
  123. while(!((immap->reset.rcer) & RCER_CRE))
  124. ;
  125. udelay(200);
  126. /* perform reset, only one bit */
  127. immap->reset.rcr = RCR_SWHR;
  128. #else /* ! MPC83xx_RESET */
  129. immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
  130. /* Interrupts and MMU off */
  131. msr = mfmsr();
  132. msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
  133. mtmsr(msr);
  134. /*
  135. * Trying to execute the next instruction at a non-existing address
  136. * should cause a machine check, resulting in reset
  137. */
  138. addr = CONFIG_SYS_RESET_ADDRESS;
  139. ((void (*)(void)) addr) ();
  140. #endif /* MPC83xx_RESET */
  141. return 1;
  142. }
  143. #endif
  144. /*
  145. * Get timebase clock frequency (like cpu_clk in Hz)
  146. */
  147. #ifndef CONFIG_TIMER
  148. unsigned long get_tbclk(void)
  149. {
  150. return (gd->bus_clk + 3L) / 4L;
  151. }
  152. #endif
  153. #if defined(CONFIG_WATCHDOG)
  154. void watchdog_reset (void)
  155. {
  156. int re_enable = disable_interrupts();
  157. /* Reset the 83xx watchdog */
  158. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  159. immr->wdt.swsrr = 0x556c;
  160. immr->wdt.swsrr = 0xaa39;
  161. if (re_enable)
  162. enable_interrupts();
  163. }
  164. #endif
  165. #ifndef CONFIG_DM_ETH
  166. /*
  167. * Initializes on-chip ethernet controllers.
  168. * to override, implement board_eth_init()
  169. */
  170. int cpu_eth_init(bd_t *bis)
  171. {
  172. #if defined(CONFIG_UEC_ETH)
  173. uec_standard_init(bis);
  174. #endif
  175. #if defined(CONFIG_TSEC_ENET)
  176. tsec_standard_init(bis);
  177. #endif
  178. return 0;
  179. }
  180. #endif /* !CONFIG_DM_ETH */
  181. /*
  182. * Initializes on-chip MMC controllers.
  183. * to override, implement board_mmc_init()
  184. */
  185. int cpu_mmc_init(bd_t *bis)
  186. {
  187. #ifdef CONFIG_FSL_ESDHC
  188. return fsl_esdhc_mmc_init(bis);
  189. #else
  190. return 0;
  191. #endif
  192. }
  193. void ppcDWstore(unsigned int *addr, unsigned int *value)
  194. {
  195. asm("lfd 1, 0(%1)\n\t"
  196. "stfd 1, 0(%0)"
  197. :
  198. : "r" (addr), "r" (value)
  199. : "memory");
  200. }
  201. void ppcDWload(unsigned int *addr, unsigned int *ret)
  202. {
  203. asm("lfd 1, 0(%0)\n\t"
  204. "stfd 1, 0(%1)"
  205. :
  206. : "r" (addr), "r" (ret)
  207. : "memory");
  208. }