o4-imx6ull-nano.dtsi 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
  3. /dts-v1/;
  4. #include "imx6ull.dtsi"
  5. / {
  6. model = "O4-iMX6ULL-NANO";
  7. compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull";
  8. aliases {
  9. mmc0 = &usdhc2;
  10. };
  11. memory@80000000 {
  12. device_type = "memory";
  13. reg = <0x80000000 0x20000000>;
  14. };
  15. };
  16. &iomuxc {
  17. pinctrl_usdhc2: usdhc2grp {
  18. fsl,pins = <
  19. MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
  20. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  21. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  22. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  23. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  24. MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
  25. MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
  26. MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
  27. MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
  28. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
  29. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  30. >;
  31. };
  32. pinctrl_fec1: fec1grp {
  33. fsl,pins = <
  34. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  35. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  36. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  37. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  38. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
  39. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  40. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  41. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  42. >;
  43. };
  44. pinctrl_fec2: fec2grp {
  45. fsl,pins = <
  46. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  47. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  48. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  49. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  50. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
  51. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  52. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  53. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  54. >;
  55. };
  56. pinctrl_phy0_irq: phy0grp {
  57. fsl,pins = <
  58. MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79
  59. >;
  60. };
  61. pinctrl_phy1_irq: phy1grp {
  62. fsl,pins = <
  63. MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
  64. >;
  65. };
  66. };
  67. &usdhc2 {
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&pinctrl_usdhc2>;
  70. no-1-8-v;
  71. non-removable;
  72. keep-power-in-suspend;
  73. wakeup-source;
  74. bus-width = <8>;
  75. status = "okay";
  76. };