o4-imx-nano.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
  3. /dts-v1/;
  4. #include <dt-bindings/leds/common.h>
  5. #include "o4-imx6ull-nano.dtsi"
  6. / {
  7. model = "O4-iMX-NANO";
  8. compatible = "out4,o4-imx-nano",
  9. "out4,o4-imx6ull-nano",
  10. "fsl,imx6ull";
  11. aliases {
  12. mmc1 = &usdhc1;
  13. };
  14. chosen {
  15. stdout-path = &uart1;
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. led@0 {
  20. color = <LED_COLOR_ID_RED>;
  21. gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>;
  22. reg = <0>;
  23. };
  24. led@1 {
  25. color = <LED_COLOR_ID_GREEN>;
  26. gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>;
  27. reg = <1>;
  28. };
  29. led@2 {
  30. gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>;
  31. color = <LED_COLOR_ID_BLUE>;
  32. reg = <2>;
  33. };
  34. led@3 {
  35. color = <LED_COLOR_ID_RED>;
  36. gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
  37. reg = <3>;
  38. };
  39. led@4 {
  40. color = <LED_COLOR_ID_GREEN>;
  41. gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>;
  42. reg = <4>;
  43. };
  44. led@5 {
  45. color = <LED_COLOR_ID_BLUE>;
  46. gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>;
  47. reg = <5>;
  48. };
  49. };
  50. usbotg1_vbus: reg_usbotg1_vbus {
  51. compatible = "regulator-fixed";
  52. enable-active-high;
  53. gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>;
  54. regulator-max-microvolt = <5000000>;
  55. regulator-min-microvolt = <5000000>;
  56. regulator-name = "usb0";
  57. };
  58. usbotg2_vbus: reg_usbotg2_vbus {
  59. compatible = "regulator-fixed";
  60. enable-active-high;
  61. gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>;
  62. regulator-max-microvolt = <5000000>;
  63. regulator-min-microvolt = <5000000>;
  64. regulator-name = "usb1";
  65. };
  66. };
  67. &iomuxc {
  68. pinctrl_uart1: uart1grp {
  69. fsl,pins = <
  70. MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  71. MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  72. >;
  73. };
  74. pinctrl_usdhc1: usdhc1grp {
  75. fsl,pins = <
  76. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069
  77. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  78. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  79. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  80. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  81. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  82. MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
  83. >;
  84. };
  85. pinctrl_mdio: mdiogrp {
  86. fsl,pins = <
  87. MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  88. MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
  89. MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */
  90. >;
  91. };
  92. pinctrl_i2c2: i2c2grp {
  93. fsl,pins = <
  94. MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
  95. MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
  96. >;
  97. };
  98. pinctrl_i2c2_gpio: i2c2gpiogrp {
  99. fsl,pins = <
  100. MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0
  101. MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0
  102. >;
  103. };
  104. pinctrl_can1: can1grp {
  105. fsl,pins = <
  106. MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
  107. MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
  108. >;
  109. };
  110. pinctrl_uart2: uart2grp {
  111. fsl,pins = <
  112. MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
  113. MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
  114. MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
  115. >;
  116. };
  117. };
  118. &uart1 {
  119. pinctrl-0 = <&pinctrl_uart1>;
  120. pinctrl-names = "default";
  121. status = "okay";
  122. };
  123. &usdhc1 {
  124. bus-width = <4>;
  125. no-1-8-v;
  126. pinctrl-0 = <&pinctrl_usdhc1>;
  127. pinctrl-names = "default";
  128. status = "okay";
  129. wakeup-source;
  130. };
  131. &fec1 {
  132. phy-handle = <&phy0>;
  133. phy-mode = "rmii";
  134. pinctrl-0 = <&pinctrl_fec1>;
  135. pinctrl-names = "default";
  136. status = "okay";
  137. };
  138. &fec2 {
  139. phy-handle = <&phy1>;
  140. phy-mode = "rmii";
  141. phy-reset-duration = <250>;
  142. phy-reset-post-delay = <100>;
  143. phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
  144. pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>;
  145. pinctrl-names = "default";
  146. status = "okay";
  147. mdio {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. phy0: ethernet-phy@0 {
  151. clocks = <&clks IMX6UL_CLK_ENET_REF>;
  152. clock-names = "rmii-ref";
  153. interrupt-parent = <&gpio5>;
  154. interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
  155. pinctrl-0 = <&pinctrl_phy0_irq>;
  156. pinctrl-names = "default";
  157. reg = <0>;
  158. };
  159. phy1: ethernet-phy@1 {
  160. clocks = <&clks IMX6UL_CLK_ENET2_REF>;
  161. clock-names = "rmii-ref";
  162. interrupt-parent = <&gpio5>;
  163. interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  164. pinctrl-0 = <&pinctrl_phy1_irq>;
  165. pinctrl-names = "default";
  166. reg = <1>;
  167. };
  168. };
  169. };
  170. &usbotg1 {
  171. dr_mode = "host";
  172. status = "okay";
  173. vbus-supply = <&usbotg1_vbus>;
  174. };
  175. &usbotg2 {
  176. dr_mode = "host";
  177. status = "okay";
  178. vbus-supply = <&usbotg2_vbus>;
  179. };
  180. &i2c2 {
  181. clock_frequency = <100000>;
  182. pinctrl-0 = <&pinctrl_i2c2>;
  183. pinctrl-1 = <&pinctrl_i2c2_gpio>;
  184. pinctrl-names = "default", "gpio";
  185. scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  186. sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  187. status = "okay";
  188. pcf8574a: gpio@38 {
  189. compatible = "nxp,pcf8574a";
  190. #gpio-cells = <2>;
  191. gpio-controller;
  192. reg = <0x38>;
  193. };
  194. };
  195. &can1 {
  196. pinctrl-names = "default";
  197. pinctrl-0 = <&pinctrl_can1>;
  198. status = "okay";
  199. };
  200. &uart2 {
  201. linux,rs485-enabled-at-boot-time;
  202. pinctrl-0 = <&pinctrl_uart2>;
  203. pinctrl-names = "default";
  204. status = "okay";
  205. uart-has-rtscts;
  206. };