gose.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/gose/gose.c
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <hang.h>
  11. #include <init.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <asm/global_data.h>
  15. #include <dm/platform_data/serial_sh.h>
  16. #include <env_internal.h>
  17. #include <asm/processor.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/io.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/errno.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/gpio.h>
  25. #include <asm/arch/rmobile.h>
  26. #include <asm/arch/rcar-mstp.h>
  27. #include <asm/arch/sh_sdhi.h>
  28. #include <netdev.h>
  29. #include <miiphy.h>
  30. #include <i2c.h>
  31. #include "qos.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  34. void s_init(void)
  35. {
  36. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  37. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  38. u32 stc;
  39. /* Watchdog init */
  40. writel(0xA5A5A500, &rwdt->rwtcsra);
  41. writel(0xA5A5A500, &swdt->swtcsra);
  42. /* CPU frequency setting. Set to 1.5GHz */
  43. stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  44. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  45. /* QoS */
  46. qos_init();
  47. }
  48. #define TMU0_MSTP125 BIT(25)
  49. #define SD1CKCR 0xE6150078
  50. #define SD2CKCR 0xE615026C
  51. #define SD_97500KHZ 0x7
  52. int board_early_init_f(void)
  53. {
  54. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  55. /*
  56. * SD0 clock is set to 97.5MHz by default.
  57. * Set SD1 and SD2 to the 97.5MHz as well.
  58. */
  59. writel(SD_97500KHZ, SD1CKCR);
  60. writel(SD_97500KHZ, SD2CKCR);
  61. return 0;
  62. }
  63. #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
  64. int board_init(void)
  65. {
  66. /* adress of boot parameters */
  67. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  68. /* Force ethernet PHY out of reset */
  69. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  70. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  71. mdelay(10);
  72. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  73. return 0;
  74. }
  75. int dram_init(void)
  76. {
  77. if (fdtdec_setup_mem_size_base() != 0)
  78. return -EINVAL;
  79. return 0;
  80. }
  81. int dram_init_banksize(void)
  82. {
  83. fdtdec_setup_memory_banksize();
  84. return 0;
  85. }
  86. /* KSZ8041RNLI */
  87. #define PHY_CONTROL1 0x1E
  88. #define PHY_LED_MODE 0xC000
  89. #define PHY_LED_MODE_ACK 0x4000
  90. int board_phy_config(struct phy_device *phydev)
  91. {
  92. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  93. ret &= ~PHY_LED_MODE;
  94. ret |= PHY_LED_MODE_ACK;
  95. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  96. return 0;
  97. }
  98. void reset_cpu(void)
  99. {
  100. struct udevice *dev;
  101. const u8 pmic_bus = 6;
  102. const u8 pmic_addr = 0x58;
  103. u8 data;
  104. int ret;
  105. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  106. if (ret)
  107. hang();
  108. ret = dm_i2c_read(dev, 0x13, &data, 1);
  109. if (ret)
  110. hang();
  111. data |= BIT(1);
  112. ret = dm_i2c_write(dev, 0x13, &data, 1);
  113. if (ret)
  114. hang();
  115. }
  116. enum env_location env_get_location(enum env_operation op, int prio)
  117. {
  118. const u32 load_magic = 0xb33fc0de;
  119. /* Block environment access if loaded using JTAG */
  120. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  121. (op != ENVOP_INIT))
  122. return ENVL_UNKNOWN;
  123. if (prio)
  124. return ENVL_UNKNOWN;
  125. return ENVL_SPI_FLASH;
  126. }