eagle.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/renesas/eagle/eagle.c
  4. * This file is Eagle board support.
  5. *
  6. * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <hang.h>
  11. #include <init.h>
  12. #include <malloc.h>
  13. #include <netdev.h>
  14. #include <dm.h>
  15. #include <asm/global_data.h>
  16. #include <dm/platform_data/serial_sh.h>
  17. #include <asm/processor.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/io.h>
  20. #include <linux/errno.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/gpio.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/rmobile.h>
  25. #include <asm/arch/rcar-mstp.h>
  26. #include <asm/arch/sh_sdhi.h>
  27. #include <i2c.h>
  28. #include <mmc.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define CPGWPR 0xE6150900
  31. #define CPGWPCR 0xE6150904
  32. /* PLL */
  33. #define PLL0CR 0xE61500D8
  34. #define PLL0_STC_MASK 0x7F000000
  35. #define PLL0_STC_OFFSET 24
  36. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  37. void s_init(void)
  38. {
  39. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  40. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  41. u32 stc;
  42. /* Watchdog init */
  43. writel(0xA5A5A500, &rwdt->rwtcsra);
  44. writel(0xA5A5A500, &swdt->swtcsra);
  45. /* CPU frequency setting. Set to 0.8GHz */
  46. stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
  47. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  48. }
  49. int board_early_init_f(void)
  50. {
  51. /* Unlock CPG access */
  52. writel(0xA5A5FFFF, CPGWPR);
  53. writel(0x5A5A0000, CPGWPCR);
  54. return 0;
  55. }
  56. int board_init(void)
  57. {
  58. /* adress of boot parameters */
  59. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  60. return 0;
  61. }
  62. #define RST_BASE 0xE6160000
  63. #define RST_CA57RESCNT (RST_BASE + 0x40)
  64. #define RST_CA53RESCNT (RST_BASE + 0x44)
  65. #define RST_RSTOUTCR (RST_BASE + 0x58)
  66. #define RST_CA57_CODE 0xA5A5000F
  67. #define RST_CA53_CODE 0x5A5A000F
  68. void reset_cpu(void)
  69. {
  70. unsigned long midr, cputype;
  71. asm volatile("mrs %0, midr_el1" : "=r" (midr));
  72. cputype = (midr >> 4) & 0xfff;
  73. if (cputype == 0xd03)
  74. writel(RST_CA53_CODE, RST_CA53RESCNT);
  75. else if (cputype == 0xd07)
  76. writel(RST_CA57_CODE, RST_CA57RESCNT);
  77. else
  78. hang();
  79. }