blanche.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/blanche/blanche.c
  4. * This file is blanche board support.
  5. *
  6. * Copyright (C) 2016 Renesas Electronics Corporation
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <asm/arch/mmc.h>
  13. #include <asm/arch/rcar-mstp.h>
  14. #include <asm/arch/rmobile.h>
  15. #include <asm/arch/sh_sdhi.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/global_data.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <asm/mach-types.h>
  21. #include <asm/processor.h>
  22. #include <dm.h>
  23. #include <dm/platform_data/serial_sh.h>
  24. #include <env.h>
  25. #include <hang.h>
  26. #include <i2c.h>
  27. #include <linux/bitops.h>
  28. #include <linux/errno.h>
  29. #include <malloc.h>
  30. #include <miiphy.h>
  31. #include <mmc.h>
  32. #include <netdev.h>
  33. #include "qos.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define CPG_PLL1CR 0xE6150028
  36. #define CPG_PLL3CR 0xE61500DC
  37. #define TMU0_MSTP125 BIT(25)
  38. #define QSPI_MSTP917 BIT(17)
  39. struct reg_config {
  40. u16 off;
  41. u32 val;
  42. };
  43. static void blanche_init_sys(void)
  44. {
  45. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  46. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  47. u32 cpu_type;
  48. cpu_type = rmobile_get_cpu_type();
  49. if (cpu_type == 0x4A) {
  50. writel(0x4D000000, CPG_PLL1CR);
  51. writel(0x4F000000, CPG_PLL3CR);
  52. }
  53. /* Watchdog init */
  54. writel(0xA5A5A500, &rwdt->rwtcsra);
  55. writel(0xA5A5A500, &swdt->swtcsra);
  56. }
  57. static void blanche_init_pfc(void)
  58. {
  59. static const struct reg_config pfc_with_unlock[] = {
  60. { 0x0004, 0x0bffffff },
  61. { 0x0008, 0x002fffff },
  62. { 0x0014, 0x00000fff },
  63. { 0x0018, 0x00010fff },
  64. { 0x001c, 0x00010fff },
  65. { 0x0020, 0x00010fff },
  66. { 0x0024, 0x00010fff },
  67. { 0x0028, 0x00010fff },
  68. { 0x002c, 0x04006000 },
  69. { 0x0030, 0x303fefe0 },
  70. { 0x0058, 0x0002000e },
  71. };
  72. static const struct reg_config pfc_without_unlock[] = {
  73. { 0x0108, 0x00000000 },
  74. { 0x010c, 0x0803FF40 },
  75. { 0x0110, 0x0000FFFF },
  76. { 0x0114, 0x00010FFF },
  77. { 0x011c, 0x0001AFFF },
  78. { 0x0124, 0x0001CFFF },
  79. { 0x0128, 0xC0438001 },
  80. { 0x012c, 0x0FC00007 },
  81. };
  82. static const u32 pfc_base = 0xe6060000;
  83. unsigned int i;
  84. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  85. writel(~pfc_with_unlock[i].val, pfc_base);
  86. writel(pfc_with_unlock[i].val,
  87. pfc_base | pfc_with_unlock[i].off);
  88. }
  89. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  90. writel(pfc_without_unlock[i].val,
  91. pfc_base | pfc_without_unlock[i].off);
  92. }
  93. static void blanche_init_lbsc(void)
  94. {
  95. static const struct reg_config lbsc_config[] = {
  96. { 0x00, 0x00000020 },
  97. { 0x08, 0x00002020 },
  98. { 0x30, 0x2a103320 },
  99. { 0x38, 0x19102110 },
  100. };
  101. static const u32 lbsc_base = 0xfec00200;
  102. unsigned int i;
  103. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  104. writel(lbsc_config[i].val,
  105. lbsc_base | lbsc_config[i].off);
  106. writel(lbsc_config[i].val,
  107. lbsc_base | (lbsc_config[i].off + 4));
  108. }
  109. }
  110. #if defined(CONFIG_MTD_NOR_FLASH)
  111. static void dbsc_wait(u16 reg)
  112. {
  113. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  114. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  115. ;
  116. }
  117. static void blanche_init_dbsc(void)
  118. {
  119. static const struct reg_config dbsc_config1[] = {
  120. { 0x0280, 0x0000a55a },
  121. { 0x0018, 0x21000000 },
  122. { 0x0018, 0x11000000 },
  123. { 0x0018, 0x10000000 },
  124. { 0x0290, 0x00000001 },
  125. { 0x02a0, 0x80000000 },
  126. { 0x0290, 0x00000004 },
  127. };
  128. static const struct reg_config dbsc_config2[] = {
  129. { 0x0290, 0x00000006 },
  130. { 0x02a0, 0x0001c000 },
  131. };
  132. static const struct reg_config dbsc_config4[] = {
  133. { 0x0290, 0x0000000f },
  134. { 0x02a0, 0x00181ee4 },
  135. { 0x0290, 0x00000010 },
  136. { 0x02a0, 0xf00464db },
  137. { 0x0290, 0x00000061 },
  138. { 0x02a0, 0x0000008d },
  139. { 0x0290, 0x00000001 },
  140. { 0x02a0, 0x00000073 },
  141. { 0x0020, 0x00000007 },
  142. { 0x0024, 0x0f030a02 },
  143. { 0x0030, 0x00000001 },
  144. { 0x00b0, 0x00000000 },
  145. { 0x0040, 0x0000000b },
  146. { 0x0044, 0x00000008 },
  147. { 0x0048, 0x00000000 },
  148. { 0x0050, 0x0000000b },
  149. { 0x0054, 0x000c000b },
  150. { 0x0058, 0x00000027 },
  151. { 0x005c, 0x0000001c },
  152. { 0x0060, 0x00000006 },
  153. { 0x0064, 0x00000020 },
  154. { 0x0068, 0x00000008 },
  155. { 0x006c, 0x0000000c },
  156. { 0x0070, 0x00000009 },
  157. { 0x0074, 0x00000012 },
  158. { 0x0078, 0x000000d0 },
  159. { 0x007c, 0x00140005 },
  160. { 0x0080, 0x00050004 },
  161. { 0x0084, 0x70233005 },
  162. { 0x0088, 0x000c0000 },
  163. { 0x008c, 0x00000300 },
  164. { 0x0090, 0x00000040 },
  165. { 0x0100, 0x00000001 },
  166. { 0x00c0, 0x00020001 },
  167. { 0x00c8, 0x20082004 },
  168. { 0x0380, 0x00020002 },
  169. { 0x0390, 0x0000001f },
  170. };
  171. static const struct reg_config dbsc_config5[] = {
  172. { 0x0244, 0x00000011 },
  173. { 0x0290, 0x00000003 },
  174. { 0x02a0, 0x0300c4e1 },
  175. { 0x0290, 0x00000023 },
  176. { 0x02a0, 0x00fcdb60 },
  177. { 0x0290, 0x00000011 },
  178. { 0x02a0, 0x1000040b },
  179. { 0x0290, 0x00000012 },
  180. { 0x02a0, 0x9d9cbb66 },
  181. { 0x0290, 0x00000013 },
  182. { 0x02a0, 0x1a868400 },
  183. { 0x0290, 0x00000014 },
  184. { 0x02a0, 0x300214d8 },
  185. { 0x0290, 0x00000015 },
  186. { 0x02a0, 0x00000d70 },
  187. { 0x0290, 0x00000016 },
  188. { 0x02a0, 0x00000004 },
  189. { 0x0290, 0x00000017 },
  190. { 0x02a0, 0x00000018 },
  191. { 0x0290, 0x0000001a },
  192. { 0x02a0, 0x910035c7 },
  193. { 0x0290, 0x00000004 },
  194. };
  195. static const struct reg_config dbsc_config6[] = {
  196. { 0x0290, 0x00000001 },
  197. { 0x02a0, 0x00000181 },
  198. { 0x0018, 0x11000000 },
  199. { 0x0290, 0x00000004 },
  200. };
  201. static const struct reg_config dbsc_config7[] = {
  202. { 0x0290, 0x00000001 },
  203. { 0x02a0, 0x0000fe01 },
  204. { 0x0304, 0x00000000 },
  205. { 0x00f4, 0x01004c20 },
  206. { 0x00f8, 0x014000aa },
  207. { 0x00e0, 0x00000140 },
  208. { 0x00e4, 0x00081860 },
  209. { 0x00e8, 0x00010000 },
  210. { 0x0290, 0x00000004 },
  211. };
  212. static const struct reg_config dbsc_config8[] = {
  213. { 0x0014, 0x00000001 },
  214. { 0x0010, 0x00000001 },
  215. { 0x0280, 0x00000000 },
  216. };
  217. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  218. unsigned int i;
  219. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
  220. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  221. dbsc_wait(0x2a0);
  222. for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
  223. writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
  224. for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
  225. writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
  226. dbsc_wait(0x240);
  227. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
  228. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  229. dbsc_wait(0x2a0);
  230. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
  231. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  232. dbsc_wait(0x2a0);
  233. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
  234. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  235. dbsc_wait(0x2a0);
  236. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
  237. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  238. }
  239. static void s_init_wait(volatile unsigned int cnt)
  240. {
  241. volatile u32 i = cnt * 0x10000;
  242. while (i-- > 0)
  243. ;
  244. }
  245. #endif
  246. void s_init(void)
  247. {
  248. blanche_init_sys();
  249. qos_init();
  250. blanche_init_pfc();
  251. blanche_init_lbsc();
  252. #if defined(CONFIG_MTD_NOR_FLASH)
  253. s_init_wait(10);
  254. blanche_init_dbsc();
  255. #endif /* CONFIG_MTD_NOR_FLASH */
  256. }
  257. int board_early_init_f(void)
  258. {
  259. /* TMU0 */
  260. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  261. /* QSPI */
  262. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  263. return 0;
  264. }
  265. int board_init(void)
  266. {
  267. /* adress of boot parameters */
  268. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  269. return 0;
  270. }
  271. /* Added for BLANCHE(R-CarV2H board) */
  272. #ifndef CONFIG_DM_ETH
  273. int board_eth_init(struct bd_info *bis)
  274. {
  275. int rc = 0;
  276. #ifdef CONFIG_SMC911X
  277. struct eth_device *dev;
  278. uchar eth_addr[6];
  279. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  280. if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
  281. dev = eth_get_dev_by_index(0);
  282. if (dev) {
  283. eth_env_set_enetaddr("ethaddr", dev->enetaddr);
  284. } else {
  285. printf("blanche: Couldn't get eth device\n");
  286. rc = -1;
  287. }
  288. }
  289. #endif
  290. return rc;
  291. }
  292. #endif
  293. int dram_init(void)
  294. {
  295. if (fdtdec_setup_mem_size_base() != 0)
  296. return -EINVAL;
  297. return 0;
  298. }
  299. int dram_init_banksize(void)
  300. {
  301. fdtdec_setup_memory_banksize();
  302. return 0;
  303. }
  304. void reset_cpu(void)
  305. {
  306. struct udevice *dev;
  307. const u8 pmic_bus = 6;
  308. const u8 pmic_addr = 0x58;
  309. u8 data;
  310. int ret;
  311. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  312. if (ret)
  313. hang();
  314. ret = dm_i2c_read(dev, 0x13, &data, 1);
  315. if (ret)
  316. hang();
  317. data |= BIT(1);
  318. ret = dm_i2c_write(dev, 0x13, &data, 1);
  319. if (ret)
  320. hang();
  321. }