alt_spl.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/alt/alt_spl.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <dm/platform_data/serial_sh.h>
  12. #include <asm/processor.h>
  13. #include <asm/mach-types.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/errno.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/rmobile.h>
  20. #include <asm/arch/rcar-mstp.h>
  21. #include <spl.h>
  22. #define TMU0_MSTP125 BIT(25)
  23. #define SCIF2_MSTP719 BIT(19)
  24. #define QSPI_MSTP917 BIT(17)
  25. #define SD1CKCR 0xE6150078
  26. #define SD_97500KHZ 0x7
  27. struct reg_config {
  28. u16 off;
  29. u32 val;
  30. };
  31. static void dbsc_wait(u16 reg)
  32. {
  33. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  34. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  35. ;
  36. }
  37. static void spl_init_sys(void)
  38. {
  39. u32 r0 = 0;
  40. writel(0xa5a5a500, 0xe6020004);
  41. writel(0xa5a5a500, 0xe6030004);
  42. asm volatile(
  43. /* ICIALLU - Invalidate I$ to PoU */
  44. "mcr 15, 0, %0, cr7, cr5, 0 \n"
  45. /* BPIALL - Invalidate branch predictors */
  46. "mcr 15, 0, %0, cr7, cr5, 6 \n"
  47. /* Set SCTLR[IZ] */
  48. "mrc 15, 0, %0, cr1, cr0, 0 \n"
  49. "orr %0, #0x1800 \n"
  50. "mcr 15, 0, %0, cr1, cr0, 0 \n"
  51. "isb sy \n"
  52. :"=r"(r0));
  53. }
  54. static void spl_init_pfc(void)
  55. {
  56. static const struct reg_config pfc_with_unlock[] = {
  57. { 0x0090, 0x00000000 },
  58. { 0x0094, 0x00000000 },
  59. { 0x0098, 0x00000000 },
  60. { 0x0020, 0x00000000 },
  61. { 0x0024, 0x00000000 },
  62. { 0x0028, 0x40000000 },
  63. { 0x002c, 0x00000155 },
  64. { 0x0030, 0x00000002 },
  65. { 0x0034, 0x00000000 },
  66. { 0x0038, 0x00000000 },
  67. { 0x003c, 0x00000000 },
  68. { 0x0040, 0x60000000 },
  69. { 0x0044, 0x36dab6db },
  70. { 0x0048, 0x926da012 },
  71. { 0x004c, 0x0008c383 },
  72. { 0x0050, 0x00000000 },
  73. { 0x0054, 0x00000140 },
  74. { 0x0004, 0xffffffff },
  75. { 0x0008, 0x00ec3fff },
  76. { 0x000c, 0x5bffffff },
  77. { 0x0010, 0x01bfe1ff },
  78. { 0x0014, 0x5bffffff },
  79. { 0x0018, 0x0f4b200f },
  80. { 0x001c, 0x03ffffff },
  81. };
  82. static const struct reg_config pfc_without_unlock[] = {
  83. { 0x0100, 0x00000000 },
  84. { 0x0104, 0x4203fc00 },
  85. { 0x0108, 0x00000000 },
  86. { 0x010c, 0x159007ff },
  87. { 0x0110, 0x80000000 },
  88. { 0x0114, 0x00de481f },
  89. { 0x0118, 0x00000000 },
  90. };
  91. static const struct reg_config pfc_with_unlock2[] = {
  92. { 0x0060, 0xffffffff },
  93. { 0x0064, 0xfffff000 },
  94. { 0x0068, 0x55555500 },
  95. { 0x006c, 0xffffff00 },
  96. { 0x0070, 0x00000000 },
  97. };
  98. static const u32 pfc_base = 0xe6060000;
  99. unsigned int i;
  100. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  101. writel(~pfc_with_unlock[i].val, pfc_base);
  102. writel(pfc_with_unlock[i].val,
  103. pfc_base | pfc_with_unlock[i].off);
  104. }
  105. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  106. writel(pfc_without_unlock[i].val,
  107. pfc_base | pfc_without_unlock[i].off);
  108. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
  109. writel(~pfc_with_unlock2[i].val, pfc_base);
  110. writel(pfc_with_unlock2[i].val,
  111. pfc_base | pfc_with_unlock2[i].off);
  112. }
  113. }
  114. static void spl_init_gpio(void)
  115. {
  116. static const u16 gpio_offs[] = {
  117. 0x1000, 0x2000, 0x3000, 0x4000, 0x5000
  118. };
  119. static const struct reg_config gpio_set[] = {
  120. { 0x2000, 0x24000000 },
  121. { 0x4000, 0xa4000000 },
  122. { 0x5000, 0x0004c000 },
  123. };
  124. static const struct reg_config gpio_clr[] = {
  125. { 0x1000, 0x01000000 },
  126. { 0x2000, 0x24000000 },
  127. { 0x3000, 0x00000000 },
  128. { 0x4000, 0xa4000000 },
  129. { 0x5000, 0x0084c380 },
  130. };
  131. static const u32 gpio_base = 0xe6050000;
  132. unsigned int i;
  133. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  134. writel(0, gpio_base | 0x20 | gpio_offs[i]);
  135. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  136. writel(0, gpio_base | 0x00 | gpio_offs[i]);
  137. for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
  138. writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
  139. for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
  140. writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
  141. }
  142. static void spl_init_lbsc(void)
  143. {
  144. static const struct reg_config lbsc_config[] = {
  145. { 0x00, 0x00000020 },
  146. { 0x08, 0x00002020 },
  147. { 0x30, 0x2a103320 },
  148. { 0x38, 0xff70ff70 },
  149. };
  150. static const u16 lbsc_offs[] = {
  151. 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
  152. };
  153. static const u32 lbsc_base = 0xfec00200;
  154. unsigned int i;
  155. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  156. writel(lbsc_config[i].val,
  157. lbsc_base | lbsc_config[i].off);
  158. writel(lbsc_config[i].val,
  159. lbsc_base | (lbsc_config[i].off + 4));
  160. }
  161. for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
  162. writel(0, lbsc_base | lbsc_offs[i]);
  163. }
  164. static void spl_init_dbsc(void)
  165. {
  166. static const struct reg_config dbsc_config1[] = {
  167. { 0x0018, 0x21000000 },
  168. { 0x0018, 0x11000000 },
  169. { 0x0018, 0x10000000 },
  170. { 0x0280, 0x0000a55a },
  171. { 0x0290, 0x00000001 },
  172. { 0x02a0, 0x80000000 },
  173. { 0x0290, 0x00000004 },
  174. };
  175. static const struct reg_config dbsc_config2[] = {
  176. { 0x0290, 0x00000006 },
  177. { 0x02a0, 0x0005c000 },
  178. };
  179. static const struct reg_config dbsc_config4[] = {
  180. { 0x0290, 0x00000010 },
  181. { 0x02a0, 0xf00464db },
  182. { 0x0290, 0x00000061 },
  183. { 0x02a0, 0x0000006d },
  184. { 0x0290, 0x00000001 },
  185. { 0x02a0, 0x00000073 },
  186. { 0x0020, 0x00000007 },
  187. { 0x0024, 0x0f030a02 },
  188. { 0x0030, 0x00000001 },
  189. { 0x00b0, 0x00000000 },
  190. { 0x0040, 0x00000009 },
  191. { 0x0044, 0x00000007 },
  192. { 0x0048, 0x00000000 },
  193. { 0x0050, 0x00000009 },
  194. { 0x0054, 0x000a0009 },
  195. { 0x0058, 0x00000021 },
  196. { 0x005c, 0x00000018 },
  197. { 0x0060, 0x00000005 },
  198. { 0x0064, 0x0000001b },
  199. { 0x0068, 0x00000007 },
  200. { 0x006c, 0x0000000a },
  201. { 0x0070, 0x00000009 },
  202. { 0x0074, 0x00000010 },
  203. { 0x0078, 0x000000ae },
  204. { 0x007c, 0x00140005 },
  205. { 0x0080, 0x00050004 },
  206. { 0x0084, 0x50213005 },
  207. { 0x0088, 0x000c0000 },
  208. { 0x008c, 0x00000200 },
  209. { 0x0090, 0x00000040 },
  210. { 0x0100, 0x00000001 },
  211. { 0x00c0, 0x00020001 },
  212. { 0x00c8, 0x20082008 },
  213. { 0x0380, 0x00020003 },
  214. { 0x0390, 0x0000001f },
  215. };
  216. static const struct reg_config dbsc_config5[] = {
  217. { 0x0244, 0x00000011 },
  218. { 0x0290, 0x00000003 },
  219. { 0x02a0, 0x0300c4e1 },
  220. { 0x0290, 0x00000023 },
  221. { 0x02a0, 0x00fcb6d0 },
  222. { 0x0290, 0x00000011 },
  223. { 0x02a0, 0x1000040b },
  224. { 0x0290, 0x00000012 },
  225. { 0x02a0, 0x85589955 },
  226. { 0x0290, 0x00000013 },
  227. { 0x02a0, 0x1a852400 },
  228. { 0x0290, 0x00000014 },
  229. { 0x02a0, 0x300210b4 },
  230. { 0x0290, 0x00000015 },
  231. { 0x02a0, 0x00000b50 },
  232. { 0x0290, 0x00000016 },
  233. { 0x02a0, 0x00000006 },
  234. { 0x0290, 0x00000017 },
  235. { 0x02a0, 0x00000010 },
  236. { 0x0290, 0x0000001a },
  237. { 0x02a0, 0x910035c7 },
  238. { 0x0290, 0x00000004 },
  239. };
  240. static const struct reg_config dbsc_config6[] = {
  241. { 0x0290, 0x00000001 },
  242. { 0x02a0, 0x00000181 },
  243. { 0x0018, 0x11000000 },
  244. { 0x0290, 0x00000004 },
  245. };
  246. static const struct reg_config dbsc_config7[] = {
  247. { 0x0290, 0x00000001 },
  248. { 0x02a0, 0x0000fe01 },
  249. { 0x0304, 0x00000000 },
  250. { 0x00f4, 0x01004c20 },
  251. { 0x00f8, 0x014000aa },
  252. { 0x00e0, 0x00000140 },
  253. { 0x00e4, 0x00081450 },
  254. { 0x00e8, 0x00010000 },
  255. { 0x0290, 0x00000004 },
  256. };
  257. static const struct reg_config dbsc_config8[] = {
  258. { 0x0014, 0x00000001 },
  259. { 0x0010, 0x00000001 },
  260. { 0x0280, 0x00000000 },
  261. };
  262. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  263. unsigned int i;
  264. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
  265. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  266. dbsc_wait(0x2a0);
  267. for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
  268. writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
  269. for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
  270. writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
  271. dbsc_wait(0x240);
  272. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
  273. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  274. dbsc_wait(0x2a0);
  275. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
  276. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  277. dbsc_wait(0x2a0);
  278. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
  279. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  280. dbsc_wait(0x2a0);
  281. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
  282. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  283. }
  284. static void spl_init_qspi(void)
  285. {
  286. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  287. static const u32 qspi_base = 0xe6b10000;
  288. writeb(0x08, qspi_base + 0x00);
  289. writeb(0x00, qspi_base + 0x01);
  290. writeb(0x06, qspi_base + 0x02);
  291. writeb(0x01, qspi_base + 0x0a);
  292. writeb(0x00, qspi_base + 0x0b);
  293. writeb(0x00, qspi_base + 0x0c);
  294. writeb(0x00, qspi_base + 0x0d);
  295. writeb(0x00, qspi_base + 0x0e);
  296. writew(0xe080, qspi_base + 0x10);
  297. writeb(0xc0, qspi_base + 0x18);
  298. writeb(0x00, qspi_base + 0x18);
  299. writeb(0x00, qspi_base + 0x08);
  300. writeb(0x48, qspi_base + 0x00);
  301. }
  302. void board_init_f(ulong dummy)
  303. {
  304. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  305. mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  306. /* Set SD1 to the 97.5MHz */
  307. writel(SD_97500KHZ, SD1CKCR);
  308. spl_init_sys();
  309. spl_init_pfc();
  310. spl_init_gpio();
  311. spl_init_lbsc();
  312. spl_init_dbsc();
  313. spl_init_qspi();
  314. }
  315. void spl_board_init(void)
  316. {
  317. /* UART clocks enabled and gd valid - init serial console */
  318. preloader_console_init();
  319. }
  320. void board_boot_order(u32 *spl_boot_list)
  321. {
  322. const u32 jtag_magic = 0x1337c0de;
  323. const u32 load_magic = 0xb33fc0de;
  324. /*
  325. * If JTAG probe sets special word at 0xe6300020, then it must
  326. * put U-Boot into RAM and SPL will start it from RAM.
  327. */
  328. if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
  329. printf("JTAG boot detected!\n");
  330. while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
  331. ;
  332. spl_boot_list[0] = BOOT_DEVICE_RAM;
  333. spl_boot_list[1] = BOOT_DEVICE_NONE;
  334. return;
  335. }
  336. /* Boot from SPI NOR with YMODEM UART fallback. */
  337. spl_boot_list[0] = BOOT_DEVICE_SPI;
  338. spl_boot_list[1] = BOOT_DEVICE_UART;
  339. spl_boot_list[2] = BOOT_DEVICE_NONE;
  340. }
  341. void reset_cpu(void)
  342. {
  343. }