alt.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/alt/alt.c
  4. *
  5. * Copyright (C) 2014, 2015 Renesas Electronics Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <hang.h>
  11. #include <init.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <asm/global_data.h>
  15. #include <dm/platform_data/serial_sh.h>
  16. #include <env_internal.h>
  17. #include <asm/processor.h>
  18. #include <asm/mach-types.h>
  19. #include <asm/io.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/errno.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/gpio.h>
  25. #include <asm/arch/rmobile.h>
  26. #include <asm/arch/rcar-mstp.h>
  27. #include <asm/arch/mmc.h>
  28. #include <asm/arch/sh_sdhi.h>
  29. #include <netdev.h>
  30. #include <miiphy.h>
  31. #include <i2c.h>
  32. #include <div64.h>
  33. #include "qos.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. void s_init(void)
  36. {
  37. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  38. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  39. /* Watchdog init */
  40. writel(0xA5A5A500, &rwdt->rwtcsra);
  41. writel(0xA5A5A500, &swdt->swtcsra);
  42. /* QoS */
  43. qos_init();
  44. }
  45. #define TMU0_MSTP125 BIT(25)
  46. #define MMC0_MSTP315 BIT(15)
  47. #define SD1CKCR 0xE6150078
  48. #define SD_97500KHZ 0x7
  49. int board_early_init_f(void)
  50. {
  51. /* TMU */
  52. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  53. /* Set SD1 to the 97.5MHz */
  54. writel(SD_97500KHZ, SD1CKCR);
  55. return 0;
  56. }
  57. #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
  58. int board_init(void)
  59. {
  60. /* adress of boot parameters */
  61. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  62. /* Force ethernet PHY out of reset */
  63. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  64. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  65. mdelay(20);
  66. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  67. udelay(1);
  68. return 0;
  69. }
  70. int dram_init(void)
  71. {
  72. if (fdtdec_setup_mem_size_base() != 0)
  73. return -EINVAL;
  74. return 0;
  75. }
  76. int dram_init_banksize(void)
  77. {
  78. fdtdec_setup_memory_banksize();
  79. return 0;
  80. }
  81. /* KSZ8041RNLI */
  82. #define PHY_CONTROL1 0x1E
  83. #define PHY_LED_MODE 0xC000
  84. #define PHY_LED_MODE_ACK 0x4000
  85. int board_phy_config(struct phy_device *phydev)
  86. {
  87. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  88. ret &= ~PHY_LED_MODE;
  89. ret |= PHY_LED_MODE_ACK;
  90. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  91. return 0;
  92. }
  93. void reset_cpu(void)
  94. {
  95. struct udevice *dev;
  96. const u8 pmic_bus = 7;
  97. const u8 pmic_addr = 0x58;
  98. u8 data;
  99. int ret;
  100. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  101. if (ret)
  102. hang();
  103. ret = dm_i2c_read(dev, 0x13, &data, 1);
  104. if (ret)
  105. hang();
  106. data |= BIT(1);
  107. ret = dm_i2c_write(dev, 0x13, &data, 1);
  108. if (ret)
  109. hang();
  110. }
  111. enum env_location env_get_location(enum env_operation op, int prio)
  112. {
  113. const u32 load_magic = 0xb33fc0de;
  114. /* Block environment access if loaded using JTAG */
  115. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  116. (op != ENVOP_INIT))
  117. return ENVL_UNKNOWN;
  118. if (prio)
  119. return ENVL_UNKNOWN;
  120. return ENVL_SPI_FLASH;
  121. }