spl.c 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <serial.h>
  13. #include <spl.h>
  14. #include <asm/global_data.h>
  15. #include <linux/delay.h>
  16. #include <linux/libfdt.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/mx6-ddr.h>
  20. #include <asm/arch/mx6-pins.h>
  21. #include "asm/arch/crm_regs.h"
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include "asm/arch/iomux.h"
  25. #include <asm/mach-imx/iomux-v3.h>
  26. #include <asm/gpio.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <netdev.h>
  29. #include <bootcount.h>
  30. #include <watchdog.h>
  31. #include "common.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  34. .dram_sdclk_0 = 0x00000030,
  35. .dram_sdclk_1 = 0x00000030,
  36. .dram_cas = 0x00000030,
  37. .dram_ras = 0x00000030,
  38. .dram_reset = 0x00000030,
  39. .dram_sdcke0 = 0x00003000,
  40. .dram_sdcke1 = 0x00003000,
  41. .dram_sdba2 = 0x00000000,
  42. .dram_sdodt0 = 0x00000030,
  43. .dram_sdodt1 = 0x00000030,
  44. .dram_sdqs0 = 0x00000030,
  45. .dram_sdqs1 = 0x00000030,
  46. .dram_sdqs2 = 0x00000030,
  47. .dram_sdqs3 = 0x00000030,
  48. .dram_sdqs4 = 0x00000030,
  49. .dram_sdqs5 = 0x00000030,
  50. .dram_sdqs6 = 0x00000030,
  51. .dram_sdqs7 = 0x00000030,
  52. .dram_dqm0 = 0x00000030,
  53. .dram_dqm1 = 0x00000030,
  54. .dram_dqm2 = 0x00000030,
  55. .dram_dqm3 = 0x00000030,
  56. .dram_dqm4 = 0x00000030,
  57. .dram_dqm5 = 0x00000030,
  58. .dram_dqm6 = 0x00000030,
  59. .dram_dqm7 = 0x00000030,
  60. };
  61. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  62. .grp_ddr_type = 0x000c0000,
  63. .grp_ddrmode_ctl = 0x00020000,
  64. .grp_ddrpke = 0x00000000,
  65. .grp_addds = 0x00000030,
  66. .grp_ctlds = 0x00000030,
  67. .grp_ddrmode = 0x00020000,
  68. .grp_b0ds = 0x00000030,
  69. .grp_b1ds = 0x00000030,
  70. .grp_b2ds = 0x00000030,
  71. .grp_b3ds = 0x00000030,
  72. .grp_b4ds = 0x00000030,
  73. .grp_b5ds = 0x00000030,
  74. .grp_b6ds = 0x00000030,
  75. .grp_b7ds = 0x00000030,
  76. };
  77. /* 4x128Mx16.cfg */
  78. static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  79. .p0_mpwldectrl0 = 0x002D0028,
  80. .p0_mpwldectrl1 = 0x0032002D,
  81. .p1_mpwldectrl0 = 0x00210036,
  82. .p1_mpwldectrl1 = 0x0019002E,
  83. .p0_mpdgctrl0 = 0x4349035C,
  84. .p0_mpdgctrl1 = 0x0348033D,
  85. .p1_mpdgctrl0 = 0x43550362,
  86. .p1_mpdgctrl1 = 0x03520316,
  87. .p0_mprddlctl = 0x41393940,
  88. .p1_mprddlctl = 0x3F3A3C47,
  89. .p0_mpwrdlctl = 0x413A423A,
  90. .p1_mpwrdlctl = 0x4042483E,
  91. };
  92. /* MT41K128M16JT-125 (2Gb density) */
  93. static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  94. .mem_speed = 1600,
  95. .density = 2,
  96. .width = 16,
  97. .banks = 8,
  98. .rowaddr = 14,
  99. .coladdr = 10,
  100. .pagesz = 2,
  101. .trcd = 1375,
  102. .trcmin = 4875,
  103. .trasmin = 3500,
  104. };
  105. iomux_v3_cfg_t const uart_console_pads[] = {
  106. /* UART5 */
  107. MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  108. MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  109. MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  110. MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  111. };
  112. void displ5_set_iomux_uart_spl(void)
  113. {
  114. SETUP_IOMUX_PADS(uart_console_pads);
  115. }
  116. iomux_v3_cfg_t const misc_pads_spl[] = {
  117. /* Emergency recovery pin */
  118. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  119. };
  120. void displ5_set_iomux_misc_spl(void)
  121. {
  122. SETUP_IOMUX_PADS(misc_pads_spl);
  123. }
  124. #ifdef CONFIG_MXC_SPI
  125. iomux_v3_cfg_t const ecspi2_pads[] = {
  126. /* SPI2, NOR Flash nWP, CS0 */
  127. MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  128. MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  129. MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  130. MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  132. };
  133. int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
  134. {
  135. if (bus != 1 || cs != 0)
  136. return -EINVAL;
  137. return IMX_GPIO_NR(5, 29);
  138. }
  139. void displ5_set_iomux_ecspi_spl(void)
  140. {
  141. SETUP_IOMUX_PADS(ecspi2_pads);
  142. }
  143. #else
  144. void displ5_set_iomux_ecspi_spl(void) {}
  145. #endif
  146. #ifdef CONFIG_FSL_ESDHC_IMX
  147. iomux_v3_cfg_t const usdhc4_pads[] = {
  148. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  154. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  155. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  156. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  157. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  158. MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  159. };
  160. void displ5_set_iomux_usdhc_spl(void)
  161. {
  162. SETUP_IOMUX_PADS(usdhc4_pads);
  163. }
  164. #else
  165. void displ5_set_iomux_usdhc_spl(void) {}
  166. #endif
  167. static void ccgr_init(void)
  168. {
  169. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  170. writel(0x00C03F3F, &ccm->CCGR0);
  171. writel(0x0030FC3F, &ccm->CCGR1);
  172. writel(0x0FFFCFC0, &ccm->CCGR2);
  173. writel(0x3FF00000, &ccm->CCGR3);
  174. writel(0x00FFF300, &ccm->CCGR4);
  175. writel(0x0F0000C3, &ccm->CCGR5);
  176. writel(0x000003FF, &ccm->CCGR6);
  177. }
  178. #ifdef CONFIG_MX6_DDRCAL
  179. static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
  180. {
  181. struct mx6_mmdc_calibration calibration = {0};
  182. mmdc_read_calibration(sysinfo, &calibration);
  183. debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
  184. debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
  185. debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
  186. debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
  187. debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
  188. debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
  189. debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
  190. debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
  191. debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
  192. debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
  193. debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
  194. debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
  195. }
  196. static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  197. {
  198. int ret;
  199. /* Perform DDR DRAM calibration */
  200. udelay(100);
  201. ret = mmdc_do_write_level_calibration(sysinfo);
  202. if (ret) {
  203. printf("DDR: Write level calibration error [%d]\n", ret);
  204. return;
  205. }
  206. ret = mmdc_do_dqs_calibration(sysinfo);
  207. if (ret) {
  208. printf("DDR: DQS calibration error [%d]\n", ret);
  209. return;
  210. }
  211. spl_dram_print_cal(sysinfo);
  212. }
  213. #endif /* CONFIG_MX6_DDRCAL */
  214. static void spl_dram_init(void)
  215. {
  216. struct mx6_ddr_sysinfo sysinfo = {
  217. /* width of data bus:0=16,1=32,2=64 */
  218. .dsize = 2,
  219. /* config for full 4GB range so that get_mem_size() works */
  220. .cs_density = 32, /* 32Gb per CS */
  221. /* single chip select */
  222. .ncs = 1,
  223. .cs1_mirror = 0,
  224. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  225. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  226. .walat = 1, /* Write additional latency */
  227. .ralat = 5, /* Read additional latency */
  228. .mif3_mode = 3, /* Command prediction working mode */
  229. .bi_on = 1, /* Bank interleaving enabled */
  230. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  231. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  232. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  233. .ddr_type = DDR_TYPE_DDR3,
  234. .refsel = 1, /* Refresh cycles at 32KHz */
  235. .refr = 7, /* 8 refresh commands per refresh cycle */
  236. };
  237. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  238. mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
  239. #ifdef CONFIG_MX6_DDRCAL
  240. spl_dram_perform_cal(&sysinfo);
  241. #endif
  242. }
  243. #ifdef CONFIG_SPL_SPI_SUPPORT
  244. static void displ5_init_ecspi(void)
  245. {
  246. displ5_set_iomux_ecspi_spl();
  247. enable_spi_clk(1, 1);
  248. }
  249. #else
  250. static inline void displ5_init_ecspi(void) { }
  251. #endif
  252. #ifdef CONFIG_SPL_MMC_SUPPORT
  253. static struct fsl_esdhc_cfg usdhc_cfg = {
  254. .esdhc_base = USDHC4_BASE_ADDR,
  255. .max_bus_width = 8,
  256. };
  257. int board_mmc_init(struct bd_info *bd)
  258. {
  259. displ5_set_iomux_usdhc_spl();
  260. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  261. gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
  262. return fsl_esdhc_initialize(bd, &usdhc_cfg);
  263. }
  264. #endif
  265. void board_init_f(ulong dummy)
  266. {
  267. ccgr_init();
  268. arch_cpu_init();
  269. gpr_init();
  270. /* setup GP timer */
  271. timer_init();
  272. displ5_set_iomux_uart_spl();
  273. /* UART clocks enabled and gd valid - init serial console */
  274. preloader_console_init();
  275. displ5_init_ecspi();
  276. /* DDR initialization */
  277. spl_dram_init();
  278. /* Clear the BSS. */
  279. memset(__bss_start, 0, __bss_end - __bss_start);
  280. displ5_set_iomux_misc_spl();
  281. /* Initialize and reset WDT in SPL */
  282. hw_watchdog_init();
  283. WATCHDOG_RESET();
  284. /* load/boot image from boot device */
  285. board_init_r(NULL, 0);
  286. }
  287. #define EM_PAD IMX_GPIO_NR(3, 29)
  288. int board_check_emergency_pad(void)
  289. {
  290. int ret;
  291. ret = gpio_direction_input(EM_PAD);
  292. if (ret)
  293. return ret;
  294. return !gpio_get_value(EM_PAD);
  295. }
  296. void board_boot_order(u32 *spl_boot_list)
  297. {
  298. /* Default boot sequence SPI -> MMC */
  299. spl_boot_list[0] = spl_boot_device();
  300. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  301. spl_boot_list[2] = BOOT_DEVICE_UART;
  302. spl_boot_list[3] = BOOT_DEVICE_NONE;
  303. /*
  304. * In case of emergency PAD pressed, we always boot
  305. * to proper u-boot and perform recovery tasks there.
  306. */
  307. if (board_check_emergency_pad())
  308. return;
  309. #ifdef CONFIG_SPL_ENV_SUPPORT
  310. /* 'fastboot' */
  311. const char *s;
  312. if (env_init() || env_load())
  313. return;
  314. s = env_get("BOOT_FROM");
  315. if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
  316. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  317. spl_boot_list[1] = spl_boot_device();
  318. }
  319. #endif
  320. }
  321. void reset_cpu(void) {}
  322. #ifdef CONFIG_SPL_LOAD_FIT
  323. int board_fit_config_name_match(const char *name)
  324. {
  325. return 0;
  326. }
  327. #endif
  328. #ifdef CONFIG_SPL_OS_BOOT
  329. /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
  330. int spl_start_uboot(void)
  331. {
  332. /* break into full u-boot on 'c' */
  333. if (serial_tstc() && serial_getc() == 'c')
  334. return 1;
  335. #ifdef CONFIG_SPL_ENV_SUPPORT
  336. if (env_get_yesno("boot_os") != 1)
  337. return 1;
  338. #endif
  339. return 0;
  340. }
  341. #endif