kzm9g.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  4. * (C) Copyright 2012 Renesas Solutions Corp.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <netdev.h>
  15. #include <i2c.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define CS0BCR_D (0x06C00400)
  18. #define CS4BCR_D (0x16c90400)
  19. #define CS0WCR_D (0x55062C42)
  20. #define CS4WCR_D (0x1e071dc3)
  21. #define CMNCR_BROMMD0 (1 << 21)
  22. #define CMNCR_BROMMD1 (1 << 22)
  23. #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
  24. #define VCLKCR1_D (0x27)
  25. #define SMSTPCR1_CMT0 (1 << 24)
  26. #define SMSTPCR1_I2C0 (1 << 16)
  27. #define SMSTPCR3_USB (1 << 22)
  28. #define SMSTPCR3_I2C1 (1 << 23)
  29. #define PORT32CR (0xE6051020)
  30. #define PORT33CR (0xE6051021)
  31. #define PORT34CR (0xE6051022)
  32. #define PORT35CR (0xE6051023)
  33. static int cmp_loop(u32 *addr, u32 data, u32 cmp)
  34. {
  35. int err = -1;
  36. int timeout = 100;
  37. u32 value;
  38. while (timeout > 0) {
  39. value = readl(addr);
  40. if ((value & data) == cmp) {
  41. err = 0;
  42. break;
  43. }
  44. timeout--;
  45. }
  46. return err;
  47. }
  48. /* SBSC Init function */
  49. static void sbsc_init(struct sh73a0_sbsc *sbsc)
  50. {
  51. writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
  52. writel(0x5, &sbsc->sdgencnt);
  53. cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  54. writel(0xacc90159, &sbsc->sdcr0);
  55. writel(0x00010059, &sbsc->sdcr1);
  56. writel(0x50874114, &sbsc->sdwcrc0);
  57. writel(0x33199b37, &sbsc->sdwcrc1);
  58. writel(0x008f2313, &sbsc->sdwcrc2);
  59. writel(0x31020707, &sbsc->sdwcr00);
  60. writel(0x0017040a, &sbsc->sdwcr01);
  61. writel(0x31020707, &sbsc->sdwcr10);
  62. writel(0x0017040a, &sbsc->sdwcr11);
  63. writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
  64. writel(0x30000000, &sbsc->sdwcr2);
  65. writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
  66. cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
  67. writel(0x00002710, &sbsc->sdgencnt);
  68. cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  69. writel(0x0000003f, &sbsc->sdmracr0);
  70. writel(0x0, SDMRA1A);
  71. writel(0x000001f4, &sbsc->sdgencnt);
  72. cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  73. writel(0x0000ff0a, &sbsc->sdmracr0);
  74. if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
  75. writel(0x0, SDMRA3A);
  76. else
  77. writel(0x0, SDMRA3B);
  78. writel(0x00000032, &sbsc->sdgencnt);
  79. cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  80. if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
  81. writel(0x00002201, &sbsc->sdmracr0);
  82. writel(0x0, SDMRA1A);
  83. writel(0x00000402, &sbsc->sdmracr0);
  84. writel(0x0, SDMRA1A);
  85. writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
  86. writel(0x0, SDMRA1A);
  87. writel(0x0, SDMRA2A);
  88. } else {
  89. writel(0x00002201, &sbsc->sdmracr0);
  90. writel(0x0, SDMRA1B);
  91. writel(0x00000402, &sbsc->sdmracr0);
  92. writel(0x0, SDMRA1B);
  93. writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
  94. writel(0x0, SDMRA1B);
  95. writel(0x0, SDMRA2B);
  96. }
  97. writel(0x88800004, &sbsc->sdmrtmpcr);
  98. writel(0x00000004, &sbsc->sdmrtmpmsk);
  99. writel(0xa55a0032, &sbsc->rtcor);
  100. writel(0xa55a000c, &sbsc->rtcorh);
  101. writel(0xa55a2048, &sbsc->rtcsr);
  102. writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
  103. writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
  104. writel(0xfff20000, &sbsc->zqccr);
  105. /* SCBS2 only */
  106. if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
  107. writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
  108. writel(0xa5390000, &sbsc->dphycnt1);
  109. writel(0x00001200, &sbsc->dphycnt0);
  110. writel(0x07ce0000, &sbsc->dphycnt1);
  111. writel(0x00001247, &sbsc->dphycnt0);
  112. cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
  113. writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
  114. }
  115. }
  116. void s_init(void)
  117. {
  118. struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
  119. struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
  120. struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
  121. (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
  122. struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
  123. struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
  124. struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
  125. struct sh73a0_hpb_bscr *hpb_bscr =
  126. (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
  127. /* Watchdog init */
  128. writew(0xA507, &rwdt->rwtcsra0);
  129. /* Secure control register Init */
  130. #define LIFEC_SEC_SRC_BIT (1 << 15)
  131. writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
  132. clrbits_le32(&cpg->smstpcr3, (1 << 15));
  133. clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
  134. clrbits_le32(&cpg->smstpcr2, (1 << 18));
  135. clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
  136. writel(0x0, &cpg->pllecr);
  137. cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
  138. cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
  139. writel(0x2D000000, &cpg->pll0cr);
  140. writel(0x17100000, &cpg->pll1cr);
  141. writel(0x96235880, &cpg->frqcrb);
  142. cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
  143. writel(0xB, &cpg->flckcr);
  144. clrbits_le32(&cpg->smstpcr0, (1 << 1));
  145. clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
  146. writel(0x0514, &hpb_bscr->smgpiotime);
  147. writel(0x0514, &hpb_bscr->smcmt2time);
  148. writel(0x0514, &hpb_bscr->smcpgtime);
  149. writel(0x0514, &hpb_bscr->smsysctime);
  150. writel(0x00092000, &cpg->dvfscr4);
  151. writel(0x000000DC, &cpg->dvfscr5);
  152. writel(0x0, &cpg->pllecr);
  153. cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
  154. /* FRQCR Init */
  155. writel(0x0012453C, &cpg->frqcra);
  156. writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */
  157. cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
  158. writel(0x00000B0B, &cpg->frqcrd);
  159. cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
  160. /* Clock Init */
  161. writel(0x00000003, PCLKCR);
  162. writel(0x0000012F, &cpg->vclkcr1);
  163. writel(0x00000119, &cpg->vclkcr2);
  164. writel(0x00000119, &cpg->vclkcr3);
  165. writel(0x00000002, &cpg->zbckcr);
  166. writel(0x00000005, &cpg->flckcr);
  167. writel(0x00000080, &cpg->sd0ckcr);
  168. writel(0x00000080, &cpg->sd1ckcr);
  169. writel(0x00000080, &cpg->sd2ckcr);
  170. writel(0x0000003F, &cpg->fsiackcr);
  171. writel(0x0000003F, &cpg->fsibckcr);
  172. writel(0x00000080, &cpg->subckcr);
  173. writel(0x0000000B, &cpg->spuackcr);
  174. writel(0x0000000B, &cpg->spuvckcr);
  175. writel(0x0000013F, &cpg->msuckcr);
  176. writel(0x00000080, &cpg->hsickcr);
  177. writel(0x0000003F, &cpg->mfck1cr);
  178. writel(0x0000003F, &cpg->mfck2cr);
  179. writel(0x00000107, &cpg->dsitckcr);
  180. writel(0x00000313, &cpg->dsi0pckcr);
  181. writel(0x0000130D, &cpg->dsi1pckcr);
  182. writel(0x2A800E0E, &cpg->dsi0phycr);
  183. writel(0x1E000000, &cpg->pll0cr);
  184. writel(0x2D000000, &cpg->pll0cr);
  185. writel(0x17100000, &cpg->pll1cr);
  186. writel(0x27000080, &cpg->pll2cr);
  187. writel(0x1D000000, &cpg->pll3cr);
  188. writel(0x00080000, &cpg->pll0stpcr);
  189. writel(0x000120C0, &cpg->pll1stpcr);
  190. writel(0x00012000, &cpg->pll2stpcr);
  191. writel(0x00000030, &cpg->pll3stpcr);
  192. writel(0x0000000B, &cpg->pllecr);
  193. cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
  194. writel(0x000120F0, &cpg->dvfscr3);
  195. writel(0x00000020, &cpg->mpmode);
  196. writel(0x0000028A, &cpg->vrefcr);
  197. writel(0xE4628087, &cpg->rmstpcr0);
  198. writel(0xFFFFFFFF, &cpg->rmstpcr1);
  199. writel(0x53FFFFFF, &cpg->rmstpcr2);
  200. writel(0xFFFFFFFF, &cpg->rmstpcr3);
  201. writel(0x00800D3D, &cpg->rmstpcr4);
  202. writel(0xFFFFF3FF, &cpg->rmstpcr5);
  203. writel(0x00000000, &cpg->smstpcr2);
  204. writel(0x00040000, &cpg_srcr->srcr2);
  205. clrbits_le32(&cpg->pllecr, (1 << 3));
  206. cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
  207. writel(0x00000001, &hpb->hpbctrl6);
  208. cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
  209. writel(0x00001414, &cpg->frqcrd);
  210. cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
  211. writel(0x1d000000, &cpg->pll3cr);
  212. setbits_le32(&cpg->pllecr, (1 << 3));
  213. cmp_loop(&cpg->pllecr, 0x800, 0x800);
  214. /* SBSC1 Init*/
  215. sbsc_init(sbsc1);
  216. /* SBSC2 Init*/
  217. sbsc_init(sbsc2);
  218. writel(0x00000b0b, &cpg->frqcrd);
  219. cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
  220. writel(0xfffffffc, &cpg->cpgxxcs4);
  221. }
  222. int board_early_init_f(void)
  223. {
  224. struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
  225. struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
  226. struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
  227. (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
  228. writel(CS0BCR_D, &bsc->cs0bcr);
  229. writel(CS4BCR_D, &bsc->cs4bcr);
  230. writel(CS0WCR_D, &bsc->cs0wcr);
  231. writel(CS4WCR_D, &bsc->cs4wcr);
  232. clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
  233. clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
  234. clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
  235. clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
  236. clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
  237. writel(VCLKCR1_D, &cpg->vclkcr1);
  238. /* Setup SCIF4 / workaround */
  239. writeb(0x12, PORT32CR);
  240. writeb(0x22, PORT33CR);
  241. writeb(0x12, PORT34CR);
  242. writeb(0x22, PORT35CR);
  243. return 0;
  244. }
  245. void adjust_core_voltage(void)
  246. {
  247. u8 data;
  248. data = 0x35;
  249. i2c_set_bus_num(0);
  250. i2c_write(0x40, 3, 1, &data, 1);
  251. }
  252. int board_init(void)
  253. {
  254. adjust_core_voltage();
  255. sh73a0_pinmux_init();
  256. /* SCIFA 4 */
  257. gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
  258. gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
  259. gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
  260. gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
  261. /* Ethernet/SMSC */
  262. gpio_request(GPIO_PORT224, NULL);
  263. gpio_direction_input(GPIO_PORT224);
  264. /* SMSC/USB */
  265. gpio_request(GPIO_FN_CS4_, NULL);
  266. /* MMCIF */
  267. gpio_request(GPIO_FN_MMCCLK0, NULL);
  268. gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
  269. gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
  270. gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
  271. gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
  272. gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
  273. gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
  274. gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
  275. gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
  276. gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
  277. /* SDHI */
  278. gpio_request(GPIO_FN_SDHIWP0, NULL);
  279. gpio_request(GPIO_FN_SDHICD0, NULL);
  280. gpio_request(GPIO_FN_SDHICMD0, NULL);
  281. gpio_request(GPIO_FN_SDHICLK0, NULL);
  282. gpio_request(GPIO_FN_SDHID0_3, NULL);
  283. gpio_request(GPIO_FN_SDHID0_2, NULL);
  284. gpio_request(GPIO_FN_SDHID0_1, NULL);
  285. gpio_request(GPIO_FN_SDHID0_0, NULL);
  286. gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
  287. gpio_request(GPIO_PORT15, NULL);
  288. gpio_direction_output(GPIO_PORT15, 1);
  289. /* I2C */
  290. gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
  291. gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
  292. gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
  293. gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
  294. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  295. return 0;
  296. }
  297. int dram_init(void)
  298. {
  299. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  300. return 0;
  301. }
  302. int board_eth_init(struct bd_info *bis)
  303. {
  304. int ret = 0;
  305. #ifdef CONFIG_SMC911X
  306. ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  307. #endif
  308. return ret;
  309. }
  310. void reset_cpu(void)
  311. {
  312. /* Soft Power On Reset */
  313. writel((1 << 31), RESCNT2);
  314. }