poplar.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017 Linaro
  4. * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <asm/cache.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <dm/platform_data/serial_pl01x.h>
  14. #include <asm/arch/hi3798cv200.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static struct mm_region poplar_mem_map[] = {
  20. {
  21. .virt = 0x0UL,
  22. .phys = 0x0UL,
  23. .size = 0x80000000UL,
  24. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25. PTE_BLOCK_INNER_SHARE
  26. }, {
  27. .virt = 0x80000000UL,
  28. .phys = 0x80000000UL,
  29. .size = 0x80000000UL,
  30. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  31. PTE_BLOCK_NON_SHARE |
  32. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  33. }, {
  34. 0,
  35. }
  36. };
  37. struct mm_region *mem_map = poplar_mem_map;
  38. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  39. static const struct pl01x_serial_plat serial_plat = {
  40. .base = REG_BASE_UART0,
  41. .type = TYPE_PL010,
  42. .clock = 75000000,
  43. };
  44. U_BOOT_DRVINFO(poplar_serial) = {
  45. .name = "serial_pl01x",
  46. .plat = &serial_plat,
  47. };
  48. #endif
  49. int checkboard(void)
  50. {
  51. puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
  52. return 0;
  53. }
  54. void reset_cpu(void)
  55. {
  56. psci_system_reset();
  57. }
  58. int dram_init(void)
  59. {
  60. gd->ram_size = get_ram_size(NULL, 0x80000000);
  61. return 0;
  62. }
  63. /*
  64. * Some linux kernel versions don't use memory before its load address, so to
  65. * be generic we just pretend it isn't there. In previous uboot versions we
  66. * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
  67. * could persist in memory and be left alone by the kernel.
  68. *
  69. * That led to a problem when mapping memory in older kernels. That PSCI code
  70. * now lies in memory below the kernel load offset; it therefore won't be
  71. * touched by the kernel, and by not specially reserving it we avoid the mapping
  72. * problem as well.
  73. *
  74. */
  75. #define KERNEL_TEXT_OFFSET 0x00080000
  76. int dram_init_banksize(void)
  77. {
  78. gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
  79. gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
  80. return 0;
  81. }
  82. static void usb2_phy_config(void)
  83. {
  84. const u32 config[] = {
  85. /* close EOP pre-emphasis. open data pre-emphasis */
  86. 0xa1001c,
  87. /* Rcomp = 150mW, increase DC level */
  88. 0xa00607,
  89. /* keep Rcomp working */
  90. 0xa10700,
  91. /* Icomp = 212mW, increase current drive */
  92. 0xa00aab,
  93. /* EMI fix: rx_active not stay 1 when error packets received */
  94. 0xa11140,
  95. /* Comp mode select */
  96. 0xa11041,
  97. /* adjust eye diagram */
  98. 0xa0098c,
  99. /* adjust eye diagram */
  100. 0xa10a0a,
  101. };
  102. int i;
  103. for (i = 0; i < ARRAY_SIZE(config); i++) {
  104. writel(config[i], PERI_CTRL_USB0);
  105. clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
  106. udelay(20);
  107. }
  108. }
  109. static void usb2_phy_init(void)
  110. {
  111. /* reset usb2 controller bus/utmi/roothub */
  112. setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  113. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  114. udelay(200);
  115. /* reset usb2 phy por/utmi */
  116. setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
  117. udelay(200);
  118. /* open usb2 ref clk */
  119. setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
  120. udelay(300);
  121. /* cancel usb2 power on reset */
  122. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
  123. udelay(500);
  124. usb2_phy_config();
  125. /* cancel usb2 port reset, wait comp circuit stable */
  126. clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
  127. mdelay(10);
  128. /* open usb2 controller clk */
  129. setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
  130. USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
  131. USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
  132. udelay(200);
  133. /* cancel usb2 control reset */
  134. clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
  135. USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
  136. udelay(200);
  137. }
  138. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  139. #include <env.h>
  140. #include <usb.h>
  141. #include <usb/dwc2_udc.h>
  142. #include <g_dnl.h>
  143. static struct dwc2_plat_otg_data poplar_otg_data = {
  144. .regs_otg = HIOTG_BASE_ADDR
  145. };
  146. static void set_usb_to_device(void)
  147. {
  148. setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID);
  149. }
  150. int board_usb_init(int index, enum usb_init_type init)
  151. {
  152. set_usb_to_device();
  153. return dwc2_udc_probe(&poplar_otg_data);
  154. }
  155. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  156. {
  157. if (!env_get("serial#"))
  158. g_dnl_set_serialnumber("0123456789POPLAR");
  159. return 0;
  160. }
  161. #endif
  162. int board_init(void)
  163. {
  164. usb2_phy_init();
  165. return 0;
  166. }