spl.c 16 KB

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  1. /*
  2. * GE b1x5v2 - QMX6 SPL
  3. *
  4. * Copyright 2013, Adeneo Embedded <www.adeneo-embedded.com>
  5. * Copyright 2018-2020 GE Inc.
  6. * Copyright 2018-2020 Collabora Ltd.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <init.h>
  18. #include <spi.h>
  19. #include <spi_flash.h>
  20. #include <spl.h>
  21. #if defined(CONFIG_SPL_BUILD)
  22. #include <asm/arch/mx6-ddr.h>
  23. #define IMX6DQ_DRIVE_STRENGTH_40_OHM 0x30
  24. #define IMX6DQ_DRIVE_STRENGTH_48_OHM 0x28
  25. #define IMX6DQ_DRIVE_STRENGTH IMX6DQ_DRIVE_STRENGTH_40_OHM
  26. #define QMX6_DDR_PKE_DISABLED 0x00000000
  27. #define QMX6_DDR_ODT_60_OHM (2 << 16)
  28. #define QMX6_DDR_TYPE_DDR3 0x000c0000
  29. #define QMX6_DRAM_SDCKE_PULLUP_100K 0x00003000
  30. #define QMX6_DRAM_SDBA2_PULLUP_NONE 0x00000000
  31. #define SPI_PAD_CTRL (PAD_CTL_HYS | \
  32. PAD_CTL_SPEED_MED | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  34. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  35. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define SPI1_CS0 IMX_GPIO_NR(3, 19)
  38. #define POWEROFF IMX_GPIO_NR(4, 25)
  39. static iomux_v3_cfg_t const poweroff_pads[] = {
  40. IOMUX_PADS(PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  41. };
  42. static iomux_v3_cfg_t const uart2_pads[] = {
  43. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  44. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  45. };
  46. static iomux_v3_cfg_t const uart3_pads[] = {
  47. IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  48. IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  49. };
  50. static iomux_v3_cfg_t const ecspi1_pads[] = {
  51. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  52. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  53. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  54. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  55. };
  56. static struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
  57. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  58. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  59. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  60. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  61. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  62. .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
  63. .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
  64. .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
  65. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  66. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  67. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  68. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  69. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  70. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  71. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  72. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  73. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  74. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  75. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  76. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  77. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  78. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  79. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  80. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  81. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  82. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  83. };
  84. static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
  85. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  86. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  87. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  88. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  89. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  90. .dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
  91. .dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
  92. .dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
  93. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  94. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  95. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  96. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  97. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  98. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  99. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  100. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  101. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  102. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  103. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  104. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  105. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  106. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  107. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  108. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  109. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  110. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  111. };
  112. static struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
  113. .grp_ddr_type = QMX6_DDR_TYPE_DDR3,
  114. .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
  115. .grp_ddrpke = QMX6_DDR_PKE_DISABLED,
  116. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  117. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  118. .grp_ddrmode = QMX6_DDR_ODT_60_OHM,
  119. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  120. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  121. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  122. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  123. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  124. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  125. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  126. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  127. };
  128. static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  129. .grp_ddr_type = QMX6_DDR_TYPE_DDR3,
  130. .grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
  131. .grp_ddrpke = QMX6_DDR_PKE_DISABLED,
  132. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  133. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  134. .grp_ddrmode = QMX6_DDR_ODT_60_OHM,
  135. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  136. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  137. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  138. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  139. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  140. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  141. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  142. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  143. };
  144. const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
  145. .p0_mpwldectrl0 = 0x0016001A,
  146. .p0_mpwldectrl1 = 0x0023001C,
  147. .p1_mpwldectrl0 = 0x0028003A,
  148. .p1_mpwldectrl1 = 0x001F002C,
  149. .p0_mpdgctrl0 = 0x43440354,
  150. .p0_mpdgctrl1 = 0x033C033C,
  151. .p1_mpdgctrl0 = 0x43300368,
  152. .p1_mpdgctrl1 = 0x03500330,
  153. .p0_mprddlctl = 0x3228242E,
  154. .p1_mprddlctl = 0x2C2C2636,
  155. .p0_mpwrdlctl = 0x36323A38,
  156. .p1_mpwrdlctl = 0x42324440,
  157. };
  158. const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
  159. .p0_mpwldectrl0 = 0x00080016,
  160. .p0_mpwldectrl1 = 0x001D0016,
  161. .p1_mpwldectrl0 = 0x0018002C,
  162. .p1_mpwldectrl1 = 0x000D001D,
  163. .p0_mpdgctrl0 = 0x43200334,
  164. .p0_mpdgctrl1 = 0x0320031C,
  165. .p1_mpdgctrl0 = 0x0344034C,
  166. .p1_mpdgctrl1 = 0x03380314,
  167. .p0_mprddlctl = 0x3E36383A,
  168. .p1_mprddlctl = 0x38363240,
  169. .p0_mpwrdlctl = 0x36364238,
  170. .p1_mpwrdlctl = 0x4230423E,
  171. };
  172. const struct mx6_mmdc_calibration mx6q_4g_mmcd_calib = {
  173. .p0_mpwldectrl0 = 0x00180018,
  174. .p0_mpwldectrl1 = 0x00220018,
  175. .p1_mpwldectrl0 = 0x00330046,
  176. .p1_mpwldectrl1 = 0x002B003D,
  177. .p0_mpdgctrl0 = 0x4344034C,
  178. .p0_mpdgctrl1 = 0x033C033C,
  179. .p1_mpdgctrl0 = 0x03700374,
  180. .p1_mpdgctrl1 = 0x03600338,
  181. .p0_mprddlctl = 0x443E3E40,
  182. .p1_mprddlctl = 0x423E3E48,
  183. .p0_mpwrdlctl = 0x3C3C4442,
  184. .p1_mpwrdlctl = 0x46384C46,
  185. };
  186. static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
  187. .p0_mpwldectrl0 = 0x00480049,
  188. .p0_mpwldectrl1 = 0x00410044,
  189. .p0_mpdgctrl0 = 0x42480248,
  190. .p0_mpdgctrl1 = 0x023C023C,
  191. .p0_mprddlctl = 0x40424644,
  192. .p0_mpwrdlctl = 0x34323034,
  193. };
  194. static const struct mx6_mmdc_calibration mx6s_2g_mmcd_calib = {
  195. .p0_mpwldectrl0 = 0x00450048,
  196. .p0_mpwldectrl1 = 0x003B003F,
  197. .p0_mpdgctrl0 = 0x424C0248,
  198. .p0_mpdgctrl1 = 0x0234023C,
  199. .p0_mprddlctl = 0x40444848,
  200. .p0_mpwrdlctl = 0x38363232,
  201. };
  202. static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
  203. .p0_mpwldectrl0 = 0x0043004B,
  204. .p0_mpwldectrl1 = 0x003A003E,
  205. .p1_mpwldectrl0 = 0x0047004F,
  206. .p1_mpwldectrl1 = 0x004E0061,
  207. .p0_mpdgctrl0 = 0x42500250,
  208. .p0_mpdgctrl1 = 0x0238023C,
  209. .p1_mpdgctrl0 = 0x42640264,
  210. .p1_mpdgctrl1 = 0x02500258,
  211. .p0_mprddlctl = 0x40424846,
  212. .p1_mprddlctl = 0x46484842,
  213. .p0_mpwrdlctl = 0x38382C30,
  214. .p1_mpwrdlctl = 0x34343430,
  215. };
  216. static const struct mx6_mmdc_calibration mx6dl_2g_mmcd_calib = {
  217. .p0_mpwldectrl0 = 0x00450045,
  218. .p0_mpwldectrl1 = 0x00390043,
  219. .p1_mpwldectrl0 = 0x0049004D,
  220. .p1_mpwldectrl1 = 0x004E0061,
  221. .p0_mpdgctrl0 = 0x4240023C,
  222. .p0_mpdgctrl1 = 0x0228022C,
  223. .p1_mpdgctrl0 = 0x02400244,
  224. .p1_mpdgctrl1 = 0x02340238,
  225. .p0_mprddlctl = 0x42464648,
  226. .p1_mprddlctl = 0x4446463C,
  227. .p0_mpwrdlctl = 0x3C38323A,
  228. .p1_mpwrdlctl = 0x34323430,
  229. };
  230. static struct mx6_ddr3_cfg mem_ddr_2g = {
  231. .mem_speed = 1600,
  232. .density = 2,
  233. .width = 16,
  234. .banks = 8,
  235. .rowaddr = 14,
  236. .coladdr = 10,
  237. .pagesz = 2,
  238. .trcd = 1310,
  239. .trcmin = 4875,
  240. .trasmin = 3500,
  241. };
  242. static struct mx6_ddr3_cfg mem_ddr_4g = {
  243. .mem_speed = 1600,
  244. .density = 4,
  245. .width = 16,
  246. .banks = 8,
  247. .rowaddr = 15,
  248. .coladdr = 10,
  249. .pagesz = 2,
  250. .trcd = 1310,
  251. .trcmin = 4875,
  252. .trasmin = 3500,
  253. };
  254. static struct mx6_ddr3_cfg mem_ddr_8g = {
  255. .mem_speed = 1600,
  256. .density = 8,
  257. .width = 16,
  258. .banks = 8,
  259. .rowaddr = 16,
  260. .coladdr = 10,
  261. .pagesz = 2,
  262. .trcd = 1310,
  263. .trcmin = 4875,
  264. .trasmin = 3500,
  265. };
  266. static void spl_dram_init(u8 width, u32 memsize) {
  267. struct mx6_ddr_sysinfo sysinfo = {
  268. /* width of data bus: 0=16, 1=32, 2=64 */
  269. .dsize = width / 32,
  270. /* config for full 4GB range so that get_mem_size() works */
  271. .cs_density = 32, /* 32Gb per CS */
  272. .ncs = 1,
  273. .cs1_mirror = 0,
  274. .rtt_wr = 2,
  275. .rtt_nom = 2,
  276. .walat = 0,
  277. .ralat = 5,
  278. .mif3_mode = 3,
  279. .bi_on = 1,
  280. .sde_to_rst = 0x0d,
  281. .rst_to_cke = 0x20,
  282. };
  283. if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  284. sysinfo.walat = 1;
  285. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  286. switch(memsize) {
  287. case 512:
  288. mx6_dram_cfg(&sysinfo, &mx6s_2g_mmcd_calib, &mem_ddr_2g);
  289. break;
  290. default:
  291. mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
  292. break;
  293. }
  294. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  295. sysinfo.walat = 1;
  296. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  297. switch(memsize) {
  298. case 2048:
  299. mx6_dram_cfg(&sysinfo, &mx6dl_2g_mmcd_calib, &mem_ddr_4g);
  300. break;
  301. default:
  302. mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
  303. break;
  304. }
  305. } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  306. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  307. switch(memsize) {
  308. case 4096:
  309. sysinfo.cs_density = 16;
  310. sysinfo.ncs = 2;
  311. mx6_dram_cfg(&sysinfo, &mx6q_4g_mmcd_calib, &mem_ddr_8g);
  312. break;
  313. case 2048:
  314. mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
  315. break;
  316. default:
  317. mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
  318. break;
  319. }
  320. }
  321. }
  322. /* Define a minimal structure so that the part number can be read via SPL */
  323. #define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
  324. struct mfgdata {
  325. unsigned char tsize;
  326. /* size of checksummed part in bytes */
  327. unsigned char ckcnt;
  328. /* checksum corrected byte */
  329. unsigned char cksum;
  330. /* decimal serial number, packed BCD */
  331. unsigned char serial[6];
  332. /* part number, right justified, ASCII */
  333. unsigned char pn[16];
  334. };
  335. static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
  336. {
  337. int remain = len;
  338. unsigned char *sptr = src;
  339. unsigned char *dptr = dst;
  340. while (remain) {
  341. if (*sptr) {
  342. *dptr = *sptr;
  343. dptr++;
  344. }
  345. sptr++;
  346. remain--;
  347. }
  348. *dptr = 0x0;
  349. }
  350. /*
  351. * Returns the total size of the memory [in MB] the board is equipped with
  352. *
  353. * This is determined via the partnumber which is stored in the
  354. * congatec manufacturing area
  355. */
  356. static int get_boardmem_size(struct spi_flash *spi)
  357. {
  358. int ret;
  359. int i;
  360. int arraysize;
  361. char buf[sizeof(struct mfgdata)];
  362. struct mfgdata *data = (struct mfgdata *)buf;
  363. unsigned char outbuf[32];
  364. char partnumbers_2g[4][7] = { "016104", "016105", "016304", "016305" };
  365. char partnumbers_4g[2][7] = { "016308", "016318" };
  366. char partnumbers_512m[2][7] = { "016203", "616300" };
  367. ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
  368. buf);
  369. if (ret)
  370. return 1024; /* default to 1GByte in case of error */
  371. conv_ascii(outbuf, data->pn, sizeof(data->pn));
  372. printf("Detected Congatec QMX6 SOM: %s\n", outbuf);
  373. /* congatec PN 016104, 016105, 016304, 016305 have 2GiB of RAM */
  374. arraysize = sizeof(partnumbers_2g) / sizeof(partnumbers_2g[0]);
  375. for (i=0; i < arraysize; i++) {
  376. if (!memcmp(outbuf,partnumbers_2g[i],6))
  377. return 2048;
  378. }
  379. /* congatec PN 016308, 016318 have 4GiB of RAM */
  380. arraysize = sizeof(partnumbers_4g) / sizeof(partnumbers_4g[0]);
  381. for (i=0; i < arraysize; i++) {
  382. if (!memcmp(outbuf,partnumbers_4g[i],6))
  383. return 4096;
  384. }
  385. /* congatec PN 016203, 616300 has 512MiB of RAM */
  386. arraysize = sizeof(partnumbers_512m) / sizeof(partnumbers_512m[0]);
  387. for (i=0; i < arraysize; i++) {
  388. if (!memcmp(outbuf,partnumbers_512m[i],6))
  389. return 512;
  390. }
  391. /* default to 1GByte */
  392. return 1024;
  393. }
  394. void reset_cpu(void)
  395. {
  396. }
  397. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  398. {
  399. if (bus == 0 && cs == 0)
  400. return (SPI1_CS0);
  401. else
  402. return -1;
  403. }
  404. static void memory_init(void) {
  405. struct spi_flash *spi;
  406. u8 width;
  407. u32 size;
  408. SETUP_IOMUX_PADS(ecspi1_pads);
  409. gpio_direction_output(SPI1_CS0, 0);
  410. spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
  411. CONFIG_ENV_SPI_CS,
  412. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  413. if (!spi)
  414. panic("Cannot identify board type: SPI-NOR flash module not detected\n");
  415. /* lock manufacturer area */
  416. spi_flash_protect(spi, CFG_MFG_ADDR_OFFSET, SZ_16K, true);
  417. width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64;
  418. size = get_boardmem_size(spi);
  419. printf("Detected Memory Size: %u\n", size);
  420. spl_dram_init(width, size);
  421. }
  422. static void ccgr_init(void)
  423. {
  424. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  425. static const uint32_t ccgr0 =
  426. MXC_CCM_CCGR0_AIPS_TZ1_MASK |
  427. MXC_CCM_CCGR0_AIPS_TZ2_MASK |
  428. MXC_CCM_CCGR0_APBHDMA_MASK |
  429. MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK |
  430. MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
  431. MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
  432. MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK;
  433. static const uint32_t ccgr1 =
  434. MXC_CCM_CCGR1_ECSPI1S_MASK |
  435. MXC_CCM_CCGR1_ENET_MASK |
  436. MXC_CCM_CCGR1_EPIT1S_MASK |
  437. MXC_CCM_CCGR1_EPIT2S_MASK |
  438. MXC_CCM_CCGR1_GPT_BUS_MASK;
  439. static const uint32_t ccgr2 =
  440. MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK |
  441. MXC_CCM_CCGR2_IPMUX1_MASK |
  442. MXC_CCM_CCGR2_IPMUX2_MASK |
  443. MXC_CCM_CCGR2_IPMUX3_MASK |
  444. MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK |
  445. MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK |
  446. MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK;
  447. static const uint32_t ccgr3 =
  448. MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK |
  449. MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK |
  450. MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK |
  451. MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK |
  452. MXC_CCM_CCGR3_OCRAM_MASK;
  453. static const uint32_t ccgr4 =
  454. MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK |
  455. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
  456. MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK |
  457. MXC_CCM_CCGR4_PWM1_MASK |
  458. MXC_CCM_CCGR4_PWM2_MASK |
  459. MXC_CCM_CCGR4_PWM3_MASK |
  460. MXC_CCM_CCGR4_PWM4_MASK;
  461. static const uint32_t ccgr5 =
  462. MXC_CCM_CCGR5_ROM_MASK |
  463. MXC_CCM_CCGR5_SDMA_MASK |
  464. MXC_CCM_CCGR5_UART_MASK |
  465. MXC_CCM_CCGR5_UART_SERIAL_MASK;
  466. static const uint32_t ccgr6 =
  467. MXC_CCM_CCGR6_USBOH3_MASK |
  468. MXC_CCM_CCGR6_USDHC1_MASK |
  469. MXC_CCM_CCGR6_USDHC2_MASK |
  470. MXC_CCM_CCGR6_SIM1_CLK_MASK |
  471. MXC_CCM_CCGR6_SIM2_CLK_MASK;
  472. writel(ccgr0, &ccm->CCGR0);
  473. writel(ccgr1, &ccm->CCGR1);
  474. writel(ccgr2, &ccm->CCGR2);
  475. writel(ccgr3, &ccm->CCGR3);
  476. writel(ccgr4, &ccm->CCGR4);
  477. writel(ccgr5, &ccm->CCGR5);
  478. writel(ccgr6, &ccm->CCGR6);
  479. }
  480. void board_init_f(ulong dummy)
  481. {
  482. /* setup clock gating */
  483. ccgr_init();
  484. /* setup AIPS and disable watchdog */
  485. arch_cpu_init();
  486. /* setup AXI */
  487. gpr_init();
  488. /*
  489. * setup poweroff GPIO. This controls system power regulator. Once
  490. * the power button is released this must be enabled to keep system
  491. * running. Not enabling it (or disabling it later) will turn off
  492. * the main system regulator and instantly poweroff the system. We
  493. * do this very early, to reduce the time users have to press the
  494. * power button.
  495. */
  496. SETUP_IOMUX_PADS(poweroff_pads);
  497. gpio_direction_output(POWEROFF, 1);
  498. /* setup GP timer */
  499. timer_init();
  500. /* iomux */
  501. if (CONFIG_MXC_UART_BASE == UART2_BASE)
  502. SETUP_IOMUX_PADS(uart2_pads);
  503. else if (CONFIG_MXC_UART_BASE == UART3_BASE)
  504. SETUP_IOMUX_PADS(uart3_pads);
  505. /* UART clocks enabled and gd valid - init serial console */
  506. preloader_console_init();
  507. /* Needed for malloc() [used by SPI] to work in SPL prior to board_init_r() */
  508. spl_init();
  509. /* DDR initialization */
  510. memory_init();
  511. }
  512. void spl_board_prepare_for_boot(void)
  513. {
  514. printf("Load normal U-Boot...\n");
  515. }
  516. #endif