board.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for BuR BRPPT2 board
  4. *
  5. * Copyright (C) 2019
  6. * B&R Industrial Automation GmbH - http://www.br-automation.com/
  7. *
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <spl.h>
  14. #include <dm.h>
  15. #include <miiphy.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/iomux.h>
  19. #include <asm/arch/mx6-pins.h>
  20. #ifdef CONFIG_SPL_BUILD
  21. # include <asm/arch/mx6-ddr.h>
  22. #endif
  23. #include <asm/arch/clock.h>
  24. #include <asm/global_data.h>
  25. #include <asm/io.h>
  26. #include <asm/gpio.h>
  27. #define USBHUB_RSTN IMX_GPIO_NR(1, 16)
  28. #define BKLT_EN IMX_GPIO_NR(1, 15)
  29. #define CAPT_INT IMX_GPIO_NR(4, 9)
  30. #define CAPT_RESETN IMX_GPIO_NR(4, 11)
  31. #define SW_INTN IMX_GPIO_NR(3, 26)
  32. #define VCCDISP_EN IMX_GPIO_NR(5, 18)
  33. #define EMMC_RSTN IMX_GPIO_NR(6, 8)
  34. #define PMIC_IRQN IMX_GPIO_NR(5, 22)
  35. #define TASTER IMX_GPIO_NR(5, 23)
  36. #define ETH0_LINK IMX_GPIO_NR(1, 27)
  37. #define ETH1_LINK IMX_GPIO_NR(1, 28)
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  39. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
  40. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  41. #define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
  43. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  44. #define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  48. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
  49. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  50. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
  52. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  53. #define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
  55. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  56. #define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
  57. PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
  58. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  59. #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  60. PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
  61. PAD_CTL_SRE_FAST)
  62. #define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
  63. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
  64. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  65. #define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
  66. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
  67. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  68. #define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
  69. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
  70. PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  71. #define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
  72. #if !defined(CONFIG_SPL_BUILD)
  73. static iomux_v3_cfg_t const eth_pads[] = {
  74. /*
  75. * Gigabit Ethernet
  76. */
  77. /* CLKs */
  78. MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
  79. MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
  80. /* MDIO */
  81. MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
  82. MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
  83. /* RGMII */
  84. MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
  85. MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
  86. MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
  87. MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
  88. MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
  89. MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
  90. MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
  91. MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
  92. MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
  93. MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
  94. MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
  95. MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
  96. /* ETH0_LINK */
  97. MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
  98. /* ETH1_LINK */
  99. MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
  100. };
  101. static iomux_v3_cfg_t const board_pads[] = {
  102. /*
  103. * I2C #3, #4
  104. */
  105. MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
  106. MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
  107. /*
  108. * UART#4 PADS
  109. * UART_Tasten
  110. */
  111. MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
  112. MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
  113. MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
  114. MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
  115. /*
  116. * ESCPI#1
  117. * M25P32 NOR-Flash
  118. */
  119. MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
  120. MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
  121. MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
  122. MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
  123. /*
  124. * ESCPI#2
  125. * resTouch SPI ADC
  126. */
  127. MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
  128. MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
  129. MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
  130. MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
  131. /*
  132. * USDHC#4
  133. */
  134. MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
  135. MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
  136. MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
  137. MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
  138. MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
  139. MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
  140. MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
  141. MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
  142. MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
  143. MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
  144. /*
  145. * USB OTG power & ID
  146. */
  147. /* USB_OTG_5V_EN */
  148. MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
  149. MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
  150. /* USB_OTG_JUMPER */
  151. MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
  152. /*
  153. * PWM-Pins
  154. */
  155. /* BKLT_CTL */
  156. MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
  157. /* SPEAKER */
  158. MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
  159. /*
  160. * GPIOs
  161. */
  162. /* USB_HUB_nRESET */
  163. MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
  164. /* BKLT_EN */
  165. MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
  166. /* capTouch_INT */
  167. MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
  168. /* capTouch_nRESET */
  169. MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
  170. /* SW_nINT */
  171. MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
  172. /* VCC_DISP_EN */
  173. MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
  174. /* eMMC_nRESET */
  175. MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
  176. /* HWID*/
  177. MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
  178. MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
  179. MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
  180. MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
  181. /* PMIC_nIRQ */
  182. MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
  183. /* nTASTER */
  184. MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
  185. /* RGB LCD Display */
  186. MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
  187. MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
  188. MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
  189. MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
  190. MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
  191. MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
  192. MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
  193. MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
  194. MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
  195. MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
  196. MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
  197. MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
  198. MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
  199. MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
  200. MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
  201. MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
  202. MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
  203. MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
  204. MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
  205. MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
  206. MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
  207. MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
  208. MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
  209. MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
  210. MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
  211. MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
  212. MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
  213. MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
  214. MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
  215. };
  216. int board_ehci_hcd_init(int port)
  217. {
  218. gpio_direction_output(USBHUB_RSTN, 1);
  219. return 0;
  220. }
  221. int board_late_init(void)
  222. {
  223. ulong b_mode = 4;
  224. if (gpio_get_value(TASTER) == 0)
  225. b_mode = 12;
  226. env_set_ulong("b_mode", b_mode);
  227. return 0;
  228. }
  229. int board_init(void)
  230. {
  231. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  232. if (gpio_request(BKLT_EN, "BKLT_EN"))
  233. printf("Warning: BKLT_EN setup failed\n");
  234. gpio_direction_output(BKLT_EN, 0);
  235. if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
  236. printf("Warning: USBHUB_nRST setup failed\n");
  237. gpio_direction_output(USBHUB_RSTN, 0);
  238. if (gpio_request(TASTER, "TASTER"))
  239. printf("Warning: TASTER setup failed\n");
  240. gpio_direction_input(TASTER);
  241. return 0;
  242. }
  243. int board_early_init_f(void)
  244. {
  245. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  246. SETUP_IOMUX_PADS(board_pads);
  247. SETUP_IOMUX_PADS(eth_pads);
  248. /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
  249. setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  250. enable_fec_anatop_clock(0, ENET_25MHZ);
  251. enable_enet_clk(1);
  252. return 0;
  253. }
  254. int dram_init(void)
  255. {
  256. gd->ram_size = imx_ddr_size();
  257. return 0;
  258. }
  259. #else
  260. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  261. static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
  262. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  263. .dram_sdclk_0 = 0x00020030,
  264. .dram_sdclk_1 = 0x00020030,
  265. .dram_cas = 0x00020030,
  266. .dram_ras = 0x00020030,
  267. .dram_reset = 0x00020030,
  268. /* SDCKE[0:1]: 100k pull-up */
  269. .dram_sdcke0 = 0x00003000,
  270. .dram_sdcke1 = 0x00003000,
  271. /* SDBA2: pull-up disabled */
  272. .dram_sdba2 = 0x00000000,
  273. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  274. .dram_sdodt0 = 0x00003030,
  275. .dram_sdodt1 = 0x00003030,
  276. /* SDQS[0:7]: Differential input, 40 ohm */
  277. .dram_sdqs0 = 0x00000030,
  278. .dram_sdqs1 = 0x00000030,
  279. .dram_sdqs2 = 0x00000030,
  280. .dram_sdqs3 = 0x00000030,
  281. .dram_sdqs4 = 0x00000030,
  282. .dram_sdqs5 = 0x00000030,
  283. .dram_sdqs6 = 0x00000030,
  284. .dram_sdqs7 = 0x00000030,
  285. /* DQM[0:7]: Differential input, 40 ohm */
  286. .dram_dqm0 = 0x00020030,
  287. .dram_dqm1 = 0x00020030,
  288. .dram_dqm2 = 0x00020030,
  289. .dram_dqm3 = 0x00020030,
  290. .dram_dqm4 = 0x00020030,
  291. .dram_dqm5 = 0x00020030,
  292. .dram_dqm6 = 0x00020030,
  293. .dram_dqm7 = 0x00020030,
  294. };
  295. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  296. static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
  297. /* DDR3 */
  298. .grp_ddr_type = 0x000c0000,
  299. .grp_ddrmode_ctl = 0x00020000,
  300. /* disable DDR pullups */
  301. .grp_ddrpke = 0x00000000,
  302. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  303. .grp_addds = 0x00000030,
  304. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  305. .grp_ctlds = 0x00000030,
  306. /* DATA[00:63]: Differential input, 40 ohm */
  307. .grp_ddrmode = 0x00020000,
  308. .grp_b0ds = 0x00000030,
  309. .grp_b1ds = 0x00000030,
  310. .grp_b2ds = 0x00000030,
  311. .grp_b3ds = 0x00000030,
  312. .grp_b4ds = 0x00000030,
  313. .grp_b5ds = 0x00000030,
  314. .grp_b6ds = 0x00000030,
  315. .grp_b7ds = 0x00000030,
  316. };
  317. /*
  318. * DDR3 desriptions - these are the memory chips we support
  319. */
  320. /* NT5CC128M16FP-DII */
  321. static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
  322. .mem_speed = 1600,
  323. .density = 2,
  324. .width = 16,
  325. .banks = 8,
  326. .rowaddr = 14,
  327. .coladdr = 10,
  328. .pagesz = 2,
  329. .trcd = 1375,
  330. .trcmin = 4875,
  331. .trasmin = 3500,
  332. };
  333. /* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
  334. static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
  335. /* write leveling calibration determine, MR1-value = 0x0002 */
  336. .p0_mpwldectrl0 = 0x003F003E,
  337. .p0_mpwldectrl1 = 0x003A003A,
  338. .p1_mpwldectrl0 = 0x001B001C,
  339. .p1_mpwldectrl1 = 0x00190031,
  340. /* Read DQS Gating calibration */
  341. .p0_mpdgctrl0 = 0x02640264,
  342. .p0_mpdgctrl1 = 0x02440250,
  343. .p1_mpdgctrl0 = 0x02400250,
  344. .p1_mpdgctrl1 = 0x0238023C,
  345. /* Read Calibration: DQS delay relative to DQ read access */
  346. .p0_mprddlctl = 0x40464644,
  347. .p1_mprddlctl = 0x464A4842,
  348. /* Write Calibration: DQ/DM delay relative to DQS write access */
  349. .p0_mpwrdlctl = 0x38343034,
  350. .p1_mpwrdlctl = 0x36323830,
  351. };
  352. /* measured on board TSERIES_ARM/1 V_LVDS_S32 */
  353. static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
  354. /* write leveling calibration determine, MR1-value = 0x0002 */
  355. .p0_mpwldectrl0 = 0x00410043,
  356. .p0_mpwldectrl1 = 0x003A003C,
  357. /* Read DQS Gating calibration */
  358. .p0_mpdgctrl0 = 0x023C0244,
  359. .p0_mpdgctrl1 = 0x02240230,
  360. /* Read Calibration: DQS delay relative to DQ read access */
  361. .p0_mprddlctl = 0x484C4A48,
  362. /* Write Calibration: DQ/DM delay relative to DQS write access */
  363. .p0_mpwrdlctl = 0x3C363434,
  364. };
  365. static void spl_dram_init(void)
  366. {
  367. struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
  368. u32 val, dram_strap = 0;
  369. struct mx6_ddr3_cfg *mem = NULL;
  370. struct mx6_mmdc_calibration *calib = NULL;
  371. struct mx6_ddr_sysinfo sysinfo = {
  372. /* width of data bus:0=16,1=32,2=64 */
  373. .dsize = -1, /* CPU type specific (overwritten) */
  374. /* config for full 4GB range so that get_mem_size() works */
  375. .cs_density = 32, /* 32Gb per CS */
  376. .ncs = 1, /* single chip select */
  377. .cs1_mirror = 0,
  378. .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
  379. .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
  380. .walat = 1, /* Write additional latency */
  381. .ralat = 5, /* Read additional latency */
  382. .mif3_mode = 3, /* Command prediction working mode */
  383. .bi_on = 1, /* Bank interleaving enabled */
  384. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  385. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  386. .ddr_type = 0, /* DDR3 */
  387. };
  388. /*
  389. * MMDC Calibration requires the following data:
  390. * mx6_mmdc_calibration - board-specific calibration (routing delays)
  391. * these calibration values depend on board routing, SoC, and DDR
  392. * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
  393. * mx6_ddr_cfg - chip specific timing/layout details
  394. */
  395. /* setup HWID3-2 to input */
  396. val = readl(&gpio->gpio_dir);
  397. val &= ~(0x1 << 0 | 0x1 << 1);
  398. writel(val, &gpio->gpio_dir);
  399. /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
  400. dram_strap = readl(&gpio->gpio_psr) & 0x3;
  401. switch (dram_strap) {
  402. /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
  403. case 0:
  404. puts("DRAM strap 00\n");
  405. mem = &cfg_nt5cc128m16fp_dii;
  406. sysinfo.dsize = 2;
  407. calib = &cal_nt5cc128m16fp_dii_128x64_s;
  408. break;
  409. /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
  410. case 1:
  411. puts("DRAM strap 01\n");
  412. mem = &cfg_nt5cc128m16fp_dii;
  413. sysinfo.dsize = 1;
  414. calib = &cal_nt5cc128m16fp_dii_128x32_s;
  415. break;
  416. default:
  417. printf("DRAM strap 0x%x (invalid)\n", dram_strap);
  418. break;
  419. }
  420. if (!mem) {
  421. puts("Error: Invalid Memory Configuration\n");
  422. hang();
  423. }
  424. if (!calib) {
  425. puts("Error: Invalid Board Calibration Configuration\n");
  426. hang();
  427. }
  428. mx6sdl_dram_iocfg(16 << sysinfo.dsize,
  429. &ddr_iomux_s,
  430. &grp_iomux_s);
  431. mx6_dram_cfg(&sysinfo, calib, mem);
  432. }
  433. static iomux_v3_cfg_t const board_pads_spl[] = {
  434. /* UART#1 PADS */
  435. MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
  436. MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
  437. /* ESCPI#1 PADS */
  438. MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
  439. MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
  440. MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
  441. MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
  442. /* USDHC#4 PADS */
  443. MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
  444. MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
  445. MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
  446. MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
  447. MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
  448. MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
  449. MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
  450. MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
  451. MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
  452. MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
  453. /* HWID*/
  454. MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
  455. MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
  456. MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
  457. MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
  458. };
  459. void spl_board_init(void)
  460. {
  461. preloader_console_init();
  462. }
  463. static void ccgr_init(void)
  464. {
  465. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  466. /*
  467. * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
  468. * initializes DMA very early (before all board code), so the only
  469. * opportunity we have to initialize APBHDMA clocks is in SPL.
  470. * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  471. */
  472. writel(0x00C03F3F, &ccm->CCGR0);
  473. writel(0x00F0FC03, &ccm->CCGR1);
  474. writel(0x0FFFF000, &ccm->CCGR2);
  475. writel(0x3FF00000, &ccm->CCGR3);
  476. writel(0x00FFF300, &ccm->CCGR4);
  477. writel(0x0F0030C3, &ccm->CCGR5);
  478. writel(0x000003F0, &ccm->CCGR6);
  479. }
  480. void board_init_f(ulong dummy)
  481. {
  482. ccgr_init();
  483. arch_cpu_init();
  484. timer_init();
  485. gpr_init();
  486. SETUP_IOMUX_PADS(board_pads_spl);
  487. spl_dram_init();
  488. }
  489. void reset_cpu(void)
  490. {
  491. }
  492. #endif /* CONFIG_SPL_BUILD */