cpu.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * (C) Copyright 2008
  5. * Graeme Russ, graeme.russ@gmail.com.
  6. *
  7. * Some portions from coreboot src/mainboard/google/link/romstage.c
  8. * and src/cpu/intel/model_206ax/bootblock.c
  9. * Copyright (C) 2007-2010 coresystems GmbH
  10. * Copyright (C) 2011 Google Inc.
  11. */
  12. #include <common.h>
  13. #include <cpu_func.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <fdtdec.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <pch.h>
  20. #include <asm/cpu.h>
  21. #include <asm/cpu_common.h>
  22. #include <asm/global_data.h>
  23. #include <asm/intel_regs.h>
  24. #include <asm/io.h>
  25. #include <asm/lapic.h>
  26. #include <asm/lpc_common.h>
  27. #include <asm/microcode.h>
  28. #include <asm/msr.h>
  29. #include <asm/mtrr.h>
  30. #include <asm/pci.h>
  31. #include <asm/post.h>
  32. #include <asm/processor.h>
  33. #include <asm/arch/model_206ax.h>
  34. #include <asm/arch/pch.h>
  35. #include <asm/arch/sandybridge.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static int set_flex_ratio_to_tdp_nominal(void)
  38. {
  39. /* Minimum CPU revision for configurable TDP support */
  40. if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
  41. return -EINVAL;
  42. return cpu_set_flex_ratio_to_tdp_nominal();
  43. }
  44. int arch_cpu_init(void)
  45. {
  46. post_code(POST_CPU_INIT);
  47. return x86_cpu_init_f();
  48. }
  49. int arch_cpu_init_dm(void)
  50. {
  51. struct pci_controller *hose;
  52. struct udevice *bus, *dev;
  53. int ret;
  54. post_code(0x70);
  55. ret = uclass_get_device(UCLASS_PCI, 0, &bus);
  56. post_code(0x71);
  57. if (ret)
  58. return ret;
  59. post_code(0x72);
  60. hose = dev_get_uclass_priv(bus);
  61. /* TODO(sjg@chromium.org): Get rid of gd->hose */
  62. gd->hose = hose;
  63. ret = uclass_first_device_err(UCLASS_LPC, &dev);
  64. if (ret)
  65. return ret;
  66. /*
  67. * We should do as little as possible before the serial console is
  68. * up. Perhaps this should move to later. Our next lot of init
  69. * happens in checkcpu() when we have a console
  70. */
  71. ret = set_flex_ratio_to_tdp_nominal();
  72. if (ret)
  73. return ret;
  74. return 0;
  75. }
  76. #define PCH_EHCI0_TEMP_BAR0 0xe8000000
  77. #define PCH_EHCI1_TEMP_BAR0 0xe8000400
  78. #define PCH_XHCI_TEMP_BAR0 0xe8001000
  79. /*
  80. * Setup USB controller MMIO BAR to prevent the reference code from
  81. * resetting the controller.
  82. *
  83. * The BAR will be re-assigned during device enumeration so these are only
  84. * temporary.
  85. *
  86. * This is used to speed up the resume path.
  87. */
  88. static void enable_usb_bar(struct udevice *bus)
  89. {
  90. pci_dev_t usb0 = PCH_EHCI1_DEV;
  91. pci_dev_t usb1 = PCH_EHCI2_DEV;
  92. pci_dev_t usb3 = PCH_XHCI_DEV;
  93. ulong cmd;
  94. /* USB Controller 1 */
  95. pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
  96. PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
  97. pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
  98. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  99. pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
  100. /* USB Controller 2 */
  101. pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
  102. PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
  103. pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
  104. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  105. pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
  106. /* USB3 Controller 1 */
  107. pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
  108. PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
  109. pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
  110. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  111. pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
  112. }
  113. int checkcpu(void)
  114. {
  115. enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
  116. struct udevice *dev, *lpc;
  117. uint32_t pm1_cnt;
  118. uint16_t pm1_sts;
  119. int ret;
  120. /* TODO: cmos_post_init() */
  121. if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
  122. debug("soft reset detected\n");
  123. boot_mode = PEI_BOOT_SOFT_RESET;
  124. /* System is not happy after keyboard reset... */
  125. debug("Issuing CF9 warm reset\n");
  126. reset_cpu();
  127. }
  128. ret = cpu_common_init();
  129. if (ret) {
  130. debug("%s: cpu_common_init() failed\n", __func__);
  131. return ret;
  132. }
  133. /* Check PM1_STS[15] to see if we are waking from Sx */
  134. pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
  135. /* Read PM1_CNT[12:10] to determine which Sx state */
  136. pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
  137. if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
  138. debug("Resume from S3 detected, but disabled.\n");
  139. } else {
  140. /*
  141. * TODO: An indication of life might be possible here (e.g.
  142. * keyboard light)
  143. */
  144. }
  145. post_code(POST_EARLY_INIT);
  146. /* Enable SPD ROMs and DDR-III DRAM */
  147. ret = uclass_first_device_err(UCLASS_I2C, &dev);
  148. if (ret) {
  149. debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
  150. return ret;
  151. }
  152. /* Prepare USB controller early in S3 resume */
  153. if (boot_mode == PEI_BOOT_RESUME) {
  154. uclass_first_device(UCLASS_LPC, &lpc);
  155. enable_usb_bar(pci_get_controller(lpc->parent));
  156. }
  157. gd->arch.pei_boot_mode = boot_mode;
  158. return 0;
  159. }
  160. int print_cpuinfo(void)
  161. {
  162. char processor_name[CPU_MAX_NAME_LEN];
  163. const char *name;
  164. /* Print processor name */
  165. name = cpu_get_name(processor_name);
  166. printf("CPU: %s\n", name);
  167. post_code(POST_CPU_INFO);
  168. return 0;
  169. }
  170. void board_debug_uart_init(void)
  171. {
  172. /* This enables the debug UART */
  173. pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
  174. }