psci.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <cpu_func.h>
  7. #include <linux/bitops.h>
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/printk.h>
  12. #include <linux/psci.h>
  13. #include <linux/sizes.h>
  14. #include <asm/processor.h>
  15. #include <asm/psci.h>
  16. #include <asm/secure.h>
  17. #include <asm/system.h>
  18. #include "../debug.h"
  19. #include "../soc-info.h"
  20. #include "arm-mpcore.h"
  21. #include "cache-uniphier.h"
  22. #define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208
  23. void uniphier_smp_trampoline(void);
  24. void uniphier_smp_trampoline_end(void);
  25. u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
  26. static int uniphier_get_nr_cpus(void)
  27. {
  28. switch (uniphier_get_soc_id()) {
  29. case UNIPHIER_PRO4_ID:
  30. case UNIPHIER_PRO5_ID:
  31. return 2;
  32. case UNIPHIER_PXS2_ID:
  33. case UNIPHIER_LD6B_ID:
  34. return 4;
  35. default:
  36. return 1;
  37. }
  38. }
  39. static void uniphier_smp_kick_all_cpus(void)
  40. {
  41. const u32 target_ways = BIT(0);
  42. size_t trmp_size;
  43. u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
  44. u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
  45. u32 trmp_dest, trmp_dest_end;
  46. int nr_cpus, i;
  47. int timeout = 1000;
  48. nr_cpus = uniphier_get_nr_cpus();
  49. if (nr_cpus == 1)
  50. return;
  51. for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */
  52. uniphier_cache_set_active_ways(i, 0);
  53. uniphier_cache_inv_way(target_ways);
  54. uniphier_cache_enable();
  55. /* copy trampoline code */
  56. uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
  57. trmp_size = trmp_src_end - trmp_src;
  58. trmp_dest = trmp_src & (SZ_64K - 1);
  59. trmp_dest += SZ_1M - SZ_64K * 2;
  60. trmp_dest_end = trmp_dest + trmp_size;
  61. uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
  62. writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
  63. asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */
  64. "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
  65. while (--timeout) {
  66. int all_booted = 1;
  67. for (i = 1; i < nr_cpus; i++)
  68. if (!uniphier_smp_booted[i])
  69. all_booted = 0;
  70. if (all_booted)
  71. break;
  72. udelay(1);
  73. /* barrier here because uniphier_smp_booted[] may be updated */
  74. cpu_relax();
  75. }
  76. if (!timeout)
  77. pr_warn("warning: some of secondary CPUs may not boot\n");
  78. uniphier_cache_disable();
  79. }
  80. void psci_board_init(void)
  81. {
  82. unsigned long scu_base;
  83. u32 scu_ctrl, tmp;
  84. asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
  85. scu_ctrl = readl(scu_base + 0x30);
  86. if (!(scu_ctrl & 1))
  87. writel(scu_ctrl | 0x1, scu_base + 0x30);
  88. scu_ctrl = readl(scu_base + SCU_CTRL);
  89. scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
  90. writel(scu_ctrl, scu_base + SCU_CTRL);
  91. tmp = readl(scu_base + SCU_SNSAC);
  92. tmp |= 0xfff;
  93. writel(tmp, scu_base + SCU_SNSAC);
  94. uniphier_smp_kick_all_cpus();
  95. }
  96. void psci_arch_init(void)
  97. {
  98. u32 actlr;
  99. asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
  100. actlr |= 0x41; /* set SMP and FW bits */
  101. asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
  102. }
  103. u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
  104. s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
  105. u32 context_id)
  106. {
  107. u32 cpu = cpuid & 0xff;
  108. debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid=");
  109. debug_puth(cpuid);
  110. debug_puts(", entry_point=");
  111. debug_puth(entry_point);
  112. debug_puts(", context_id=");
  113. debug_puth(context_id);
  114. debug_puts("\n");
  115. psci_save(cpu, entry_point, context_id);
  116. /* We assume D-cache is off, so do not call flush_dcache() here */
  117. uniphier_psci_holding_pen_release = cpu;
  118. /* Send an event to wake up the secondary CPU. */
  119. asm("dsb ishst\n"
  120. "sev");
  121. return PSCI_RET_SUCCESS;
  122. }
  123. void __secure psci_system_reset(void)
  124. {
  125. reset_cpu();
  126. }