pmc.c 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <log.h>
  8. #include <asm/global_data.h>
  9. #include <linux/arm-smccc.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-tegra/pmc.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  14. static bool tegra_pmc_detect_tz_only(void)
  15. {
  16. static bool initialized = false;
  17. static bool is_tz_only = false;
  18. u32 value, saved;
  19. if (!initialized) {
  20. saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  21. value = saved ^ 0xffffffff;
  22. if (value == 0xffffffff)
  23. value = 0xdeadbeef;
  24. /* write pattern and read it back */
  25. writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
  26. value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  27. /* if we read all-zeroes, access is restricted to TZ only */
  28. if (value == 0) {
  29. debug("access to PMC is restricted to TZ\n");
  30. is_tz_only = true;
  31. } else {
  32. /* restore original value */
  33. writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
  34. }
  35. initialized = true;
  36. }
  37. return is_tz_only;
  38. }
  39. #endif
  40. uint32_t tegra_pmc_readl(unsigned long offset)
  41. {
  42. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  43. if (tegra_pmc_detect_tz_only()) {
  44. struct arm_smccc_res res;
  45. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
  46. 0, 0, 0, &res);
  47. if (res.a0)
  48. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  49. return res.a1;
  50. }
  51. #endif
  52. return readl(NV_PA_PMC_BASE + offset);
  53. }
  54. void tegra_pmc_writel(u32 value, unsigned long offset)
  55. {
  56. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  57. if (tegra_pmc_detect_tz_only()) {
  58. struct arm_smccc_res res;
  59. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
  60. value, 0, 0, 0, 0, &res);
  61. if (res.a0)
  62. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  63. return;
  64. }
  65. #endif
  66. writel(value, NV_PA_PMC_BASE + offset);
  67. }
  68. void reset_cpu(void)
  69. {
  70. u32 value;
  71. value = tegra_pmc_readl(PMC_CNTRL);
  72. value |= PMC_CNTRL_MAIN_RST;
  73. tegra_pmc_writel(value, PMC_CNTRL);
  74. }