soc.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Actions Semi Owl SoCs platform support.
  4. *
  5. * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  6. */
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <asm/cache.h>
  10. #include <asm/global_data.h>
  11. #include <linux/arm-smccc.h>
  12. #include <linux/psci.h>
  13. #include <common.h>
  14. #include <asm/io.h>
  15. #include <asm/mach-types.h>
  16. #include <asm/psci.h>
  17. #define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028
  18. DECLARE_GLOBAL_DATA_PTR;
  19. unsigned int owl_get_ddrcap(void)
  20. {
  21. unsigned int val, cap;
  22. /* ddr capacity register initialized by ddr driver
  23. * in early bootloader
  24. */
  25. #if defined(CONFIG_MACH_S700)
  26. val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7;
  27. cap = (val + 1) * 256;
  28. #elif defined(CONFIG_MACH_S900)
  29. val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf;
  30. cap = 64 * (1 << val);
  31. #endif
  32. return cap;
  33. }
  34. /*
  35. * dram_init - sets uboots idea of sdram size
  36. */
  37. int dram_init(void)
  38. {
  39. gd->ram_size = owl_get_ddrcap() * 1024 * 1024;
  40. return 0;
  41. }
  42. /* This is called after dram_init() so use get_ram_size result */
  43. int dram_init_banksize(void)
  44. {
  45. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  46. gd->bd->bi_dram[0].size = gd->ram_size;
  47. return 0;
  48. }
  49. static void show_psci_version(void)
  50. {
  51. struct arm_smccc_res res;
  52. arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
  53. printf("PSCI: v%ld.%ld\n",
  54. PSCI_VERSION_MAJOR(res.a0),
  55. PSCI_VERSION_MINOR(res.a0));
  56. }
  57. int board_init(void)
  58. {
  59. show_psci_version();
  60. return 0;
  61. }
  62. void reset_cpu(void)
  63. {
  64. psci_system_reset();
  65. }