cpu.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dm.h>
  8. #include <fdtdec.h>
  9. #include <linux/libfdt.h>
  10. #include <asm/io.h>
  11. #include <asm/system.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <asm/armv8/mmu.h>
  15. /* Armada 7k/8k */
  16. #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
  17. #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
  18. #define RFU_SW_RESET_OFFSET 0
  19. #define SAR0_REG (MVEBU_REGISTER(0x2400200))
  20. #define BOOT_MODE_MASK 0x3f
  21. #define BOOT_MODE_OFFSET 4
  22. /*
  23. * The following table includes all memory regions for Armada 7k and
  24. * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
  25. * define these regions at the beginning of the struct so that they
  26. * can be easier removed later dynamically if an Armada 7k device is detected.
  27. * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
  28. */
  29. #define ARMADA_7K8K_COMMON_REGIONS_START 2
  30. static struct mm_region mvebu_mem_map[] = {
  31. /* Armada 80x0 memory regions include the CP1 (slave) units */
  32. {
  33. /* SRAM, MMIO regions - CP110 slave region */
  34. .phys = 0xf4000000UL,
  35. .virt = 0xf4000000UL,
  36. .size = 0x02000000UL, /* 32MiB internal registers */
  37. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  38. PTE_BLOCK_NON_SHARE
  39. },
  40. {
  41. /* PCI CP1 regions */
  42. .phys = 0xfa000000UL,
  43. .virt = 0xfa000000UL,
  44. .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
  45. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  46. PTE_BLOCK_NON_SHARE
  47. },
  48. /* Armada 80x0 and 70x0 common memory regions start here */
  49. {
  50. /* RAM */
  51. .phys = 0x0UL,
  52. .virt = 0x0UL,
  53. .size = 0x80000000UL,
  54. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  55. PTE_BLOCK_INNER_SHARE
  56. },
  57. {
  58. /* SRAM, MMIO regions - AP806 region */
  59. .phys = 0xf0000000UL,
  60. .virt = 0xf0000000UL,
  61. .size = 0x01000000UL, /* 16MiB internal registers */
  62. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  63. PTE_BLOCK_NON_SHARE
  64. },
  65. {
  66. /* SRAM, MMIO regions - CP110 master region */
  67. .phys = 0xf2000000UL,
  68. .virt = 0xf2000000UL,
  69. .size = 0x02000000UL, /* 32MiB internal registers */
  70. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  71. PTE_BLOCK_NON_SHARE
  72. },
  73. {
  74. /* PCI CP0 regions */
  75. .phys = 0xf6000000UL,
  76. .virt = 0xf6000000UL,
  77. .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
  78. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  79. PTE_BLOCK_NON_SHARE
  80. },
  81. {
  82. 0,
  83. }
  84. };
  85. struct mm_region *mem_map = mvebu_mem_map;
  86. void enable_caches(void)
  87. {
  88. /*
  89. * Armada 7k is not equipped with the CP110 slave CP. In case this
  90. * code runs on an Armada 7k device, lets remove the CP110 slave
  91. * entries from the memory mapping by moving the start to the
  92. * common regions.
  93. */
  94. if (of_machine_is_compatible("marvell,armada7040"))
  95. mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
  96. icache_enable();
  97. dcache_enable();
  98. }
  99. void reset_cpu(void)
  100. {
  101. u32 reg;
  102. reg = readl(RFU_GLOBAL_SW_RST);
  103. reg &= ~(1 << RFU_SW_RESET_OFFSET);
  104. writel(reg, RFU_GLOBAL_SW_RST);
  105. }
  106. /*
  107. * TODO - implement this functionality using platform
  108. * clock driver once it gets available
  109. * Return NAND clock in Hz
  110. */
  111. u32 mvebu_get_nand_clock(void)
  112. {
  113. unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
  114. unsigned long NF_CLOCK_SEL_MASK = 0x1;
  115. u32 reg;
  116. reg = readl(NAND_FLASH_CLK_CTRL);
  117. if (reg & NF_CLOCK_SEL_MASK)
  118. return 400 * 1000000;
  119. else
  120. return 250 * 1000000;
  121. }
  122. int mmc_get_env_dev(void)
  123. {
  124. u32 reg;
  125. unsigned int boot_mode;
  126. reg = readl(SAR0_REG);
  127. boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
  128. switch (boot_mode) {
  129. case 0x28:
  130. case 0x2a:
  131. return 0;
  132. case 0x29:
  133. case 0x2b:
  134. return 1;
  135. }
  136. return CONFIG_SYS_MMC_ENV_DEV;
  137. }