init.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: Architecture initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <init.h>
  11. #include <ns16550.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/msmc.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/psc_defs.h>
  18. #include <linux/bitops.h>
  19. #define MAX_PCI_PORTS 2
  20. enum pci_mode {
  21. ENDPOINT,
  22. LEGACY_ENDPOINT,
  23. ROOTCOMPLEX,
  24. };
  25. #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
  26. #define DEVCFG_MODE_SHIFT 1
  27. void chip_configuration_unlock(void)
  28. {
  29. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  30. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  31. }
  32. #ifdef CONFIG_SOC_K2L
  33. void osr_init(void)
  34. {
  35. u32 i;
  36. u32 j;
  37. u32 val;
  38. u32 base = KS2_OSR_CFG_BASE;
  39. u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  40. /* Enable the OSR clock domain */
  41. psc_enable_module(KS2_LPSC_OSR);
  42. /* Disable OSR ECC check for all the ram banks */
  43. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  44. val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  45. (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  46. writel(val , base + KS2_OSR_ECC_VEC);
  47. /**
  48. * wait till read is done.
  49. * Print should be added after earlyprintk support is added.
  50. */
  51. for (j = 0; j < 10000; j++) {
  52. val = readl(base + KS2_OSR_ECC_VEC);
  53. if (val & KS2_OSR_ECC_VEC_RD_DONE)
  54. break;
  55. }
  56. ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  57. KS2_OSR_ECC_CTRL_CHK;
  58. writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  59. writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  60. }
  61. /* Reset OSR memory to all zeros */
  62. for (i = 0; i < KS2_OSR_SIZE; i += 4)
  63. writel(0, KS2_OSR_DATA_BASE + i);
  64. /* Enable OSR ECC check for all the ram banks */
  65. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  66. writel(ecc_ctrl[i] |
  67. KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  68. }
  69. #endif
  70. /* Function to set up PCIe mode */
  71. static void config_pcie_mode(int pcie_port, enum pci_mode mode)
  72. {
  73. u32 val = __raw_readl(KS2_DEVCFG);
  74. if (pcie_port >= MAX_PCI_PORTS)
  75. return;
  76. /**
  77. * each pci port has two bits for mode and it starts at
  78. * bit 1. So use port number to get the right bit position.
  79. */
  80. pcie_port <<= 1;
  81. val &= ~(DEVCFG_MODE_MASK << pcie_port);
  82. val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  83. __raw_writel(val, KS2_DEVCFG);
  84. }
  85. static void msmc_k2hkle_common_setup(void)
  86. {
  87. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  88. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
  89. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
  90. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
  91. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
  92. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  93. }
  94. static void msmc_k2hk_setup(void)
  95. {
  96. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  97. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  98. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  99. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
  100. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
  101. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
  102. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
  103. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  104. }
  105. static inline void msmc_k2l_setup(void)
  106. {
  107. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  108. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  109. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  110. msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
  111. }
  112. static inline void msmc_k2e_setup(void)
  113. {
  114. msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
  115. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  116. msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
  117. }
  118. static void msmc_k2g_setup(void)
  119. {
  120. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  121. msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
  122. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
  123. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
  124. msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
  125. msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
  126. msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
  127. msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
  128. msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
  129. msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
  130. msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
  131. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  132. }
  133. int arch_cpu_init(void)
  134. {
  135. chip_configuration_unlock();
  136. icache_enable();
  137. if (cpu_is_k2g()) {
  138. msmc_k2g_setup();
  139. } else {
  140. msmc_k2hkle_common_setup();
  141. if (cpu_is_k2e())
  142. msmc_k2e_setup();
  143. else if (cpu_is_k2l())
  144. msmc_k2l_setup();
  145. else
  146. msmc_k2hk_setup();
  147. }
  148. /* Initialize the PCIe-0 to work as Root Complex */
  149. config_pcie_mode(0, ROOTCOMPLEX);
  150. #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  151. /* Initialize the PCIe-1 to work as Root Complex */
  152. config_pcie_mode(1, ROOTCOMPLEX);
  153. #endif
  154. #ifdef CONFIG_SOC_K2L
  155. osr_init();
  156. #endif
  157. /*
  158. * just initialise the COM2 port so that TI specific
  159. * UART register PWREMU_MGMT is initialized. Linux UART
  160. * driver doesn't handle this.
  161. */
  162. #ifndef CONFIG_DM_SERIAL
  163. ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2),
  164. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  165. #endif
  166. return 0;
  167. }
  168. void reset_cpu(void)
  169. {
  170. volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
  171. u32 tmp;
  172. tmp = *rstctrl & KS2_RSTCTRL_MASK;
  173. *rstctrl = tmp | KS2_RSTCTRL_KEY;
  174. *rstctrl &= KS2_RSTCTRL_SWRST;
  175. for (;;)
  176. ;
  177. }
  178. void enable_caches(void)
  179. {
  180. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  181. /* Enable D-cache. I-cache is already enabled in start.S */
  182. dcache_enable();
  183. #endif
  184. }
  185. #if defined(CONFIG_DISPLAY_CPUINFO)
  186. int print_cpuinfo(void)
  187. {
  188. u16 cpu = get_part_number();
  189. u8 rev = cpu_revision();
  190. puts("CPU: ");
  191. switch (cpu) {
  192. case CPU_66AK2Hx:
  193. puts("66AK2Hx SR");
  194. break;
  195. case CPU_66AK2Lx:
  196. puts("66AK2Lx SR");
  197. break;
  198. case CPU_66AK2Ex:
  199. puts("66AK2Ex SR");
  200. break;
  201. case CPU_66AK2Gx:
  202. puts("66AK2Gx");
  203. #ifdef CONFIG_SOC_K2G
  204. {
  205. int speed = get_max_arm_speed(speeds);
  206. if (speed == SPD1000)
  207. puts("-100 ");
  208. else if (speed == SPD600)
  209. puts("-60 ");
  210. else
  211. puts("-xx ");
  212. }
  213. #endif
  214. puts("SR");
  215. break;
  216. default:
  217. puts("Unknown\n");
  218. }
  219. if (rev == 2)
  220. puts("2.0\n");
  221. else if (rev == 1)
  222. puts("1.1\n");
  223. else if (rev == 0)
  224. puts("1.0\n");
  225. else if (rev == 8)
  226. puts("1.0\n");
  227. return 0;
  228. }
  229. #endif