soc.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/mach-imx/hab.h>
  15. #include <linux/bitops.h>
  16. #define PMC0_BASE_ADDR 0x410a1000
  17. #define PMC0_CTRL 0x28
  18. #define PMC0_CTRL_LDOEN BIT(31)
  19. #define PMC0_CTRL_LDOOKDIS BIT(30)
  20. #define PMC0_CTRL_PMC1ON BIT(24)
  21. #define PMC1_BASE_ADDR 0x40400000
  22. #define PMC1_RUN 0x8
  23. #define PMC1_STOP 0x10
  24. #define PMC1_VLPS 0x14
  25. #define PMC1_LDOVL_SHIFT 16
  26. #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
  27. #define PMC1_LDOVL_900 0x1e
  28. #define PMC1_LDOVL_950 0x23
  29. #define PMC1_STATUS 0x20
  30. #define PMC1_STATUS_LDOVLF BIT(8)
  31. static char *get_reset_cause(char *);
  32. #if defined(CONFIG_IMX_HAB)
  33. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  34. .bank = 29,
  35. .word = 6,
  36. };
  37. #endif
  38. #define ROM_VERSION_ADDR 0x80
  39. u32 get_cpu_rev(void)
  40. {
  41. /* Check the ROM version for cpu revision */
  42. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  43. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  44. }
  45. #ifdef CONFIG_REVISION_TAG
  46. u32 __weak get_board_rev(void)
  47. {
  48. return get_cpu_rev();
  49. }
  50. #endif
  51. enum bt_mode get_boot_mode(void)
  52. {
  53. u32 bt0_cfg = 0;
  54. bt0_cfg = readl(CMC0_RBASE + 0x40);
  55. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  56. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  57. /* No low power boot */
  58. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  59. return DUAL_BOOT;
  60. else
  61. return SINGLE_BOOT;
  62. }
  63. return LOW_POWER_BOOT;
  64. }
  65. int arch_cpu_init(void)
  66. {
  67. return 0;
  68. }
  69. #ifdef CONFIG_BOARD_POSTCLK_INIT
  70. int board_postclk_init(void)
  71. {
  72. return 0;
  73. }
  74. #endif
  75. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  76. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  77. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  78. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  79. static void disable_wdog(u32 wdog_base)
  80. {
  81. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  82. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  83. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  84. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  85. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  86. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  87. writel(REFRESH_WORD1, (wdog_base + 0x04));
  88. }
  89. void init_wdog(void)
  90. {
  91. /*
  92. * ROM will configure WDOG1, disable it or enable it
  93. * depending on FUSE. The update bit is set for reconfigurable.
  94. * We have to use unlock sequence to reconfigure it.
  95. * WDOG2 is not touched by ROM, so it will have default value
  96. * which is enabled. We can directly configure it.
  97. * To simplify the codes, we still use same reconfigure
  98. * process as WDOG1. Because the update bit is not set for
  99. * WDOG2, the unlock sequence won't take effect really.
  100. * It actually directly configure the wdog.
  101. * In this function, we will disable both WDOG1 and WDOG2,
  102. * and set update bit for both. So that kernel can reconfigure them.
  103. */
  104. disable_wdog(WDG1_RBASE);
  105. disable_wdog(WDG2_RBASE);
  106. }
  107. static bool ldo_mode_is_enabled(void)
  108. {
  109. unsigned int reg;
  110. reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
  111. if (reg & PMC0_CTRL_LDOEN)
  112. return true;
  113. else
  114. return false;
  115. }
  116. #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
  117. #if defined(CONFIG_LDO_ENABLED_MODE)
  118. static void init_ldo_mode(void)
  119. {
  120. unsigned int reg;
  121. if (ldo_mode_is_enabled())
  122. return;
  123. /* Set LDOOKDIS */
  124. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
  125. /* Set LDOVL to 0.95V in PMC1_RUN */
  126. reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
  127. reg &= ~PMC1_LDOVL_MASK;
  128. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  129. writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
  130. /* Wait for LDOVLF to be cleared */
  131. reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
  132. while (reg & PMC1_STATUS_LDOVLF)
  133. ;
  134. /* Set LDOVL to 0.95V in PMC1_STOP */
  135. reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
  136. reg &= ~PMC1_LDOVL_MASK;
  137. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  138. writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
  139. /* Set LDOVL to 0.90V in PMC1_VLPS */
  140. reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
  141. reg &= ~PMC1_LDOVL_MASK;
  142. reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
  143. writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
  144. /* Set LDOEN bit */
  145. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
  146. /* Set the PMC1ON bit */
  147. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
  148. }
  149. #endif
  150. void s_init(void)
  151. {
  152. /* Disable wdog */
  153. init_wdog();
  154. /* clock configuration. */
  155. clock_init();
  156. if (soc_rev() < CHIP_REV_2_0) {
  157. /* enable dumb pmic */
  158. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  159. }
  160. #if defined(CONFIG_LDO_ENABLED_MODE)
  161. init_ldo_mode();
  162. #endif
  163. return;
  164. }
  165. #endif
  166. #ifndef CONFIG_ULP_WATCHDOG
  167. void reset_cpu(void)
  168. {
  169. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  170. while (1)
  171. ;
  172. }
  173. #endif
  174. #if defined(CONFIG_DISPLAY_CPUINFO)
  175. const char *get_imx_type(u32 imxtype)
  176. {
  177. return "7ULP";
  178. }
  179. int print_cpuinfo(void)
  180. {
  181. u32 cpurev;
  182. char cause[18];
  183. cpurev = get_cpu_rev();
  184. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  185. get_imx_type((cpurev & 0xFF000) >> 12),
  186. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  187. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  188. printf("Reset cause: %s\n", get_reset_cause(cause));
  189. printf("Boot mode: ");
  190. switch (get_boot_mode()) {
  191. case LOW_POWER_BOOT:
  192. printf("Low power boot\n");
  193. break;
  194. case DUAL_BOOT:
  195. printf("Dual boot\n");
  196. break;
  197. case SINGLE_BOOT:
  198. default:
  199. printf("Single boot\n");
  200. break;
  201. }
  202. if (ldo_mode_is_enabled())
  203. printf("PMC1: LDO enabled mode\n");
  204. else
  205. printf("PMC1: LDO bypass mode\n");
  206. return 0;
  207. }
  208. #endif
  209. #define CMC_SRS_TAMPER (1 << 31)
  210. #define CMC_SRS_SECURITY (1 << 30)
  211. #define CMC_SRS_TZWDG (1 << 29)
  212. #define CMC_SRS_JTAG_RST (1 << 28)
  213. #define CMC_SRS_CORE1 (1 << 16)
  214. #define CMC_SRS_LOCKUP (1 << 15)
  215. #define CMC_SRS_SW (1 << 14)
  216. #define CMC_SRS_WDG (1 << 13)
  217. #define CMC_SRS_PIN_RESET (1 << 8)
  218. #define CMC_SRS_WARM (1 << 4)
  219. #define CMC_SRS_HVD (1 << 3)
  220. #define CMC_SRS_LVD (1 << 2)
  221. #define CMC_SRS_POR (1 << 1)
  222. #define CMC_SRS_WUP (1 << 0)
  223. static u32 reset_cause = -1;
  224. static char *get_reset_cause(char *ret)
  225. {
  226. u32 cause1, cause = 0, srs = 0;
  227. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  228. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  229. if (!ret)
  230. return "null";
  231. srs = readl(reg_srs);
  232. cause1 = readl(reg_ssrs);
  233. writel(cause1, reg_ssrs);
  234. reset_cause = cause1;
  235. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  236. switch (cause) {
  237. case CMC_SRS_POR:
  238. sprintf(ret, "%s", "POR");
  239. break;
  240. case CMC_SRS_WUP:
  241. sprintf(ret, "%s", "WUP");
  242. break;
  243. case CMC_SRS_WARM:
  244. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  245. CMC_SRS_JTAG_RST);
  246. switch (cause) {
  247. case CMC_SRS_WDG:
  248. sprintf(ret, "%s", "WARM-WDG");
  249. break;
  250. case CMC_SRS_SW:
  251. sprintf(ret, "%s", "WARM-SW");
  252. break;
  253. case CMC_SRS_JTAG_RST:
  254. sprintf(ret, "%s", "WARM-JTAG");
  255. break;
  256. default:
  257. sprintf(ret, "%s", "WARM-UNKN");
  258. break;
  259. }
  260. break;
  261. default:
  262. sprintf(ret, "%s-%X", "UNKN", cause1);
  263. break;
  264. }
  265. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  266. return ret;
  267. }
  268. #ifdef CONFIG_ENV_IS_IN_MMC
  269. __weak int board_mmc_get_env_dev(int devno)
  270. {
  271. return CONFIG_SYS_MMC_ENV_DEV;
  272. }
  273. int mmc_get_env_dev(void)
  274. {
  275. int devno = 0;
  276. u32 bt1_cfg = 0;
  277. /* If not boot from sd/mmc, use default value */
  278. if (get_boot_mode() == LOW_POWER_BOOT)
  279. return CONFIG_SYS_MMC_ENV_DEV;
  280. bt1_cfg = readl(CMC1_RBASE + 0x40);
  281. devno = (bt1_cfg >> 9) & 0x7;
  282. return board_mmc_get_env_dev(devno);
  283. }
  284. #endif
  285. enum boot_device get_boot_device(void)
  286. {
  287. struct bootrom_sw_info **p =
  288. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  289. enum boot_device boot_dev = SD1_BOOT;
  290. u8 boot_type = (*p)->boot_dev_type;
  291. u8 boot_instance = (*p)->boot_dev_instance;
  292. switch (boot_type) {
  293. case BOOT_TYPE_SD:
  294. boot_dev = boot_instance + SD1_BOOT;
  295. break;
  296. case BOOT_TYPE_MMC:
  297. boot_dev = boot_instance + MMC1_BOOT;
  298. break;
  299. case BOOT_TYPE_USB:
  300. boot_dev = USB_BOOT;
  301. break;
  302. default:
  303. break;
  304. }
  305. return boot_dev;
  306. }