pxa2xx.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Alex Zuepke <azu@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <irq_func.h>
  15. #include <asm/arch/pxa-regs.h>
  16. #include <asm/cache.h>
  17. #include <asm/io.h>
  18. #include <asm/system.h>
  19. #include <command.h>
  20. /* Flush I/D-cache */
  21. static void cache_flush(void)
  22. {
  23. unsigned long i = 0;
  24. asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
  25. }
  26. int cleanup_before_linux(void)
  27. {
  28. /*
  29. * This function is called just before we call Linux. It prepares
  30. * the processor for Linux by just disabling everything that can
  31. * disturb booting Linux.
  32. */
  33. disable_interrupts();
  34. icache_disable();
  35. dcache_disable();
  36. cache_flush();
  37. return 0;
  38. }
  39. inline void writelrb(uint32_t val, uint32_t addr)
  40. {
  41. writel(val, addr);
  42. asm volatile("" : : : "memory");
  43. readl(addr);
  44. asm volatile("" : : : "memory");
  45. }
  46. void pxa2xx_dram_init(void)
  47. {
  48. uint32_t tmp;
  49. int i;
  50. /*
  51. * 1) Initialize Asynchronous static memory controller
  52. */
  53. writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
  54. writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
  55. writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
  56. /*
  57. * 2) Initialize Card Interface
  58. */
  59. /* MECR: Memory Expansion Card Register */
  60. writelrb(CONFIG_SYS_MECR_VAL, MECR);
  61. /* MCMEM0: Card Interface slot 0 timing */
  62. writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
  63. /* MCMEM1: Card Interface slot 1 timing */
  64. writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
  65. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  66. writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
  67. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  68. writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
  69. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  70. writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
  71. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  72. writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
  73. /*
  74. * 3) Configure Fly-By DMA register
  75. */
  76. writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
  77. /*
  78. * 4) Initialize Timing for Sync Memory (SDCLK0)
  79. */
  80. /*
  81. * Before accessing MDREFR we need a valid DRI field, so we set
  82. * this to power on defaults + DRI field.
  83. */
  84. /* Read current MDREFR config and zero out DRI */
  85. tmp = readl(MDREFR) & ~0xfff;
  86. /* Add user-specified DRI */
  87. tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
  88. /* Configure important bits */
  89. tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
  90. tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
  91. /* Write MDREFR back */
  92. writelrb(tmp, MDREFR);
  93. /*
  94. * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
  95. */
  96. /* Initialize SXCNFG register. Assert the enable bits.
  97. *
  98. * Write SXMRS to cause an MRS command to all enabled banks of
  99. * synchronous static memory. Note that SXLCR need not be written
  100. * at this time.
  101. */
  102. writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
  103. /*
  104. * 6) Initialize SDRAM
  105. */
  106. writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
  107. writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
  108. /*
  109. * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
  110. * but not enable each SDRAM partition pair.
  111. */
  112. writelrb(CONFIG_SYS_MDCNFG_VAL &
  113. ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
  114. /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
  115. writel(0, OSCR);
  116. while (readl(OSCR) < 0x300)
  117. asm volatile("" : : : "memory");
  118. /*
  119. * 8) Trigger a number (usually 8) refresh cycles by attempting
  120. * non-burst read or write accesses to disabled SDRAM, as commonly
  121. * specified in the power up sequence documented in SDRAM data
  122. * sheets. The address(es) used for this purpose must not be
  123. * cacheable.
  124. */
  125. for (i = 9; i >= 0; i--) {
  126. writel(i, 0xa0000000);
  127. asm volatile("" : : : "memory");
  128. }
  129. /*
  130. * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
  131. */
  132. tmp = CONFIG_SYS_MDCNFG_VAL &
  133. (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
  134. tmp |= readl(MDCNFG);
  135. writelrb(tmp, MDCNFG);
  136. /*
  137. * 10) Write MDMRS.
  138. */
  139. writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
  140. /*
  141. * 11) Enable APD
  142. */
  143. if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
  144. tmp = readl(MDREFR);
  145. tmp |= MDREFR_APD;
  146. writelrb(tmp, MDREFR);
  147. }
  148. }
  149. void pxa_gpio_setup(void)
  150. {
  151. writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
  152. writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
  153. writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
  154. #if defined(CONFIG_CPU_PXA27X)
  155. writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
  156. #endif
  157. writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
  158. writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
  159. writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
  160. #if defined(CONFIG_CPU_PXA27X)
  161. writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
  162. #endif
  163. writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
  164. writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
  165. writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
  166. #if defined(CONFIG_CPU_PXA27X)
  167. writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
  168. #endif
  169. writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
  170. writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
  171. writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
  172. writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
  173. writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
  174. writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
  175. #if defined(CONFIG_CPU_PXA27X)
  176. writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
  177. writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
  178. #endif
  179. writel(CONFIG_SYS_PSSR_VAL, PSSR);
  180. }
  181. void pxa_interrupt_setup(void)
  182. {
  183. writel(0, ICLR);
  184. writel(0, ICMR);
  185. #if defined(CONFIG_CPU_PXA27X)
  186. writel(0, ICLR2);
  187. writel(0, ICMR2);
  188. #endif
  189. }
  190. void pxa_clock_setup(void)
  191. {
  192. writel(CONFIG_SYS_CKEN, CKEN);
  193. writel(CONFIG_SYS_CCCR, CCCR);
  194. asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
  195. /* enable the 32Khz oscillator for RTC and PowerManager */
  196. writel(OSCC_OON, OSCC);
  197. while (!(readl(OSCC) & OSCC_OOK))
  198. asm volatile("" : : : "memory");
  199. }
  200. void pxa_wakeup(void)
  201. {
  202. uint32_t rcsr;
  203. rcsr = readl(RCSR);
  204. writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
  205. /* Wakeup */
  206. if (rcsr & RCSR_SMR) {
  207. writel(PSSR_PH, PSSR);
  208. pxa2xx_dram_init();
  209. icache_disable();
  210. dcache_disable();
  211. asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
  212. }
  213. }
  214. int arch_cpu_init(void)
  215. {
  216. pxa_gpio_setup();
  217. pxa_wakeup();
  218. pxa_interrupt_setup();
  219. pxa_clock_setup();
  220. return 0;
  221. }
  222. void i2c_clk_enable(void)
  223. {
  224. /* Set the global I2C clock on */
  225. writel(readl(CKEN) | CKEN14_I2C, CKEN);
  226. }
  227. void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
  228. void reset_cpu(void)
  229. {
  230. uint32_t tmp;
  231. setbits_le32(OWER, OWER_WME);
  232. tmp = readl(OSCR);
  233. tmp += 0x1000;
  234. writel(tmp, OSMR3);
  235. writel(MDREFR_SLFRSH, MDREFR);
  236. for (;;)
  237. ;
  238. }
  239. void enable_caches(void)
  240. {
  241. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  242. icache_enable();
  243. #endif
  244. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  245. dcache_enable();
  246. #endif
  247. }