README.p1010rdb 6.2 KB

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  1. Overview
  2. =========
  3. The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
  4. The P1010 is a cost-effective, low-power, highly integrated host processor
  5. based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
  6. that addresses the requirements of several routing, gateways, storage, consumer,
  7. and industrial applications. Applications of interest include the main CPUs and
  8. I/O processors in network attached storage (NAS), the voice over IP (VoIP)
  9. router/gateway, and wireless LAN (WLAN) and industrial controllers.
  10. The P1010RDB board features are as follows:
  11. Memory subsystem:
  12. - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
  13. - 32 Mbyte NOR flash single-chip memory
  14. - 32 Mbyte NAND flash memory
  15. - 256 Kbit M24256 I2C EEPROM
  16. - 16 Mbyte SPI memory
  17. - I2C Board EEPROM 128x8 bit memory
  18. - SD/MMC connector to interface with the SD memory card
  19. Interfaces:
  20. - PCIe:
  21. - Lane0: x1 mini-PCIe slot
  22. - Lane1: x1 PCIe standard slot
  23. - SATA:
  24. - 1 internal SATA connector to 2.5" 160G SATA2 HDD
  25. - 1 eSATA connector to rear panel
  26. - 10/100/1000 BaseT Ethernet ports:
  27. - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
  28. - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
  29. - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
  30. - USB 2.0 port:
  31. - x1 USB2.0 port: via an ULPI PHY to micro-AB connector
  32. - x1 USB2.0 poort via an internal PHY to micro-AB connector
  33. - FlexCAN ports:
  34. - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
  35. interface;
  36. - DUART interface:
  37. - DUART interface: supports two UARTs up to 115200 bps for
  38. console display
  39. - J45 connectors are used for these 2 UART ports.
  40. - TDM
  41. - 2 FXS ports connected via an external SLIC to the TDM
  42. interface. SLIC is controllled via SPI.
  43. - 1 FXO port connected via a relay to FXS for switchover to
  44. POTS
  45. Board connectors:
  46. - Mini-ITX power supply connector
  47. - JTAG/COP for debugging
  48. IEEE Std. 1588 signals for test and measurement
  49. Real-time clock on I2C bus
  50. POR
  51. - support critical POR setting changed via switch on board
  52. PCB
  53. - 6-layer routing (4-layer signals, 2-layer power and ground)
  54. Serial Port Configuration on P1010RDB
  55. =====================================
  56. Configure the serial port of the attached computer with the following values:
  57. -Data rate: 115200 bps
  58. -Number of data bits: 8
  59. -Parity: None
  60. -Number of Stop bits: 1
  61. -Flow Control: Hardware/None
  62. Settings of DIP-switch
  63. ======================
  64. SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
  65. SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
  66. SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
  67. Note: 1 stands for 'on', 0 stands for 'off'
  68. Setting of hwconfig
  69. ===================
  70. If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
  71. "fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
  72. setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
  73. By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
  74. is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
  75. instead of to CAN/UART1.
  76. Build and burn u-boot to NOR flash
  77. ==================================
  78. 1. Build u-boot.bin image
  79. export ARCH=powerpc
  80. export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
  81. make P1010RDB_NOR
  82. 2. Burn u-boot.bin into NOR flash
  83. => tftp $loadaddr $uboot
  84. => protect off eff80000 +$filesize
  85. => erase eff80000 +$filesize
  86. => cp.b $loadaddr eff80000 $filesize
  87. 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
  88. Alternate NOR bank
  89. ============================
  90. 1. Burn u-boot.bin into alternate NOR bank
  91. => tftp $loadaddr $uboot
  92. => protect off eef80000 +$filesize
  93. => erase eef80000 +$filesize
  94. => cp.b $loadaddr eef80000 $filesize
  95. 2. Switch to alternate NOR bank
  96. => mw.b ffb00009 1
  97. => reset
  98. or set SW1[8]= ON
  99. SW1[8]= OFF: Upper bank used for booting start
  100. SW1[8]= ON: Lower bank used for booting start
  101. CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
  102. 0 - boot from upper 4 sectors
  103. 1 - boot from lower 4 sectors
  104. Build and burn u-boot to NAND flash
  105. ===================================
  106. 1. Build u-boot.bin image
  107. export ARCH=powerpc
  108. export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
  109. make P1010RDB_NAND
  110. 2. Burn u-boot-nand.bin into NAND flash
  111. => tftp $loadaddr $uboot-nand
  112. => nand erase 0 $filesize
  113. => nand write $loadaddr 0 $filesize
  114. 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
  115. Build and burn u-boot to SPI flash
  116. ==================================
  117. 1. Build u-boot-spi.bin image
  118. make P1010RDB_SPIFLASH_config; make
  119. Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
  120. Download u-boot.bin to linux and you can find some config files
  121. under /usr/share such as config_xx.dat. Do below command:
  122. boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
  123. u-boot-spi.bin
  124. to generate u-boot-spi.bin.
  125. 2. Burn u-boot-spi.bin into SPI flash
  126. => tftp $loadaddr $uboot-spi
  127. => sf erase 0 100000
  128. => sf write $loadaddr 0 $filesize
  129. 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
  130. CPLD POR setting registers
  131. ==========================
  132. 1. Set POR switch selection register (addr 0xFFB00011) to 0.
  133. 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
  134. proper values.
  135. If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
  136. switch command by I2C.
  137. 3. Send reset command.
  138. After reset, the new POR setting will be implemented.
  139. Two examples are given in below:
  140. Switch from NOR to NAND boot with default frequency:
  141. => i2c dev 0
  142. => i2c mw 18 1 f9
  143. => i2c mw 18 3 f0
  144. => mw.b ffb00011 0
  145. => mw.b ffb00017 1
  146. => reset
  147. Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
  148. => i2c dev 0
  149. => i2c mw 18 1 f1
  150. => i2c mw 18 3 f0
  151. => mw.b ffb00011 0
  152. => mw.b ffb00014 2
  153. => mw.b ffb00015 5
  154. => mw.b ffb00016 3
  155. => mw.b ffb00017 f
  156. => reset
  157. Boot Linux from network using TFTP on P1010RDB
  158. ==============================================
  159. Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
  160. => tftp 1000000 uImage
  161. => tftp 2000000 p1010rdb.dtb
  162. => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
  163. => bootm 1000000 3000000 2000000
  164. Please contact your local field applications engineer or sales representative
  165. to obtain related documents, such as P1010-RDB User Guide for details.