README.fsl-ddr 21 KB

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  1. Table of interleaving 2-4 controllers
  2. =====================================
  3. +--------------+-----------------------------------------------------------+
  4. |Configuration | Memory Controller |
  5. | | 1 2 3 4 |
  6. |--------------+--------------+--------------+-----------------------------+
  7. | Two memory | Not Intlv'ed | Not Intlv'ed | |
  8. | complexes +--------------+--------------+ |
  9. | | 2-way Intlv'ed | |
  10. |--------------+--------------+--------------+--------------+ |
  11. | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
  12. | Three memory +--------------+--------------+--------------+ |
  13. | complexes | 2-way Intlv'ed | Not Intlv'ed | |
  14. | +-----------------------------+--------------+ |
  15. | | 3-way Intlv'ed | |
  16. +--------------+--------------+--------------+--------------+--------------+
  17. | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
  18. | Four memory +--------------+--------------+--------------+--------------+
  19. | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
  20. | +-----------------------------+-----------------------------+
  21. | | 4-way Intlv'ed |
  22. +--------------+-----------------------------------------------------------+
  23. Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
  24. ======================================================
  25. +-------------+---------------------------------------------------------+
  26. | | Rank Interleaving |
  27. | +--------+-----------+-----------+------------+-----------+
  28. |Memory | | | | 2x2 | 4x1 |
  29. |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  30. |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
  31. +-------------+--------+-----------+-----------+------------+-----------+
  32. |None | Yes | Yes | Yes | Yes | Yes |
  33. +-------------+--------+-----------+-----------+------------+-----------+
  34. |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
  35. | |CS0 Only| | | {CS0+CS1} | |
  36. +-------------+--------+-----------+-----------+------------+-----------+
  37. |Page | Yes | Yes | No | No, Only(*)| Yes |
  38. | |CS0 Only| | | {CS0+CS1} | |
  39. +-------------+--------+-----------+-----------+------------+-----------+
  40. |Bank | Yes | Yes | No | No, Only(*)| Yes |
  41. | |CS0 Only| | | {CS0+CS1} | |
  42. +-------------+--------+-----------+-----------+------------+-----------+
  43. |Superbank | No | Yes | No | No, Only(*)| Yes |
  44. | | | | | {CS0+CS1} | |
  45. +-------------+--------+-----------+-----------+------------+-----------+
  46. (*) Although the hardware can be configured with memory controller
  47. interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
  48. from each controller. {CS2+CS3} on each controller are only rank
  49. interleaved on that controller.
  50. For memory controller interleaving, identical DIMMs are suggested. Software
  51. doesn't check the size or organization of interleaved DIMMs.
  52. The ways to configure the ddr interleaving mode
  53. ==============================================
  54. 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
  55. under "CONFIG_EXTRA_ENV_SETTINGS", like:
  56. #define CONFIG_EXTRA_ENV_SETTINGS \
  57. "hwconfig=fsl_ddr:ctlr_intlv=bank" \
  58. ......
  59. 2. Run u-boot "setenv" command to configure the memory interleaving mode.
  60. Either numerical or string value is accepted.
  61. # disable memory controller interleaving
  62. setenv hwconfig "fsl_ddr:ctlr_intlv=null"
  63. # cacheline interleaving
  64. setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
  65. # page interleaving
  66. setenv hwconfig "fsl_ddr:ctlr_intlv=page"
  67. # bank interleaving
  68. setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
  69. # superbank
  70. setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
  71. # 1KB 3-way interleaving
  72. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
  73. # 4KB 3-way interleaving
  74. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
  75. # 8KB 3-way interleaving
  76. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
  77. # disable bank (chip-select) interleaving
  78. setenv hwconfig "fsl_ddr:bank_intlv=null"
  79. # bank(chip-select) interleaving cs0+cs1
  80. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
  81. # bank(chip-select) interleaving cs2+cs3
  82. setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
  83. # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
  84. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
  85. # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
  86. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
  87. # bank(chip-select) interleaving (auto)
  88. setenv hwconfig "fsl_ddr:bank_intlv=auto"
  89. This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
  90. on DIMMs.
  91. Memory controller address hashing
  92. ==================================
  93. If the DDR controller supports address hashing, it can be enabled by hwconfig.
  94. Syntax is:
  95. hwconfig=fsl_ddr:addr_hash=true
  96. Memory controller ECC on/off
  97. ============================
  98. If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
  99. ECC can be turned on/off by hwconfig.
  100. Syntax is
  101. hwconfig=fsl_ddr:ecc=off
  102. Memory testing options for mpc85xx
  103. ==================================
  104. 1. Memory test can be done once U-boot prompt comes up using mtest, or
  105. 2. Memory test can be done with Power-On-Self-Test function, activated at
  106. compile time.
  107. In order to enable the POST memory test, CONFIG_POST needs to be
  108. defined in board configuraiton header file. By default, POST memory test
  109. performs a fast test. A slow test can be enabled by changing the flag at
  110. compiling time. To test memory bigger than 2GB, 36BIT support is needed.
  111. Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
  112. window to physical address so that all physical memory can be tested.
  113. Combination of hwconfig
  114. =======================
  115. Hwconfig can be combined with multiple parameters, for example, on a supported
  116. platform
  117. hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
  118. Table for dynamic ODT for DDR3
  119. ==============================
  120. For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
  121. be needed, depending on the configuration. The numbers in the following tables are
  122. in Ohms.
  123. * denotes dynamic ODT
  124. Two slots system
  125. +-----------------------+----------+---------------+-----------------------------+-----------------------------+
  126. | Configuration | |DRAM controller| Slot 1 | Slot 2 |
  127. +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
  128. | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
  129. + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
  130. | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
  131. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  132. | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
  133. | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  134. | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
  135. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  136. | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
  137. | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  138. | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
  139. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  140. | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
  141. |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  142. | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
  143. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  144. | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
  145. |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  146. | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
  147. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  148. | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
  149. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  150. | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
  151. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  152. |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
  153. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  154. | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
  155. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  156. Single slot system
  157. +-------------+------------+---------------+-----------------------------+-----------------------------+
  158. | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
  159. |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
  160. | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
  161. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  162. | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
  163. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  164. | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
  165. | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  166. | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
  167. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  168. | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
  169. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  170. | | R1 | off | 75 | 40 | off | off | off |
  171. | Dual Rank |------------+-------+-------+-------+------+-------+------+
  172. | | R2 | off | 75 | 40 | off | off | off |
  173. +-------------+------------+-------+-------+-------+------+-------+------+
  174. | Single Rank | R1 | off | 75 | 40 | off |
  175. +-------------+------------+-------+-------+-------+------+
  176. Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
  177. http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
  178. Table for ODT for DDR2
  179. ======================
  180. Two slots system
  181. +-----------------------+----------+---------------+-----------------------------+-----------------------------+
  182. | Configuration | |DRAM controller| Slot 1 | Slot 2 |
  183. +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
  184. | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
  185. + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
  186. | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
  187. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  188. | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
  189. | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  190. | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
  191. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  192. | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
  193. | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  194. | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
  195. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  196. | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
  197. |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  198. | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
  199. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  200. | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
  201. |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  202. | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
  203. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  204. | Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
  205. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  206. | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
  207. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  208. |Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
  209. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  210. | Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
  211. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  212. Single slot system
  213. +-------------+------------+---------------+-----------------------------+
  214. | | |DRAM controller| Rank 1 | Rank 2 |
  215. |Configuration| Write/Read |-------+-------+-------+------+-------+------+
  216. | | | Write | Read | Write | Read | Write | Read |
  217. +-------------+------------+-------+-------+-------+------+-------+------+
  218. | | R1 | off | 75 | 150 | off | off | off |
  219. | Dual Rank |------------+-------+-------+-------+------+-------+------+
  220. | | R2 | off | 75 | 150 | off | off | off |
  221. +-------------+------------+-------+-------+-------+------+-------+------+
  222. | Single Rank | R1 | off | 75 | 150 | off |
  223. +-------------+------------+-------+-------+-------+------+
  224. Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
  225. Interactive DDR debugging
  226. ===========================
  227. For DDR parameter tuning up and debugging, the interactive DDR debugger can
  228. be activated by setting the environment variable "ddr_interactive" to any
  229. value. (The value of ddr_interactive may have a meaning in the future, but,
  230. for now, the presence of the variable will cause the debugger to run.) Once
  231. activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR
  232. controller. The available commands are printed by typing "help".
  233. Another way to enter the interactive DDR debugger without setting the
  234. environment variable is to send the 'd' character early during the boot
  235. process. To save booting time, no additional delay is added, so the window
  236. to send the key press is very short -- basically, it is the time before the
  237. memory controller code starts to run. For example, when rebooting from
  238. within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to
  239. initiate a 'reset' command. In case of power on/reset, the user can hold
  240. down the 'd' key while applying power or hitting the board's reset button.
  241. The example flow of using interactive debugging is
  242. type command "compute" to calculate the parameters from the default
  243. type command "print" with arguments to show SPD, options, registers
  244. type command "edit" with arguments to change any if desired
  245. type command "copy" with arguments to copy controller/dimm settings
  246. type command "go" to continue calculation and enable DDR controller
  247. Additional commands to restart the debugging are:
  248. type command "reset" to reset the board
  249. type command "recompute" to reload SPD and start over
  250. Note, check "next_step" to show the flow. For example, after edit opts, the
  251. next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
  252. STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
  253. DDR controller with the current setting without further calculation and then
  254. exit to resume the booting of the machine.
  255. The detail syntax for each commands are
  256. print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
  257. c<n> - the controller number, eg. c0, c1
  258. d<n> - the DIMM number, eg. d0, d1
  259. spd - print SPD data
  260. dimmparms - DIMM parameters, calculated from SPD
  261. commonparms - lowest common parameters for all DIMMs
  262. opts - options
  263. addresses - address assignment (not implemented yet)
  264. regs - controller registers
  265. edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
  266. c<n> - the controller number, eg. c0, c1
  267. d<n> - the DIMM number, eg. d0, d1
  268. spd - print SPD data
  269. dimmparms - DIMM parameters, calculated from SPD
  270. commonparms - lowest common parameters for all DIMMs
  271. opts - options
  272. addresses - address assignment (not implemented yet)
  273. regs - controller registers
  274. <element> - name of the modified element
  275. byte number if the object is SPD
  276. <value> - decimal or heximal (prefixed with 0x) numbers
  277. copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
  278. same as for "edit" command
  279. DIMM numbers ignored for commonparms, opts, and regs
  280. reset
  281. no arguement - reset the board
  282. recompute
  283. no argument - reload SPD and start over
  284. compute
  285. no argument - recompute from current next_step
  286. next_step
  287. no argument - show current next_step
  288. help
  289. no argument - print a list of all commands
  290. go
  291. no argument - program memory controller(s) and continue with U-boot
  292. Examples of debugging flow
  293. FSL DDR>compute
  294. Detected UDIMM UG51U6400N8SU-ACF
  295. FSL DDR>print
  296. print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
  297. FSL DDR>print dimmparms
  298. DIMM parameters: Controller=0 DIMM=0
  299. DIMM organization parameters:
  300. module part name = UG51U6400N8SU-ACF
  301. rank_density = 2147483648 bytes (2048 megabytes)
  302. capacity = 4294967296 bytes (4096 megabytes)
  303. burst_lengths_bitmask = 0C
  304. base_addresss = 0 (00000000 00000000)
  305. n_ranks = 2
  306. data_width = 64
  307. primary_sdram_width = 64
  308. ec_sdram_width = 0
  309. registered_dimm = 0
  310. n_row_addr = 15
  311. n_col_addr = 10
  312. edc_config = 0
  313. n_banks_per_sdram_device = 8
  314. tCKmin_X_ps = 1500
  315. tCKmin_X_minus_1_ps = 0
  316. tCKmin_X_minus_2_ps = 0
  317. tCKmax_ps = 0
  318. caslat_X = 960
  319. tAA_ps = 13125
  320. caslat_X_minus_1 = 0
  321. caslat_X_minus_2 = 0
  322. caslat_lowest_derated = 0
  323. tRCD_ps = 13125
  324. tRP_ps = 13125
  325. tRAS_ps = 36000
  326. tWR_ps = 15000
  327. tWTR_ps = 7500
  328. tRFC_ps = 160000
  329. tRRD_ps = 6000
  330. tRC_ps = 49125
  331. refresh_rate_ps = 7800000
  332. tIS_ps = 0
  333. tIH_ps = 0
  334. tDS_ps = 0
  335. tDH_ps = 0
  336. tRTP_ps = 7500
  337. tDQSQ_max_ps = 0
  338. tQHS_ps = 0
  339. FSL DDR>edit c0 opts ECC_mode 0
  340. FSL DDR>edit c0 regs cs0_bnds 0x000000FF
  341. FSL DDR>go
  342. 2 GiB left unmapped
  343. 4 GiB (DDR3, 64-bit, CL=9, ECC off)
  344. DDR Chip-Select Interleaving Mode: CS0+CS1
  345. Testing 0x00000000 - 0x7fffffff
  346. Testing 0x80000000 - 0xffffffff
  347. Remap DDR 2 GiB left unmapped
  348. POST memory PASSED
  349. Flash: 128 MiB
  350. L2: 128 KB enabled
  351. Corenet Platform Cache: 1024 KB enabled
  352. SERDES: timeout resetting bank 3
  353. SRIO1: disabled
  354. SRIO2: disabled
  355. MMC: FSL_ESDHC: 0
  356. EEPROM: Invalid ID (ff ff ff ff)
  357. PCIe1: disabled
  358. PCIe2: Root Complex, x1, regs @ 0xfe201000
  359. 01:00.0 - 8086:10d3 - Network controller
  360. PCIe2: Bus 00 - 01
  361. PCIe3: disabled
  362. In: serial
  363. Out: serial
  364. Err: serial
  365. Net: Initializing Fman
  366. Fman1: Uploading microcode version 101.8.0
  367. e1000: 00:1b:21:81:d2:e0
  368. FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
  369. Warning: e1000#0 MAC addresses don't match:
  370. Address in SROM is 00:1b:21:81:d2:e0
  371. Address in environment is 00:e0:0c:00:ea:05
  372. Hit any key to stop autoboot: 0
  373. =>