digsy_mtc.h 14 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2005-2007
  6. * Modified for InterControl digsyMTC MPC5200 board by
  7. * Frank Bodammer, GCD Hard- & Software GmbH,
  8. * frank.bodammer@gcd-solutions.de
  9. *
  10. * (C) Copyright 2009 Semihalf
  11. * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software\; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation\; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY\; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program\; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. #ifndef __CONFIG_H
  32. #define __CONFIG_H
  33. /*
  34. * High Level Configuration Options
  35. */
  36. #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  37. #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
  38. #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
  39. /*
  40. * Valid values for CONFIG_SYS_TEXT_BASE are:
  41. * 0xFFF00000 boot high (standard configuration)
  42. * 0xFE000000 boot low
  43. * 0x00100000 boot from RAM (for testing only)
  44. */
  45. #ifndef CONFIG_SYS_TEXT_BASE
  46. #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
  47. #endif
  48. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
  49. #define CONFIG_SYS_CACHELINE_SIZE 32
  50. /*
  51. * Serial console configuration
  52. */
  53. #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
  54. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  55. #define CONFIG_SYS_BAUDRATE_TABLE \
  56. { 9600, 19200, 38400, 57600, 115200, 230400 }
  57. /*
  58. * PCI Mapping:
  59. * 0x40000000 - 0x4fffffff - PCI Memory
  60. * 0x50000000 - 0x50ffffff - PCI IO Space
  61. */
  62. #define CONFIG_PCI 1
  63. #define CONFIG_PCI_PNP 1
  64. #define CONFIG_PCI_SCAN_SHOW 1
  65. #define CONFIG_PCI_MEM_BUS 0x40000000
  66. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  67. #define CONFIG_PCI_MEM_SIZE 0x10000000
  68. #define CONFIG_PCI_IO_BUS 0x50000000
  69. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  70. #define CONFIG_PCI_IO_SIZE 0x01000000
  71. /*
  72. * Partitions
  73. */
  74. #define CONFIG_DOS_PARTITION
  75. #define CONFIG_BZIP2
  76. /*
  77. * Video
  78. */
  79. #define CONFIG_VIDEO
  80. #ifdef CONFIG_VIDEO
  81. #define CONFIG_VIDEO_MB862xx
  82. #define CONFIG_VIDEO_MB862xx_ACCEL
  83. #define CONFIG_VIDEO_CORALP
  84. #define CONFIG_CFB_CONSOLE
  85. #define CONFIG_VIDEO_LOGO
  86. #define CONFIG_VIDEO_BMP_LOGO
  87. #define CONFIG_VIDEO_SW_CURSOR
  88. #define CONFIG_VGA_AS_SINGLE_DEVICE
  89. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  90. #define CONFIG_SPLASH_SCREEN
  91. #define CONFIG_VIDEO_BMP_GZIP
  92. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
  93. /* Coral-PA clock frequency, geo and other both 133MHz */
  94. #define CONFIG_SYS_MB862xx_CCF 0x00050000
  95. /* Video SDRAM parameters */
  96. #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
  97. #endif
  98. /*
  99. * Command line configuration.
  100. */
  101. #include <config_cmd_default.h>
  102. #ifdef CONFIG_VIDEO
  103. #define CONFIG_CMD_BMP
  104. #endif
  105. #define CONFIG_CMD_DFL
  106. #define CONFIG_CMD_CACHE
  107. #define CONFIG_CMD_DATE
  108. #define CONFIG_CMD_DHCP
  109. #define CONFIG_CMD_DIAG
  110. #define CONFIG_CMD_EEPROM
  111. #define CONFIG_CMD_ELF
  112. #define CONFIG_CMD_EXT2
  113. #define CONFIG_CMD_FAT
  114. #define CONFIG_CMD_I2C
  115. #define CONFIG_CMD_IDE
  116. #define CONFIG_CMD_IRQ
  117. #define CONFIG_CMD_MII
  118. #define CONFIG_CMD_PCI
  119. #define CONFIG_CMD_PING
  120. #define CONFIG_CMD_REGINFO
  121. #define CONFIG_CMD_SAVES
  122. #define CONFIG_CMD_SPI
  123. #define CONFIG_CMD_USB
  124. #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
  125. #define CONFIG_SYS_LOWBOOT 1
  126. #endif
  127. /*
  128. * Autobooting
  129. */
  130. #define CONFIG_BOOTDELAY 1
  131. #undef CONFIG_BOOTARGS
  132. #define CONFIG_EXTRA_ENV_SETTINGS \
  133. "fw_image=digsyMPC.img\0" \
  134. "mtcb_start=mtc led diag orange; run mtcb_1\0" \
  135. "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
  136. "do mtc led $x; done\0" \
  137. "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
  138. "else run mtcb_fw; fi\0" \
  139. "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
  140. "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
  141. "mtcb_update=mtc led user1 orange;" \
  142. "while mtc key; do ; done; run mtcb_2;\0" \
  143. "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
  144. "mtcb_usb1=if fatload usb 0 400000 script.img; " \
  145. "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
  146. "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
  147. "then run mtcb_dousb; else run mtcb_ide; fi\0" \
  148. "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
  149. "run mtcb_wait_flickr mtcb_ds_1;\0" \
  150. "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
  151. "source 400000; else run mtcb_error; fi\0" \
  152. "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
  153. "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
  154. "else run mtcb_error; fi\0" \
  155. "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
  156. "run mtcb_checkfw\0" \
  157. "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
  158. "else run mtcb_error; fi\0" \
  159. "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
  160. "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
  161. "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
  162. "mtcb_uledflckr=mtc led user1 orange 11\0" \
  163. "mtcb_error=mtc led user1 red\0" \
  164. "mtcb_clear=erase ff000000 ff0fffff\0" \
  165. "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
  166. "mtcb_success=mtc led user1 green\0" \
  167. "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
  168. "then run mtcb_doide; else run mtcb_error; fi\0" \
  169. "mtcb_doide=mtc led user2 green 1;" \
  170. "run mtcb_wait_flickr mtcb_di_1;\0" \
  171. "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
  172. "else run mtcb_error; fi\0" \
  173. "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
  174. "ramdisk_num_sector=16\0" \
  175. "flash_base=ff000000\0" \
  176. "flashdisk_size=e00000\0" \
  177. "env_sector=fff60000\0" \
  178. "flashdisk_start=ff100000\0" \
  179. "load_cmd=tftp 400000 digsyMPC.img\0" \
  180. "clear_cmd=erase ff000000 ff0fffff\0" \
  181. "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
  182. "update_cmd=run load_cmd; " \
  183. "iminfo 400000; " \
  184. "run clear_cmd flash_cmd; " \
  185. "iminfo ff000000\0" \
  186. "spi_driver=yes\0" \
  187. "spi_watchdog=no\0" \
  188. "ftps_start=yes\0" \
  189. "ftps_user1=admin\0" \
  190. "ftps_pass1=admin\0" \
  191. "ftps_base1=/\0" \
  192. "ftps_home1=/\0" \
  193. "plc_sio_srv=no\0" \
  194. "plc_sio_baud=57600\0" \
  195. "plc_sio_parity=no\0" \
  196. "plc_sio_stop=1\0" \
  197. "plc_sio_com=2\0" \
  198. "plc_eth_srv=yes\0" \
  199. "plc_eth_port=1200\0" \
  200. "plc_root=/ide/\0" \
  201. "diag_level=0\0" \
  202. "webvisu=no\0" \
  203. "plc_can1_routing=no\0" \
  204. "plc_can1_baudrate=250\0" \
  205. "plc_can2_routing=no\0" \
  206. "plc_can2_baudrate=250\0" \
  207. "plc_can3_routing=no\0" \
  208. "plc_can3_baudrate=250\0" \
  209. "plc_can4_routing=no\0" \
  210. "plc_can4_baudrate=250\0" \
  211. "netdev=eth0\0" \
  212. "console=ttyPSC0\0" \
  213. "kernel_addr_r=400000\0" \
  214. "fdt_addr_r=600000\0" \
  215. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  216. "nfsroot=${serverip}:${rootpath}\0" \
  217. "addip=setenv bootargs ${bootargs} " \
  218. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  219. "${netmask}:${hostname}:${netdev}:off panic=1\0" \
  220. "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
  221. "rootpath=/opt/eldk/ppc_6xx\0" \
  222. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  223. "tftp ${fdt_addr_r} ${fdt_file};" \
  224. "run nfsargs addip addcons;" \
  225. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  226. "load=tftp 200000 ${u-boot}\0" \
  227. "update=protect off FFF00000 +${filesize};" \
  228. "erase FFF00000 +${filesize};" \
  229. "cp.b 200000 FFF00000 ${filesize};" \
  230. "protect on FFF00000 +${filesize}\0" \
  231. ""
  232. #define CONFIG_BOOTCOMMAND "run mtcb_start"
  233. /*
  234. * SPI configuration
  235. */
  236. #define CONFIG_HARD_SPI 1
  237. #define CONFIG_MPC52XX_SPI 1
  238. /*
  239. * I2C configuration
  240. */
  241. #define CONFIG_HARD_I2C 1
  242. #define CONFIG_SYS_I2C_MODULE 1
  243. #define CONFIG_SYS_I2C_SPEED 100000
  244. #define CONFIG_SYS_I2C_SLAVE 0x7F
  245. /*
  246. * EEPROM configuration
  247. */
  248. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  249. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  250. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  251. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
  252. /*
  253. * RTC configuration
  254. */
  255. #if defined(CONFIG_DIGSY_REV5)
  256. #define CONFIG_SYS_I2C_RTC_ADDR 0x56
  257. #define CONFIG_RTC_RV3029
  258. /* Enable 5k Ohm trickle charge resistor */
  259. #define CONFIG_SYS_RV3029_TCR 0x20
  260. #else
  261. #define CONFIG_RTC_DS1337
  262. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  263. #define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
  264. #endif
  265. /*
  266. * Flash configuration
  267. */
  268. #define CONFIG_SYS_FLASH_CFI 1
  269. #define CONFIG_FLASH_CFI_DRIVER 1
  270. #if defined(CONFIG_DIGSY_REV5)
  271. #define CONFIG_SYS_FLASH_BASE 0xFE000000
  272. #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
  273. #define CONFIG_SYS_MAX_FLASH_BANKS 2
  274. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  275. CONFIG_SYS_FLASH_BASE_CS1}
  276. #define CONFIG_SYS_UPDATE_FLASH_SIZE
  277. #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
  278. #else
  279. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  280. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  281. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  282. #endif
  283. #define CONFIG_SYS_MAX_FLASH_SECT 256
  284. #define CONFIG_FLASH_16BIT
  285. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  286. #define CONFIG_SYS_FLASH_SIZE 0x01000000
  287. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
  288. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  289. #define CONFIG_OF_LIBFDT 1
  290. #define CONFIG_OF_BOARD_SETUP 1
  291. #define OF_CPU "PowerPC,5200@0"
  292. #define OF_SOC "soc5200@f0000000"
  293. #define OF_TBCLK (bd->bi_busfreq / 4)
  294. #define CONFIG_BOARD_EARLY_INIT_R
  295. #define CONFIG_MISC_INIT_R
  296. /*
  297. * Environment settings
  298. */
  299. #define CONFIG_ENV_IS_IN_FLASH 1
  300. #if defined(CONFIG_LOWBOOT)
  301. #define CONFIG_ENV_ADDR 0xFF060000
  302. #else /* CONFIG_LOWBOOT */
  303. #define CONFIG_ENV_ADDR 0xFFF60000
  304. #endif /* CONFIG_LOWBOOT */
  305. #define CONFIG_ENV_SIZE 0x10000
  306. #define CONFIG_ENV_SECT_SIZE 0x20000
  307. #define CONFIG_ENV_OVERWRITE 1
  308. /*
  309. * Memory map
  310. */
  311. #define CONFIG_SYS_MBAR 0xF0000000
  312. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  313. #if !defined(CONFIG_SYS_LOWBOOT)
  314. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  315. #else
  316. #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
  317. #endif
  318. /*
  319. * Use SRAM until RAM will be available
  320. */
  321. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  322. #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
  323. #define CONFIG_SYS_GBL_DATA_OFFSET \
  324. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  325. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  326. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  327. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  328. #define CONFIG_SYS_RAMBOOT 1
  329. #endif
  330. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  331. #define CONFIG_SYS_MALLOC_LEN (4096 << 10)
  332. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  333. /*
  334. * Ethernet configuration
  335. */
  336. #define CONFIG_MPC5xxx_FEC 1
  337. #define CONFIG_MPC5xxx_FEC_MII100
  338. #if defined(CONFIG_DIGSY_REV5)
  339. #define CONFIG_PHY_ADDR 0x01
  340. #else
  341. #define CONFIG_PHY_ADDR 0x00
  342. #endif
  343. #define CONFIG_PHY_RESET_DELAY 1000
  344. #define CONFIG_NETCONSOLE /* include NetConsole support */
  345. /*
  346. * GPIO configuration
  347. * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
  348. * Bit 0 (mask 0x80000000) : 0x1
  349. * SPI on Tmr2/3/4/5 pins
  350. * Bit 2:3 (mask 0x30000000) : 0x2
  351. * ATA cs0/1 on csb_4/5
  352. * Bit 6:7 (mask 0x03000000) : 0x2
  353. * Ethernet 100Mbit with MD
  354. * Bits 12:15 (mask 0x000f0000): 0x5
  355. * USB - Two UARTs
  356. * Bits 18:19 (mask 0x00003000) : 0x2
  357. * PSC3 - USB2 on PSC3
  358. * Bits 20:23 (mask 0x00000f00) : 0x1
  359. * PSC2 - CAN1&2 on PSC2 pins
  360. * Bits 25:27 (mask 0x00000070) : 0x1
  361. * PSC1 - AC97 functionality
  362. * Bits 29:31 (mask 0x00000007) : 0x2
  363. */
  364. #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
  365. /*
  366. * Miscellaneous configurable options
  367. */
  368. #define CONFIG_SYS_LONGHELP
  369. #define CONFIG_AUTO_COMPLETE 1
  370. #define CONFIG_CMDLINE_EDITING 1
  371. #define CONFIG_SYS_PROMPT "=> "
  372. #define CONFIG_SYS_HUSH_PARSER
  373. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  374. #define CONFIG_AUTOBOOT_KEYED
  375. #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
  376. #define CONFIG_AUTOBOOT_DELAY_STR " "
  377. #define CONFIG_LOOPW 1
  378. #define CONFIG_MX_CYCLIC 1
  379. #define CONFIG_ZERO_BOOTDELAY_CHECK
  380. #define CONFIG_SYS_CBSIZE 1024
  381. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  382. #define CONFIG_SYS_MAXARGS 32
  383. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  384. #define CONFIG_SYS_ALT_MEMTEST
  385. #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
  386. #define CONFIG_SYS_MEMTEST_START 0x00010000
  387. #define CONFIG_SYS_MEMTEST_END 0x019fffff
  388. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  389. #define CONFIG_SYS_HZ 1000
  390. /*
  391. * Various low-level settings
  392. */
  393. #define CONFIG_SYS_SDRAM_CS1 1
  394. #define CONFIG_SYS_XLB_PIPELINING 1
  395. #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  396. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  397. #if defined(CONFIG_SYS_LOWBOOT)
  398. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  399. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  400. #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
  401. #endif
  402. #define CONFIG_SYS_CS4_START 0x60000000
  403. #define CONFIG_SYS_CS4_SIZE 0x1000
  404. #define CONFIG_SYS_CS4_CFG 0x0008FC00
  405. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  406. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  407. #define CONFIG_SYS_CS0_CFG 0x0002DD00
  408. #if defined(CONFIG_DIGSY_REV5)
  409. #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
  410. #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
  411. #define CONFIG_SYS_CS1_CFG 0x0002DD00
  412. #endif
  413. #define CONFIG_SYS_CS_BURST 0x00000000
  414. #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
  415. #if !defined(CONFIG_SYS_LOWBOOT)
  416. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  417. #else
  418. #define CONFIG_SYS_RESET_ADDRESS 0xff000100
  419. #endif
  420. /*
  421. * USB
  422. */
  423. #define CONFIG_USB_OHCI_NEW
  424. #define CONFIG_SYS_OHCI_BE_CONTROLLER
  425. #define CONFIG_USB_STORAGE
  426. #define CONFIG_USB_CLOCK 0x00013333
  427. #define CONFIG_USB_CONFIG 0x00002000
  428. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  429. #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
  430. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
  431. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  432. /*
  433. * IDE/ATA
  434. */
  435. #define CONFIG_IDE_RESET
  436. #define CONFIG_IDE_PREINIT
  437. #define CONFIG_SYS_ATA_CS_ON_I2C2
  438. #define CONFIG_SYS_IDE_MAXBUS 1
  439. #define CONFIG_SYS_IDE_MAXDEVICE 1
  440. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  441. #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
  442. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
  443. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  444. #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
  445. #define CONFIG_SYS_ATA_STRIDE 4
  446. #define CONFIG_ATAPI 1
  447. #define CONFIG_LBA48 1
  448. #endif /* __CONFIG_H */