digsy_mtc.c 13 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  7. *
  8. * (C) Copyright 2005-2009
  9. * Modified for InterControl digsyMTC MPC5200 board by
  10. * Frank Bodammer, GCD Hard- & Software GmbH,
  11. * frank.bodammer@gcd-solutions.de
  12. *
  13. * (C) Copyright 2009
  14. * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. */
  34. #include <common.h>
  35. #include <mpc5xxx.h>
  36. #include <net.h>
  37. #include <pci.h>
  38. #include <asm/processor.h>
  39. #include <asm/io.h>
  40. #include "eeprom.h"
  41. #if defined(CONFIG_DIGSY_REV5)
  42. #include "is45s16800a2.h"
  43. #include <mtd/cfi_flash.h>
  44. #include <flash.h>
  45. #else
  46. #include "is42s16800a-7t.h"
  47. #endif
  48. #include <libfdt.h>
  49. #include <fdt_support.h>
  50. #include <i2c.h>
  51. DECLARE_GLOBAL_DATA_PTR;
  52. extern int usb_cpu_init(void);
  53. #if defined(CONFIG_DIGSY_REV5)
  54. /*
  55. * The M29W128GH needs a specail reset command function,
  56. * details see the doc/README.cfi file
  57. */
  58. void flash_cmd_reset(flash_info_t *info)
  59. {
  60. flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
  61. }
  62. #endif
  63. #ifndef CONFIG_SYS_RAMBOOT
  64. static void sdram_start(int hi_addr)
  65. {
  66. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  67. long control = SDRAM_CONTROL | hi_addr_bit;
  68. /* unlock mode register */
  69. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  70. /* precharge all banks */
  71. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  72. /* auto refresh */
  73. out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  74. /* set mode register */
  75. out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  76. /* normal operation */
  77. out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  78. }
  79. #endif
  80. /*
  81. * ATTENTION: Although partially referenced initdram does NOT make real use
  82. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  83. * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  84. */
  85. phys_size_t initdram(int board_type)
  86. {
  87. ulong dramsize = 0;
  88. ulong dramsize2 = 0;
  89. uint svr, pvr;
  90. #ifndef CONFIG_SYS_RAMBOOT
  91. ulong test1, test2;
  92. /* setup SDRAM chip selects */
  93. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
  94. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
  95. /* setup config registers */
  96. out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  97. out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  98. /* find RAM size using SDRAM CS0 only */
  99. sdram_start(0);
  100. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  101. sdram_start(1);
  102. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  103. if (test1 > test2) {
  104. sdram_start(0);
  105. dramsize = test1;
  106. } else {
  107. dramsize = test2;
  108. }
  109. /* memory smaller than 1MB is impossible */
  110. if (dramsize < (1 << 20))
  111. dramsize = 0;
  112. /* set SDRAM CS0 size according to the amount of RAM found */
  113. if (dramsize > 0) {
  114. out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
  115. (0x13 + __builtin_ffs(dramsize >> 20) - 1));
  116. } else {
  117. out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
  118. }
  119. /* let SDRAM CS1 start right after CS0 */
  120. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
  121. /* find RAM size using SDRAM CS1 only */
  122. test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
  123. 0x08000000);
  124. dramsize2 = test1;
  125. /* memory smaller than 1MB is impossible */
  126. if (dramsize2 < (1 << 20))
  127. dramsize2 = 0;
  128. /* set SDRAM CS1 size according to the amount of RAM found */
  129. if (dramsize2 > 0) {
  130. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
  131. (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
  132. } else {
  133. out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
  134. }
  135. #else /* CONFIG_SYS_RAMBOOT */
  136. /* retrieve size of memory connected to SDRAM CS0 */
  137. dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
  138. if (dramsize >= 0x13)
  139. dramsize = (1 << (dramsize - 0x13)) << 20;
  140. else
  141. dramsize = 0;
  142. /* retrieve size of memory connected to SDRAM CS1 */
  143. dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
  144. if (dramsize2 >= 0x13)
  145. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  146. else
  147. dramsize2 = 0;
  148. #endif /* CONFIG_SYS_RAMBOOT */
  149. /*
  150. * On MPC5200B we need to set the special configuration delay in the
  151. * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
  152. * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
  153. *
  154. * "The SDelay should be written to a value of 0x00000004. It is
  155. * required to account for changes caused by normal wafer processing
  156. * parameters."
  157. */
  158. svr = get_svr();
  159. pvr = get_pvr();
  160. if ((SVR_MJREV(svr) >= 2) &&
  161. (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
  162. out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
  163. return dramsize + dramsize2;
  164. }
  165. int checkboard(void)
  166. {
  167. char buf[64];
  168. int i = getenv_f("serial#", buf, sizeof(buf));
  169. puts ("Board: InterControl digsyMTC");
  170. #if defined(CONFIG_DIGSY_REV5)
  171. puts (" rev5");
  172. #endif
  173. if (i > 0) {
  174. puts(", ");
  175. puts(buf);
  176. }
  177. putc('\n');
  178. return 0;
  179. }
  180. #if defined(CONFIG_VIDEO)
  181. #define GPIO_USB1_0 0x00010000 /* Power-On pin */
  182. #define GPIO_USB1_9 0x08 /* PX_~EN pin */
  183. #define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
  184. #define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
  185. #define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
  186. #define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
  187. #define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
  188. /* ExBo I2C Addresses */
  189. #define EXBO_EE_I2C_ADDRESS 0x56
  190. static void exbo_hw_init(void)
  191. {
  192. struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
  193. struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
  194. struct mpc5xxx_wu_gpio *wu_gpio =
  195. (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
  196. unsigned char val;
  197. /* 1st, check if extension board is present */
  198. if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1))
  199. return;
  200. /* configure IrDA pins (PSC6 port) as gpios */
  201. gpio->port_config &= 0xFF8FFFFF;
  202. /* Init for USB1_0, EE_CLK and EE_DI - Low */
  203. setbits_be32(&gpio->simple_ddr,
  204. GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
  205. clrbits_be32(&gpio->simple_ode,
  206. GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
  207. clrbits_be32(&gpio->simple_dvo,
  208. GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
  209. setbits_be32(&gpio->simple_gpioe,
  210. GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
  211. /* Init for EE_DO, EE_CTS - Input */
  212. clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
  213. setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
  214. /* Init for PX_~EN (USB1_9) - High */
  215. clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
  216. setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
  217. clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
  218. setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
  219. setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
  220. /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
  221. out_be32(&gpt[0].emsr, GPT_GPIO_ON);
  222. /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
  223. out_be32(&gpt[1].emsr, GPT_GPIO_ON);
  224. /* Power-On camera supply */
  225. setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
  226. }
  227. #else
  228. static inline void exbo_hw_init(void) {}
  229. #endif /* CONFIG_VIDEO */
  230. int board_early_init_r(void)
  231. {
  232. #ifdef CONFIG_MPC52XX_SPI
  233. struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
  234. #endif
  235. /*
  236. * Now, when we are in RAM, enable flash write access for detection
  237. * process. Note that CS_BOOT cannot be cleared when executing in
  238. * flash.
  239. */
  240. /* disable CS_BOOT */
  241. clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
  242. /* enable CS1 */
  243. setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
  244. /* enable CS0 */
  245. setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
  246. exbo_hw_init();
  247. #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
  248. /* Low level USB init, required for proper kernel operation */
  249. usb_cpu_init();
  250. #endif
  251. #ifdef CONFIG_MPC52XX_SPI
  252. /* GPT 6 Output Enable */
  253. out_be32(&gpt[6].emsr, 0x00000034);
  254. /* GPT 7 Output Enable */
  255. out_be32(&gpt[7].emsr, 0x00000034);
  256. #endif
  257. return (0);
  258. }
  259. void board_get_enetaddr (uchar * enet)
  260. {
  261. ushort read = 0;
  262. ushort addr_of_eth_addr = 0;
  263. ushort len_sys = 0;
  264. ushort len_sys_cfg = 0;
  265. /* check identification word */
  266. eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
  267. if (read != EEPROM_IDENT)
  268. return;
  269. /* calculate offset of config area */
  270. eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
  271. eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
  272. (uchar *)&len_sys_cfg, 2);
  273. addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
  274. if (addr_of_eth_addr >= EEPROM_LEN)
  275. return;
  276. eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
  277. }
  278. int misc_init_r(void)
  279. {
  280. uchar enetaddr[6];
  281. if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
  282. board_get_enetaddr(enetaddr);
  283. eth_setenv_enetaddr("ethaddr", enetaddr);
  284. }
  285. return 0;
  286. }
  287. #ifdef CONFIG_PCI
  288. static struct pci_controller hose;
  289. extern void pci_mpc5xxx_init(struct pci_controller *);
  290. void pci_init_board(void)
  291. {
  292. pci_mpc5xxx_init(&hose);
  293. }
  294. #endif
  295. #ifdef CONFIG_CMD_IDE
  296. #ifdef CONFIG_IDE_RESET
  297. void init_ide_reset(void)
  298. {
  299. debug ("init_ide_reset\n");
  300. /* set gpio output value to 1 */
  301. setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
  302. /* open drain output */
  303. setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
  304. /* direction output */
  305. setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
  306. /* enable gpio */
  307. setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
  308. }
  309. void ide_set_reset(int idereset)
  310. {
  311. debug ("ide_reset(%d)\n", idereset);
  312. /* set gpio output value to 0 */
  313. clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
  314. /* open drain output */
  315. setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
  316. /* direction output */
  317. setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
  318. /* enable gpio */
  319. setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
  320. udelay(10000);
  321. /* set gpio output value to 1 */
  322. setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
  323. /* open drain output */
  324. setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
  325. /* direction output */
  326. setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
  327. /* enable gpio */
  328. setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
  329. }
  330. #endif /* CONFIG_IDE_RESET */
  331. #endif /* CONFIG_CMD_IDE */
  332. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  333. static void ft_delete_node(void *fdt, const char *compat)
  334. {
  335. int off = -1;
  336. int ret;
  337. off = fdt_node_offset_by_compatible(fdt, -1, compat);
  338. if (off < 0) {
  339. printf("Could not find %s node.\n", compat);
  340. return;
  341. }
  342. ret = fdt_del_node(fdt, off);
  343. if (ret < 0)
  344. printf("Could not delete %s node.\n", compat);
  345. }
  346. #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
  347. static void ft_adapt_flash_base(void *blob)
  348. {
  349. flash_info_t *dev = &flash_info[0];
  350. int off;
  351. struct fdt_property *prop;
  352. int len;
  353. u32 *reg, *reg2;
  354. off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
  355. if (off < 0) {
  356. printf("Could not find fsl,mpc5200b-lpb node.\n");
  357. return;
  358. }
  359. /* found compatible property */
  360. prop = fdt_get_property_w(blob, off, "ranges", &len);
  361. if (prop) {
  362. reg = reg2 = (u32 *)&prop->data[0];
  363. reg[2] = dev->start[0];
  364. reg[3] = dev->size;
  365. fdt_setprop(blob, off, "ranges", reg2, len);
  366. } else
  367. printf("Could not find ranges\n");
  368. }
  369. extern ulong flash_get_size (phys_addr_t base, int banknum);
  370. /* Update the Flash Baseaddr settings */
  371. int update_flash_size (int flash_size)
  372. {
  373. volatile struct mpc5xxx_mmap_ctl *mm =
  374. (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
  375. flash_info_t *dev;
  376. int i;
  377. int size = 0;
  378. unsigned long base = 0x0;
  379. u32 *cs_reg = (u32 *)&mm->cs0_start;
  380. for (i = 0; i < 2; i++) {
  381. dev = &flash_info[i];
  382. if (dev->size) {
  383. /* calculate new base addr for this chipselect */
  384. base -= dev->size;
  385. out_be32(cs_reg, START_REG(base));
  386. cs_reg++;
  387. out_be32(cs_reg, STOP_REG(base, dev->size));
  388. cs_reg++;
  389. /* recalculate the sectoraddr in the cfi driver */
  390. size += flash_get_size(base, i);
  391. }
  392. }
  393. flash_protect_default();
  394. gd->bd->bi_flashstart = base;
  395. return 0;
  396. }
  397. #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
  398. void ft_board_setup(void *blob, bd_t *bd)
  399. {
  400. int phy_addr = CONFIG_PHY_ADDR;
  401. char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
  402. ft_cpu_setup(blob, bd);
  403. /*
  404. * There are 2 RTC nodes in the DTS, so remove
  405. * the unneeded node here.
  406. */
  407. #if defined(CONFIG_DIGSY_REV5)
  408. ft_delete_node(blob, "dallas,ds1339");
  409. #else
  410. ft_delete_node(blob, "mc,rv3029c2");
  411. #endif
  412. #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
  413. #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
  414. /* Update reg property in all nor flash nodes too */
  415. fdt_fixup_nor_flash_size(blob);
  416. #endif
  417. ft_adapt_flash_base(blob);
  418. #endif
  419. /* fix up the phy address */
  420. do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
  421. }
  422. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */