stm32_rtc.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY UCLASS_RTC
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <malloc.h>
  10. #include <rtc.h>
  11. #include <asm/io.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/bitops.h>
  14. #include <linux/iopoll.h>
  15. #define STM32_RTC_TR 0x00
  16. #define STM32_RTC_DR 0x04
  17. #define STM32_RTC_ISR 0x0C
  18. #define STM32_RTC_PRER 0x10
  19. #define STM32_RTC_CR 0x18
  20. #define STM32_RTC_WPR 0x24
  21. /* STM32_RTC_TR bit fields */
  22. #define STM32_RTC_SEC_SHIFT 0
  23. #define STM32_RTC_SEC GENMASK(6, 0)
  24. #define STM32_RTC_MIN_SHIFT 8
  25. #define STM32_RTC_MIN GENMASK(14, 8)
  26. #define STM32_RTC_HOUR_SHIFT 16
  27. #define STM32_RTC_HOUR GENMASK(21, 16)
  28. /* STM32_RTC_DR bit fields */
  29. #define STM32_RTC_DATE_SHIFT 0
  30. #define STM32_RTC_DATE GENMASK(5, 0)
  31. #define STM32_RTC_MONTH_SHIFT 8
  32. #define STM32_RTC_MONTH GENMASK(12, 8)
  33. #define STM32_RTC_WDAY_SHIFT 13
  34. #define STM32_RTC_WDAY GENMASK(15, 13)
  35. #define STM32_RTC_YEAR_SHIFT 16
  36. #define STM32_RTC_YEAR GENMASK(23, 16)
  37. /* STM32_RTC_CR bit fields */
  38. #define STM32_RTC_CR_FMT BIT(6)
  39. /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
  40. #define STM32_RTC_ISR_INITS BIT(4)
  41. #define STM32_RTC_ISR_RSF BIT(5)
  42. #define STM32_RTC_ISR_INITF BIT(6)
  43. #define STM32_RTC_ISR_INIT BIT(7)
  44. /* STM32_RTC_PRER bit fields */
  45. #define STM32_RTC_PRER_PRED_S_SHIFT 0
  46. #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
  47. #define STM32_RTC_PRER_PRED_A_SHIFT 16
  48. #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
  49. /* STM32_RTC_WPR key constants */
  50. #define RTC_WPR_1ST_KEY 0xCA
  51. #define RTC_WPR_2ND_KEY 0x53
  52. #define RTC_WPR_WRONG_KEY 0xFF
  53. struct stm32_rtc_priv {
  54. fdt_addr_t base;
  55. };
  56. static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
  57. {
  58. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  59. u32 tr, dr;
  60. tr = readl(priv->base + STM32_RTC_TR);
  61. dr = readl(priv->base + STM32_RTC_DR);
  62. tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
  63. tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
  64. tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
  65. tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
  66. tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
  67. tm->tm_year = 2000 +
  68. bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
  69. tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
  70. tm->tm_yday = 0;
  71. tm->tm_isdst = 0;
  72. dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  73. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  74. tm->tm_hour, tm->tm_min, tm->tm_sec);
  75. return 0;
  76. }
  77. static void stm32_rtc_unlock(struct udevice *dev)
  78. {
  79. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  80. writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
  81. writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
  82. }
  83. static void stm32_rtc_lock(struct udevice *dev)
  84. {
  85. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  86. writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
  87. }
  88. static int stm32_rtc_enter_init_mode(struct udevice *dev)
  89. {
  90. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  91. u32 isr = readl(priv->base + STM32_RTC_ISR);
  92. if (!(isr & STM32_RTC_ISR_INITF)) {
  93. isr |= STM32_RTC_ISR_INIT;
  94. writel(isr, priv->base + STM32_RTC_ISR);
  95. return readl_poll_timeout(priv->base + STM32_RTC_ISR,
  96. isr,
  97. (isr & STM32_RTC_ISR_INITF),
  98. 100000);
  99. }
  100. return 0;
  101. }
  102. static int stm32_rtc_wait_sync(struct udevice *dev)
  103. {
  104. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  105. u32 isr = readl(priv->base + STM32_RTC_ISR);
  106. isr &= ~STM32_RTC_ISR_RSF;
  107. writel(isr, priv->base + STM32_RTC_ISR);
  108. /*
  109. * Wait for RSF to be set to ensure the calendar registers are
  110. * synchronised, it takes around 2 rtc_ck clock cycles
  111. */
  112. return readl_poll_timeout(priv->base + STM32_RTC_ISR,
  113. isr, (isr & STM32_RTC_ISR_RSF),
  114. 100000);
  115. }
  116. static void stm32_rtc_exit_init_mode(struct udevice *dev)
  117. {
  118. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  119. u32 isr = readl(priv->base + STM32_RTC_ISR);
  120. isr &= ~STM32_RTC_ISR_INIT;
  121. writel(isr, priv->base + STM32_RTC_ISR);
  122. }
  123. static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
  124. {
  125. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  126. int ret;
  127. stm32_rtc_unlock(dev);
  128. ret = stm32_rtc_enter_init_mode(dev);
  129. if (ret)
  130. goto lock;
  131. writel(time, priv->base + STM32_RTC_TR);
  132. writel(date, priv->base + STM32_RTC_DR);
  133. stm32_rtc_exit_init_mode(dev);
  134. ret = stm32_rtc_wait_sync(dev);
  135. lock:
  136. stm32_rtc_lock(dev);
  137. return ret;
  138. }
  139. static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
  140. {
  141. u32 t, d;
  142. dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  143. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  144. tm->tm_hour, tm->tm_min, tm->tm_sec);
  145. if (tm->tm_year < 2000 || tm->tm_year > 2099)
  146. return -EINVAL;
  147. /* Time in BCD format */
  148. t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
  149. t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
  150. t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
  151. /* Date in BCD format */
  152. d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
  153. d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
  154. d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
  155. STM32_RTC_YEAR;
  156. d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
  157. return stm32_rtc_set_time(dev, t, d);
  158. }
  159. static int stm32_rtc_reset(struct udevice *dev)
  160. {
  161. dev_dbg(dev, "Reset DATE\n");
  162. return stm32_rtc_set_time(dev, 0, 0);
  163. }
  164. static int stm32_rtc_init(struct udevice *dev)
  165. {
  166. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  167. unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
  168. unsigned int rate;
  169. struct clk clk;
  170. int ret;
  171. u32 isr = readl(priv->base + STM32_RTC_ISR);
  172. if (isr & STM32_RTC_ISR_INITS)
  173. return 0;
  174. ret = clk_get_by_index(dev, 1, &clk);
  175. if (ret)
  176. return ret;
  177. ret = clk_enable(&clk);
  178. if (ret) {
  179. clk_free(&clk);
  180. return ret;
  181. }
  182. rate = clk_get_rate(&clk);
  183. /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
  184. pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
  185. pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
  186. for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
  187. pred_s = (rate / (pred_a + 1)) - 1;
  188. if (((pred_s + 1) * (pred_a + 1)) == rate)
  189. break;
  190. }
  191. /*
  192. * Can't find a 1Hz, so give priority to RTC power consumption
  193. * by choosing the higher possible value for prediv_a
  194. */
  195. if (pred_s > pred_s_max || pred_a > pred_a_max) {
  196. pred_a = pred_a_max;
  197. pred_s = (rate / (pred_a + 1)) - 1;
  198. }
  199. stm32_rtc_unlock(dev);
  200. ret = stm32_rtc_enter_init_mode(dev);
  201. if (ret) {
  202. dev_err(dev,
  203. "Can't enter in init mode. Prescaler config failed.\n");
  204. goto unlock;
  205. }
  206. prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
  207. prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
  208. writel(prer, priv->base + STM32_RTC_PRER);
  209. /* Force 24h time format */
  210. cr = readl(priv->base + STM32_RTC_CR);
  211. cr &= ~STM32_RTC_CR_FMT;
  212. writel(cr, priv->base + STM32_RTC_CR);
  213. stm32_rtc_exit_init_mode(dev);
  214. ret = stm32_rtc_wait_sync(dev);
  215. unlock:
  216. stm32_rtc_lock(dev);
  217. if (ret) {
  218. clk_disable(&clk);
  219. clk_free(&clk);
  220. }
  221. return ret;
  222. }
  223. static int stm32_rtc_probe(struct udevice *dev)
  224. {
  225. struct stm32_rtc_priv *priv = dev_get_priv(dev);
  226. struct clk clk;
  227. int ret;
  228. priv->base = dev_read_addr(dev);
  229. if (priv->base == FDT_ADDR_T_NONE)
  230. return -EINVAL;
  231. ret = clk_get_by_index(dev, 0, &clk);
  232. if (ret)
  233. return ret;
  234. ret = clk_enable(&clk);
  235. if (ret) {
  236. clk_free(&clk);
  237. return ret;
  238. }
  239. ret = stm32_rtc_init(dev);
  240. if (ret) {
  241. clk_disable(&clk);
  242. clk_free(&clk);
  243. }
  244. return ret;
  245. }
  246. static const struct rtc_ops stm32_rtc_ops = {
  247. .get = stm32_rtc_get,
  248. .set = stm32_rtc_set,
  249. .reset = stm32_rtc_reset,
  250. };
  251. static const struct udevice_id stm32_rtc_ids[] = {
  252. { .compatible = "st,stm32mp1-rtc" },
  253. { }
  254. };
  255. U_BOOT_DRIVER(rtc_stm32) = {
  256. .name = "rtc-stm32",
  257. .id = UCLASS_RTC,
  258. .probe = stm32_rtc_probe,
  259. .of_match = stm32_rtc_ids,
  260. .ops = &stm32_rtc_ops,
  261. .priv_auto = sizeof(struct stm32_rtc_priv),
  262. };