tpm-v2.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. struct udevice;
  17. #define TPM2_DIGEST_LEN 32
  18. #define TPM2_SHA1_DIGEST_SIZE 20
  19. #define TPM2_SHA256_DIGEST_SIZE 32
  20. #define TPM2_SHA384_DIGEST_SIZE 48
  21. #define TPM2_SHA512_DIGEST_SIZE 64
  22. #define TPM2_SM3_256_DIGEST_SIZE 32
  23. #define TPM2_MAX_PCRS 32
  24. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  25. #define TPM2_MAX_CAP_BUFFER 1024
  26. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  27. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  28. /*
  29. * We deviate from this draft of the specification by increasing the value of
  30. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  31. * implementations that have enabled a larger than typical number of PCR
  32. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  33. * in a future revision of the specification.
  34. */
  35. #define TPM2_NUM_PCR_BANKS 16
  36. /* Definition of (UINT32) TPM2_CAP Constants */
  37. #define TPM2_CAP_PCRS 0x00000005U
  38. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  39. /* Definition of (UINT32) TPM2_PT Constants */
  40. #define TPM2_PT_GROUP (u32)(0x00000100)
  41. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  42. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  43. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  44. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  45. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  46. /*
  47. * event types, cf.
  48. * "TCG Server Management Domain Firmware Profile Specification",
  49. * rev 1.00, 2020-05-01
  50. */
  51. #define EV_POST_CODE ((u32)0x00000001)
  52. #define EV_NO_ACTION ((u32)0x00000003)
  53. #define EV_SEPARATOR ((u32)0x00000004)
  54. #define EV_ACTION ((u32)0x00000005)
  55. #define EV_TAG ((u32)0x00000006)
  56. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  57. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  58. #define EV_CPU_MICROCODE ((u32)0x00000009)
  59. #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
  60. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  61. #define EV_COMPACT_HASH ((u32)0x0000000C)
  62. /*
  63. * event types, cf.
  64. * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
  65. * rev 1.04, June 3, 2019
  66. */
  67. #define EV_EFI_EVENT_BASE ((u32)0x80000000)
  68. #define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
  69. #define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
  70. #define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
  71. #define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
  72. #define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
  73. #define EV_EFI_GPT_EVENT ((u32)0x80000006)
  74. #define EV_EFI_ACTION ((u32)0x80000007)
  75. #define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
  76. #define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
  77. #define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
  78. #define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
  79. /* TPMS_TAGGED_PROPERTY Structure */
  80. struct tpms_tagged_property {
  81. u32 property;
  82. u32 value;
  83. } __packed;
  84. /* TPMS_PCR_SELECTION Structure */
  85. struct tpms_pcr_selection {
  86. u16 hash;
  87. u8 size_of_select;
  88. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  89. } __packed;
  90. /* TPML_PCR_SELECTION Structure */
  91. struct tpml_pcr_selection {
  92. u32 count;
  93. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  94. } __packed;
  95. /* TPML_TAGGED_TPM_PROPERTY Structure */
  96. struct tpml_tagged_tpm_property {
  97. u32 count;
  98. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  99. } __packed;
  100. /* TPMU_CAPABILITIES Union */
  101. union tpmu_capabilities {
  102. /*
  103. * Non exhaustive. Only added the structs needed for our
  104. * current code
  105. */
  106. struct tpml_pcr_selection assigned_pcr;
  107. struct tpml_tagged_tpm_property tpm_properties;
  108. } __packed;
  109. /* TPMS_CAPABILITY_DATA Structure */
  110. struct tpms_capability_data {
  111. u32 capability;
  112. union tpmu_capabilities data;
  113. } __packed;
  114. /**
  115. * SHA1 Event Log Entry Format
  116. *
  117. * @pcr_index: PCRIndex event extended to
  118. * @event_type: Type of event (see EFI specs)
  119. * @digest: Value extended into PCR index
  120. * @event_size: Size of event
  121. * @event: Event data
  122. */
  123. struct tcg_pcr_event {
  124. u32 pcr_index;
  125. u32 event_type;
  126. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  127. u32 event_size;
  128. u8 event[];
  129. } __packed;
  130. /**
  131. * Definition of TPMU_HA Union
  132. */
  133. union tmpu_ha {
  134. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  135. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  136. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  137. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  138. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  139. } __packed;
  140. /**
  141. * Definition of TPMT_HA Structure
  142. *
  143. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  144. * @digest: Digest value for a given algorithm
  145. */
  146. struct tpmt_ha {
  147. u16 hash_alg;
  148. union tmpu_ha digest;
  149. } __packed;
  150. /**
  151. * Definition of TPML_DIGEST_VALUES Structure
  152. *
  153. * @count: Number of algorithms supported by hardware
  154. * @digests: struct for algorithm id and hash value
  155. */
  156. struct tpml_digest_values {
  157. u32 count;
  158. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  159. } __packed;
  160. /**
  161. * Crypto Agile Log Entry Format
  162. *
  163. * @pcr_index: PCRIndex event extended to
  164. * @event_type: Type of event
  165. * @digests: List of digestsextended to PCR index
  166. * @event_size: Size of the event data
  167. * @event: Event data
  168. */
  169. struct tcg_pcr_event2 {
  170. u32 pcr_index;
  171. u32 event_type;
  172. struct tpml_digest_values digests;
  173. u32 event_size;
  174. u8 event[];
  175. } __packed;
  176. /**
  177. * TPM2 Structure Tags for command/response buffers.
  178. *
  179. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  180. * @TPM2_ST_SESSIONS: the command needs an authentication.
  181. */
  182. enum tpm2_structures {
  183. TPM2_ST_NO_SESSIONS = 0x8001,
  184. TPM2_ST_SESSIONS = 0x8002,
  185. };
  186. /**
  187. * TPM2 type of boolean.
  188. */
  189. enum tpm2_yes_no {
  190. TPMI_YES = 1,
  191. TPMI_NO = 0,
  192. };
  193. /**
  194. * TPM2 startup values.
  195. *
  196. * @TPM2_SU_CLEAR: reset the internal state.
  197. * @TPM2_SU_STATE: restore saved state (if any).
  198. */
  199. enum tpm2_startup_types {
  200. TPM2_SU_CLEAR = 0x0000,
  201. TPM2_SU_STATE = 0x0001,
  202. };
  203. /**
  204. * TPM2 permanent handles.
  205. *
  206. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  207. * @TPM2_RS_PW: indicates a password.
  208. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  209. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  210. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  211. */
  212. enum tpm2_handles {
  213. TPM2_RH_OWNER = 0x40000001,
  214. TPM2_RS_PW = 0x40000009,
  215. TPM2_RH_LOCKOUT = 0x4000000A,
  216. TPM2_RH_ENDORSEMENT = 0x4000000B,
  217. TPM2_RH_PLATFORM = 0x4000000C,
  218. };
  219. /**
  220. * TPM2 command codes used at the beginning of a buffer, gives the command.
  221. *
  222. * @TPM2_CC_STARTUP: TPM2_Startup().
  223. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  224. * @TPM2_CC_CLEAR: TPM2_Clear().
  225. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  226. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  227. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  228. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  229. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  230. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  231. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  232. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  233. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  234. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  235. */
  236. enum tpm2_command_codes {
  237. TPM2_CC_STARTUP = 0x0144,
  238. TPM2_CC_SELF_TEST = 0x0143,
  239. TPM2_CC_HIER_CONTROL = 0x0121,
  240. TPM2_CC_CLEAR = 0x0126,
  241. TPM2_CC_CLEARCONTROL = 0x0127,
  242. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  243. TPM2_CC_NV_DEFINE_SPACE = 0x012a,
  244. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  245. TPM2_CC_NV_WRITE = 0x0137,
  246. TPM2_CC_NV_WRITELOCK = 0x0138,
  247. TPM2_CC_DAM_RESET = 0x0139,
  248. TPM2_CC_DAM_PARAMETERS = 0x013A,
  249. TPM2_CC_NV_READ = 0x014E,
  250. TPM2_CC_GET_CAPABILITY = 0x017A,
  251. TPM2_CC_GET_RANDOM = 0x017B,
  252. TPM2_CC_PCR_READ = 0x017E,
  253. TPM2_CC_PCR_EXTEND = 0x0182,
  254. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  255. };
  256. /**
  257. * TPM2 return codes.
  258. */
  259. enum tpm2_return_codes {
  260. TPM2_RC_SUCCESS = 0x0000,
  261. TPM2_RC_BAD_TAG = 0x001E,
  262. TPM2_RC_FMT1 = 0x0080,
  263. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  264. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  265. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  266. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  267. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  268. TPM2_RC_VER1 = 0x0100,
  269. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  270. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  271. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  272. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  273. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  274. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  275. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  276. TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
  277. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  278. TPM2_RC_WARN = 0x0900,
  279. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  280. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  281. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  282. };
  283. /**
  284. * TPM2 algorithms.
  285. */
  286. enum tpm2_algorithms {
  287. TPM2_ALG_SHA1 = 0x04,
  288. TPM2_ALG_XOR = 0x0A,
  289. TPM2_ALG_SHA256 = 0x0B,
  290. TPM2_ALG_SHA384 = 0x0C,
  291. TPM2_ALG_SHA512 = 0x0D,
  292. TPM2_ALG_NULL = 0x10,
  293. TPM2_ALG_SM3_256 = 0x12,
  294. };
  295. /* NV index attributes */
  296. enum tpm_index_attrs {
  297. TPMA_NV_PPWRITE = 1UL << 0,
  298. TPMA_NV_OWNERWRITE = 1UL << 1,
  299. TPMA_NV_AUTHWRITE = 1UL << 2,
  300. TPMA_NV_POLICYWRITE = 1UL << 3,
  301. TPMA_NV_COUNTER = 1UL << 4,
  302. TPMA_NV_BITS = 1UL << 5,
  303. TPMA_NV_EXTEND = 1UL << 6,
  304. TPMA_NV_POLICY_DELETE = 1UL << 10,
  305. TPMA_NV_WRITELOCKED = 1UL << 11,
  306. TPMA_NV_WRITEALL = 1UL << 12,
  307. TPMA_NV_WRITEDEFINE = 1UL << 13,
  308. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  309. TPMA_NV_GLOBALLOCK = 1UL << 15,
  310. TPMA_NV_PPREAD = 1UL << 16,
  311. TPMA_NV_OWNERREAD = 1UL << 17,
  312. TPMA_NV_AUTHREAD = 1UL << 18,
  313. TPMA_NV_POLICYREAD = 1UL << 19,
  314. TPMA_NV_NO_DA = 1UL << 25,
  315. TPMA_NV_ORDERLY = 1UL << 26,
  316. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  317. TPMA_NV_READLOCKED = 1UL << 28,
  318. TPMA_NV_WRITTEN = 1UL << 29,
  319. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  320. TPMA_NV_READ_STCLEAR = 1UL << 31,
  321. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  322. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  323. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  324. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  325. };
  326. enum {
  327. TPM_ACCESS_VALID = 1 << 7,
  328. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  329. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  330. TPM_ACCESS_REQUEST_USE = 1 << 1,
  331. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  332. };
  333. enum {
  334. TPM_STS_FAMILY_SHIFT = 26,
  335. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  336. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  337. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  338. TPM_STS_COMMAND_CANCEL = 1 << 24,
  339. TPM_STS_BURST_COUNT_SHIFT = 8,
  340. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  341. TPM_STS_VALID = 1 << 7,
  342. TPM_STS_COMMAND_READY = 1 << 6,
  343. TPM_STS_GO = 1 << 5,
  344. TPM_STS_DATA_AVAIL = 1 << 4,
  345. TPM_STS_DATA_EXPECT = 1 << 3,
  346. TPM_STS_SELF_TEST_DONE = 1 << 2,
  347. TPM_STS_RESPONSE_RETRY = 1 << 1,
  348. };
  349. enum {
  350. TPM_CMD_COUNT_OFFSET = 2,
  351. TPM_CMD_ORDINAL_OFFSET = 6,
  352. TPM_MAX_BUF_SIZE = 1260,
  353. };
  354. enum {
  355. /* Secure storage for firmware settings */
  356. TPM_HT_PCR = 0,
  357. TPM_HT_NV_INDEX,
  358. TPM_HT_HMAC_SESSION,
  359. TPM_HT_POLICY_SESSION,
  360. HR_SHIFT = 24,
  361. HR_PCR = TPM_HT_PCR << HR_SHIFT,
  362. HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
  363. HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
  364. HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
  365. };
  366. /**
  367. * Issue a TPM2_Startup command.
  368. *
  369. * @dev TPM device
  370. * @mode TPM startup mode
  371. *
  372. * @return code of the operation
  373. */
  374. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  375. /**
  376. * Issue a TPM2_SelfTest command.
  377. *
  378. * @dev TPM device
  379. * @full_test Asking to perform all tests or only the untested ones
  380. *
  381. * @return code of the operation
  382. */
  383. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  384. /**
  385. * Issue a TPM2_Clear command.
  386. *
  387. * @dev TPM device
  388. * @handle Handle
  389. * @pw Password
  390. * @pw_sz Length of the password
  391. *
  392. * @return code of the operation
  393. */
  394. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  395. const ssize_t pw_sz);
  396. /**
  397. * Issue a TPM_NV_DefineSpace command
  398. *
  399. * This allows a space to be defined with given attributes and policy
  400. *
  401. * @dev TPM device
  402. * @space_index index of the area
  403. * @space_size size of area in bytes
  404. * @nv_attributes TPM_NV_ATTRIBUTES of the area
  405. * @nv_policy policy to use
  406. * @nv_policy_size size of the policy
  407. * @return return code of the operation
  408. */
  409. u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
  410. size_t space_size, u32 nv_attributes,
  411. const u8 *nv_policy, size_t nv_policy_size);
  412. /**
  413. * Issue a TPM2_PCR_Extend command.
  414. *
  415. * @dev TPM device
  416. * @index Index of the PCR
  417. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  418. * @digest Value representing the event to be recorded
  419. * @digest_len len of the hash
  420. *
  421. * @return code of the operation
  422. */
  423. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  424. const u8 *digest, u32 digest_len);
  425. /**
  426. * Read data from the secure storage
  427. *
  428. * @dev TPM device
  429. * @index Index of data to read
  430. * @data Place to put data
  431. * @count Number of bytes of data
  432. * @return code of the operation
  433. */
  434. u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
  435. /**
  436. * Write data to the secure storage
  437. *
  438. * @dev TPM device
  439. * @index Index of data to write
  440. * @data Data to write
  441. * @count Number of bytes of data
  442. * @return code of the operation
  443. */
  444. u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
  445. u32 count);
  446. /**
  447. * Issue a TPM2_PCR_Read command.
  448. *
  449. * @dev TPM device
  450. * @idx Index of the PCR
  451. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  452. * @data Output buffer for contents of the named PCR
  453. * @updates Optional out parameter: number of updates for this PCR
  454. *
  455. * @return code of the operation
  456. */
  457. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  458. void *data, unsigned int *updates);
  459. /**
  460. * Issue a TPM2_GetCapability command. This implementation is limited
  461. * to query property index that is 4-byte wide.
  462. *
  463. * @dev TPM device
  464. * @capability Partition of capabilities
  465. * @property Further definition of capability, limited to be 4 bytes wide
  466. * @buf Output buffer for capability information
  467. * @prop_count Size of output buffer
  468. *
  469. * @return code of the operation
  470. */
  471. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  472. void *buf, size_t prop_count);
  473. /**
  474. * Issue a TPM2_DictionaryAttackLockReset command.
  475. *
  476. * @dev TPM device
  477. * @pw Password
  478. * @pw_sz Length of the password
  479. *
  480. * @return code of the operation
  481. */
  482. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  483. /**
  484. * Issue a TPM2_DictionaryAttackParameters command.
  485. *
  486. * @dev TPM device
  487. * @pw Password
  488. * @pw_sz Length of the password
  489. * @max_tries Count of authorizations before lockout
  490. * @recovery_time Time before decrementation of the failure count
  491. * @lockout_recovery Time to wait after a lockout
  492. *
  493. * @return code of the operation
  494. */
  495. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  496. const ssize_t pw_sz, unsigned int max_tries,
  497. unsigned int recovery_time,
  498. unsigned int lockout_recovery);
  499. /**
  500. * Issue a TPM2_HierarchyChangeAuth command.
  501. *
  502. * @dev TPM device
  503. * @handle Handle
  504. * @newpw New password
  505. * @newpw_sz Length of the new password
  506. * @oldpw Old password
  507. * @oldpw_sz Length of the old password
  508. *
  509. * @return code of the operation
  510. */
  511. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  512. const ssize_t newpw_sz, const char *oldpw,
  513. const ssize_t oldpw_sz);
  514. /**
  515. * Issue a TPM_PCR_SetAuthPolicy command.
  516. *
  517. * @dev TPM device
  518. * @pw Platform password
  519. * @pw_sz Length of the password
  520. * @index Index of the PCR
  521. * @digest New key to access the PCR
  522. *
  523. * @return code of the operation
  524. */
  525. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  526. const ssize_t pw_sz, u32 index, const char *key);
  527. /**
  528. * Issue a TPM_PCR_SetAuthValue command.
  529. *
  530. * @dev TPM device
  531. * @pw Platform password
  532. * @pw_sz Length of the password
  533. * @index Index of the PCR
  534. * @digest New key to access the PCR
  535. * @key_sz Length of the new key
  536. *
  537. * @return code of the operation
  538. */
  539. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  540. const ssize_t pw_sz, u32 index, const char *key,
  541. const ssize_t key_sz);
  542. /**
  543. * Issue a TPM2_GetRandom command.
  544. *
  545. * @dev TPM device
  546. * @param data output buffer for the random bytes
  547. * @param count size of output buffer
  548. *
  549. * @return return code of the operation
  550. */
  551. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  552. /**
  553. * Lock data in the TPM
  554. *
  555. * Once locked the data cannot be written until after a reboot
  556. *
  557. * @dev TPM device
  558. * @index Index of data to lock
  559. * @return code of the operation
  560. */
  561. u32 tpm2_write_lock(struct udevice *dev, u32 index);
  562. /**
  563. * Disable access to any platform data
  564. *
  565. * This can be called to close off access to the firmware data in the data,
  566. * before calling the kernel.
  567. *
  568. * @dev TPM device
  569. * @return code of the operation
  570. */
  571. u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
  572. #endif /* __TPM_V2_H */