imx8mm_evk.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #ifndef __IMX8MM_EVK_H
  6. #define __IMX8MM_EVK_H
  7. #include <linux/sizes.h>
  8. #include <linux/stringify.h>
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
  11. #define CONFIG_SPL_MAX_SIZE (148 * 1024)
  12. #define CONFIG_SYS_MONITOR_LEN SZ_512K
  13. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  14. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  15. #define CONFIG_SYS_UBOOT_BASE \
  16. (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  17. #ifdef CONFIG_SPL_BUILD
  18. #define CONFIG_SPL_STACK 0x920000
  19. #define CONFIG_SPL_BSS_START_ADDR 0x910000
  20. #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
  21. #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  22. #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
  23. /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  24. #define CONFIG_MALLOC_F_ADDR 0x930000
  25. /* For RAW image gives a error info not panic */
  26. #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  27. #endif
  28. #ifndef CONFIG_SPL_BUILD
  29. #define BOOT_TARGET_DEVICES(func) \
  30. func(MMC, mmc, 1) \
  31. func(MMC, mmc, 2) \
  32. func(DHCP, dhcp, na)
  33. #include <config_distro_bootcmd.h>
  34. #endif
  35. /* Initial environment variables */
  36. #define CONFIG_EXTRA_ENV_SETTINGS \
  37. BOOTENV \
  38. "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
  39. "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  40. "image=Image\0" \
  41. "console=ttymxc1,115200\0" \
  42. "fdt_addr_r=0x43000000\0" \
  43. "boot_fit=no\0" \
  44. "fdtfile=imx8mm-evk.dtb\0" \
  45. "initrd_addr=0x43800000\0" \
  46. "bootm_size=0x10000000\0" \
  47. "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  48. "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  49. /* Link Definitions */
  50. #define CONFIG_LOADADDR 0x40480000
  51. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  52. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  53. #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
  54. #define CONFIG_SYS_INIT_SP_OFFSET \
  55. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  56. #define CONFIG_SYS_INIT_SP_ADDR \
  57. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  58. #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  59. /* Size of malloc() pool */
  60. #define CONFIG_SYS_MALLOC_LEN SZ_32M
  61. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  62. #define PHYS_SDRAM 0x40000000
  63. #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
  64. #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  65. /* Monitor Command Prompt */
  66. #define CONFIG_SYS_CBSIZE 2048
  67. #define CONFIG_SYS_MAXARGS 64
  68. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  69. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  70. sizeof(CONFIG_SYS_PROMPT) + 16)
  71. /* USDHC */
  72. #define CONFIG_FSL_USDHC
  73. #define CONFIG_SYS_FSL_USDHC_NUM 2
  74. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  75. #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  76. #define CONFIG_SYS_I2C_SPEED 100000
  77. #define CONFIG_ETHPRIME "FEC"
  78. #define CONFIG_FEC_XCV_TYPE RGMII
  79. #define CONFIG_FEC_MXC_PHYADDR 0
  80. #define FEC_QUIRK_ENET_MAC
  81. #define IMX_FEC_BASE 0x30BE0000
  82. #endif