T104xRDB.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <linux/stringify.h>
  9. /*
  10. * T104x RDB board configuration file
  11. */
  12. #include <asm/config_mpc85xx.h>
  13. #ifdef CONFIG_RAMBOOT_PBL
  14. #ifndef CONFIG_NXP_ESBC
  15. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  16. #else
  17. #define CONFIG_SYS_FSL_PBL_PBI \
  18. $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  19. #endif
  20. #define CONFIG_SPL_FLUSH_IMAGE
  21. #define CONFIG_SPL_PAD_TO 0x40000
  22. #define CONFIG_SPL_MAX_SIZE 0x28000
  23. #ifdef CONFIG_SPL_BUILD
  24. #define CONFIG_SPL_SKIP_RELOCATE
  25. #define CONFIG_SPL_COMMON_INIT_DDR
  26. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  27. #endif
  28. #define RESET_VECTOR_OFFSET 0x27FFC
  29. #define BOOT_PAGE_OFFSET 0x27000
  30. #ifdef CONFIG_MTD_RAW_NAND
  31. #ifdef CONFIG_NXP_ESBC
  32. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  33. /*
  34. * HDR would be appended at end of image and copied to DDR along
  35. * with U-Boot image.
  36. */
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
  38. CONFIG_U_BOOT_HDR_SIZE)
  39. #else
  40. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  41. #endif
  42. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  43. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  44. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  45. #ifdef CONFIG_TARGET_T1040RDB
  46. #define CONFIG_SYS_FSL_PBL_RCW \
  47. $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  48. #endif
  49. #ifdef CONFIG_TARGET_T1042RDB_PI
  50. #define CONFIG_SYS_FSL_PBL_RCW \
  51. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  52. #endif
  53. #ifdef CONFIG_TARGET_T1042RDB
  54. #define CONFIG_SYS_FSL_PBL_RCW \
  55. $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  56. #endif
  57. #ifdef CONFIG_TARGET_T1040D4RDB
  58. #define CONFIG_SYS_FSL_PBL_RCW \
  59. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  60. #endif
  61. #ifdef CONFIG_TARGET_T1042D4RDB
  62. #define CONFIG_SYS_FSL_PBL_RCW \
  63. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  64. #endif
  65. #endif
  66. #ifdef CONFIG_SPIFLASH
  67. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  68. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  69. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  70. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  71. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  72. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  73. #ifndef CONFIG_SPL_BUILD
  74. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  75. #endif
  76. #ifdef CONFIG_TARGET_T1040RDB
  77. #define CONFIG_SYS_FSL_PBL_RCW \
  78. $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  79. #endif
  80. #ifdef CONFIG_TARGET_T1042RDB_PI
  81. #define CONFIG_SYS_FSL_PBL_RCW \
  82. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  83. #endif
  84. #ifdef CONFIG_TARGET_T1042RDB
  85. #define CONFIG_SYS_FSL_PBL_RCW \
  86. $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  87. #endif
  88. #ifdef CONFIG_TARGET_T1040D4RDB
  89. #define CONFIG_SYS_FSL_PBL_RCW \
  90. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  91. #endif
  92. #ifdef CONFIG_TARGET_T1042D4RDB
  93. #define CONFIG_SYS_FSL_PBL_RCW \
  94. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
  95. #endif
  96. #endif
  97. #ifdef CONFIG_SDCARD
  98. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  99. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  100. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  101. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  102. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  103. #ifndef CONFIG_SPL_BUILD
  104. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  105. #endif
  106. #ifdef CONFIG_TARGET_T1040RDB
  107. #define CONFIG_SYS_FSL_PBL_RCW \
  108. $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
  109. #endif
  110. #ifdef CONFIG_TARGET_T1042RDB_PI
  111. #define CONFIG_SYS_FSL_PBL_RCW \
  112. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
  113. #endif
  114. #ifdef CONFIG_TARGET_T1042RDB
  115. #define CONFIG_SYS_FSL_PBL_RCW \
  116. $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
  117. #endif
  118. #ifdef CONFIG_TARGET_T1040D4RDB
  119. #define CONFIG_SYS_FSL_PBL_RCW \
  120. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
  121. #endif
  122. #ifdef CONFIG_TARGET_T1042D4RDB
  123. #define CONFIG_SYS_FSL_PBL_RCW \
  124. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
  125. #endif
  126. #endif
  127. #endif
  128. /* High Level Configuration Options */
  129. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  130. /* support deep sleep */
  131. #define CONFIG_DEEP_SLEEP
  132. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  133. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  134. #endif
  135. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  136. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  137. #define CONFIG_PCIE1 /* PCIE controller 1 */
  138. #define CONFIG_PCIE2 /* PCIE controller 2 */
  139. #define CONFIG_PCIE3 /* PCIE controller 3 */
  140. #define CONFIG_PCIE4 /* PCIE controller 4 */
  141. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  142. #if defined(CONFIG_SPIFLASH)
  143. #elif defined(CONFIG_MTD_RAW_NAND)
  144. #ifdef CONFIG_NXP_ESBC
  145. #define CONFIG_RAMBOOT_NAND
  146. #define CONFIG_BOOTSCRIPT_COPY_RAM
  147. #endif
  148. #endif
  149. #define CONFIG_SYS_CLK_FREQ 100000000
  150. #define CONFIG_DDR_CLK_FREQ 66666666
  151. /*
  152. * These can be toggled for performance analysis, otherwise use default.
  153. */
  154. #define CONFIG_SYS_CACHE_STASHING
  155. #define CONFIG_BACKSIDE_L2_CACHE
  156. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  157. #define CONFIG_BTB /* toggle branch predition */
  158. #define CONFIG_DDR_ECC
  159. #ifdef CONFIG_DDR_ECC
  160. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  161. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  162. #endif
  163. #define CONFIG_ENABLE_36BIT_PHYS
  164. /*
  165. * Config the L3 Cache as L3 SRAM
  166. */
  167. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  168. /*
  169. * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  170. * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  171. * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  172. */
  173. #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
  174. #define CONFIG_SYS_L3_SIZE 256 << 10
  175. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
  176. #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  177. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  178. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  179. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  180. #define CONFIG_SYS_DCSRBAR 0xf0000000
  181. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  182. /*
  183. * DDR Setup
  184. */
  185. #define CONFIG_VERY_BIG_RAM
  186. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  187. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  188. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  189. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  190. #define CONFIG_DDR_SPD
  191. #define CONFIG_SYS_SPD_BUS_NUM 0
  192. #define SPD_EEPROM_ADDRESS 0x51
  193. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  194. /*
  195. * IFC Definitions
  196. */
  197. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  198. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  199. #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
  200. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  201. CSPR_PORT_SIZE_16 | \
  202. CSPR_MSEL_NOR | \
  203. CSPR_V)
  204. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  205. /*
  206. * TDM Definition
  207. */
  208. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  209. /* NOR Flash Timing Params */
  210. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  211. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  212. FTIM0_NOR_TEADC(0x5) | \
  213. FTIM0_NOR_TEAHC(0x5))
  214. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  215. FTIM1_NOR_TRAD_NOR(0x1A) |\
  216. FTIM1_NOR_TSEQRAD_NOR(0x13))
  217. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  218. FTIM2_NOR_TCH(0x4) | \
  219. FTIM2_NOR_TWPH(0x0E) | \
  220. FTIM2_NOR_TWP(0x1c))
  221. #define CONFIG_SYS_NOR_FTIM3 0x0
  222. #define CONFIG_SYS_FLASH_QUIET_TEST
  223. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  224. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  225. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  226. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  227. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  228. #define CONFIG_SYS_FLASH_EMPTY_INFO
  229. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  230. /* CPLD on IFC */
  231. #define CPLD_LBMAP_MASK 0x3F
  232. #define CPLD_BANK_SEL_MASK 0x07
  233. #define CPLD_BANK_OVERRIDE 0x40
  234. #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  235. #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
  236. #define CPLD_LBMAP_RESET 0xFF
  237. #define CPLD_LBMAP_SHIFT 0x03
  238. #if defined(CONFIG_TARGET_T1042RDB_PI)
  239. #define CPLD_DIU_SEL_DFP 0x80
  240. #elif defined(CONFIG_TARGET_T1042D4RDB)
  241. #define CPLD_DIU_SEL_DFP 0xc0
  242. #endif
  243. #if defined(CONFIG_TARGET_T1040D4RDB)
  244. #define CPLD_INT_MASK_ALL 0xFF
  245. #define CPLD_INT_MASK_THERM 0x80
  246. #define CPLD_INT_MASK_DVI_DFP 0x40
  247. #define CPLD_INT_MASK_QSGMII1 0x20
  248. #define CPLD_INT_MASK_QSGMII2 0x10
  249. #define CPLD_INT_MASK_SGMI1 0x08
  250. #define CPLD_INT_MASK_SGMI2 0x04
  251. #define CPLD_INT_MASK_TDMR1 0x02
  252. #define CPLD_INT_MASK_TDMR2 0x01
  253. #endif
  254. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  255. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  256. #define CONFIG_SYS_CSPR2_EXT (0xf)
  257. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  258. | CSPR_PORT_SIZE_8 \
  259. | CSPR_MSEL_GPCM \
  260. | CSPR_V)
  261. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  262. #define CONFIG_SYS_CSOR2 0x0
  263. /* CPLD Timing parameters for IFC CS2 */
  264. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  265. FTIM0_GPCM_TEADC(0x0e) | \
  266. FTIM0_GPCM_TEAHC(0x0e))
  267. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  268. FTIM1_GPCM_TRAD(0x1f))
  269. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  270. FTIM2_GPCM_TCH(0x8) | \
  271. FTIM2_GPCM_TWP(0x1f))
  272. #define CONFIG_SYS_CS2_FTIM3 0x0
  273. /* NAND Flash on IFC */
  274. #define CONFIG_NAND_FSL_IFC
  275. #define CONFIG_SYS_NAND_BASE 0xff800000
  276. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  277. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  278. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  279. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  280. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  281. | CSPR_V)
  282. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  283. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  284. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  285. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  286. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  287. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  288. | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
  289. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  290. #define CONFIG_SYS_NAND_ONFI_DETECTION
  291. /* ONFI NAND Flash mode0 Timing Params */
  292. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  293. FTIM0_NAND_TWP(0x18) | \
  294. FTIM0_NAND_TWCHT(0x07) | \
  295. FTIM0_NAND_TWH(0x0a))
  296. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  297. FTIM1_NAND_TWBE(0x39) | \
  298. FTIM1_NAND_TRR(0x0e) | \
  299. FTIM1_NAND_TRP(0x18))
  300. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  301. FTIM2_NAND_TREH(0x0a) | \
  302. FTIM2_NAND_TWHRE(0x1e))
  303. #define CONFIG_SYS_NAND_FTIM3 0x0
  304. #define CONFIG_SYS_NAND_DDR_LAW 11
  305. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  306. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  307. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  308. #if defined(CONFIG_MTD_RAW_NAND)
  309. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  310. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  311. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  312. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  313. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  314. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  315. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  316. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  317. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  318. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  319. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  320. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  321. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  322. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  323. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  324. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  325. #else
  326. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  327. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  328. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  329. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  330. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  331. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  332. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  333. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  334. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  335. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  336. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  337. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  338. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  339. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  340. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  341. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  342. #endif
  343. #ifdef CONFIG_SPL_BUILD
  344. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  345. #else
  346. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  347. #endif
  348. #if defined(CONFIG_RAMBOOT_PBL)
  349. #define CONFIG_SYS_RAMBOOT
  350. #endif
  351. #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
  352. #if defined(CONFIG_MTD_RAW_NAND)
  353. #define CONFIG_A008044_WORKAROUND
  354. #endif
  355. #endif
  356. #define CONFIG_HWCONFIG
  357. /* define to use L1 as initial stack */
  358. #define CONFIG_L1_INIT_RAM
  359. #define CONFIG_SYS_INIT_RAM_LOCK
  360. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  361. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  362. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  363. /* The assembler doesn't like typecast */
  364. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  365. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  366. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  367. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  368. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  369. GENERATED_GBL_DATA_SIZE)
  370. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  371. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  372. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  373. /* Serial Port - controlled on board with jumper J8
  374. * open - index 2
  375. * shorted - index 1
  376. */
  377. #define CONFIG_SYS_NS16550_SERIAL
  378. #define CONFIG_SYS_NS16550_REG_SIZE 1
  379. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  380. #define CONFIG_SYS_BAUDRATE_TABLE \
  381. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  382. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  383. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  384. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  385. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  386. #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
  387. /* Video */
  388. #define CONFIG_FSL_DIU_FB
  389. #ifdef CONFIG_FSL_DIU_FB
  390. #define CONFIG_FSL_DIU_CH7301
  391. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  392. #define CONFIG_VIDEO_LOGO
  393. #define CONFIG_VIDEO_BMP_LOGO
  394. #endif
  395. #endif
  396. /* I2C */
  397. #if !CONFIG_IS_ENABLED(DM_I2C)
  398. #define CONFIG_SYS_I2C
  399. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  400. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  401. #define CONFIG_SYS_FSL_I2C3_SPEED 400000
  402. #define CONFIG_SYS_FSL_I2C4_SPEED 400000
  403. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  404. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  405. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  406. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  407. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  408. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  409. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  410. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  411. #else
  412. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  413. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  414. #endif
  415. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  416. /* I2C bus multiplexer */
  417. #define I2C_MUX_PCA_ADDR 0x70
  418. #define I2C_MUX_CH_DEFAULT 0x8
  419. #if defined(CONFIG_TARGET_T1042RDB_PI) || \
  420. defined(CONFIG_TARGET_T1040D4RDB) || \
  421. defined(CONFIG_TARGET_T1042D4RDB)
  422. /* LDI/DVI Encoder for display */
  423. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  424. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  425. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  426. /*
  427. * RTC configuration
  428. */
  429. #define RTC
  430. #define CONFIG_RTC_DS1337 1
  431. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  432. /*DVI encoder*/
  433. #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
  434. #endif
  435. /*
  436. * eSPI - Enhanced SPI
  437. */
  438. /*
  439. * General PCI
  440. * Memory space is mapped 1-1, but I/O space must start from 0.
  441. */
  442. #ifdef CONFIG_PCI
  443. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  444. #ifdef CONFIG_PCIE1
  445. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  446. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  447. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  448. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  449. #endif
  450. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  451. #ifdef CONFIG_PCIE2
  452. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  453. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  454. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  455. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  456. #endif
  457. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  458. #ifdef CONFIG_PCIE3
  459. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  460. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  461. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  462. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  463. #endif
  464. /* controller 4, Base address 203000 */
  465. #ifdef CONFIG_PCIE4
  466. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  467. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  468. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  469. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  470. #endif
  471. #if !defined(CONFIG_DM_PCI)
  472. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  473. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  474. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  475. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  476. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  477. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  478. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  479. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  480. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  481. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  482. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  483. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  484. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  485. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  486. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  487. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  488. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  489. #define CONFIG_PCI_INDIRECT_BRIDGE
  490. #endif
  491. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  492. #endif /* CONFIG_PCI */
  493. /* SATA */
  494. #define CONFIG_FSL_SATA_V2
  495. #ifdef CONFIG_FSL_SATA_V2
  496. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  497. #define CONFIG_SATA1
  498. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  499. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  500. #define CONFIG_LBA48
  501. #endif
  502. /*
  503. * USB
  504. */
  505. #define CONFIG_HAS_FSL_DR_USB
  506. #ifdef CONFIG_HAS_FSL_DR_USB
  507. #ifdef CONFIG_USB_EHCI_HCD
  508. #define CONFIG_USB_EHCI_FSL
  509. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  510. #endif
  511. #endif
  512. #ifdef CONFIG_MMC
  513. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  514. #endif
  515. /* Qman/Bman */
  516. #ifndef CONFIG_NOBQFMAN
  517. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  518. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  519. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  520. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  521. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  522. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  523. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  524. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  525. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  526. CONFIG_SYS_BMAN_CENA_SIZE)
  527. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  528. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  529. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  530. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  531. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  532. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  533. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  534. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  535. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  536. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  537. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  538. CONFIG_SYS_QMAN_CENA_SIZE)
  539. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  540. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  541. #define CONFIG_SYS_DPAA_FMAN
  542. #define CONFIG_SYS_DPAA_PME
  543. #define CONFIG_U_QE
  544. /* Default address of microcode for the Linux Fman driver */
  545. #if defined(CONFIG_SPIFLASH)
  546. /*
  547. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  548. * env, so we got 0x110000.
  549. */
  550. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  551. #elif defined(CONFIG_SDCARD)
  552. /*
  553. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  554. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  555. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  556. */
  557. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  558. #elif defined(CONFIG_MTD_RAW_NAND)
  559. #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  560. #else
  561. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  562. #endif
  563. #if defined(CONFIG_SPIFLASH)
  564. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  565. #elif defined(CONFIG_SDCARD)
  566. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  567. #elif defined(CONFIG_MTD_RAW_NAND)
  568. #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  569. #else
  570. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  571. #endif
  572. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  573. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  574. #endif /* CONFIG_NOBQFMAN */
  575. #ifdef CONFIG_FMAN_ENET
  576. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
  577. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
  578. #elif defined(CONFIG_TARGET_T1040D4RDB)
  579. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
  580. #elif defined(CONFIG_TARGET_T1042D4RDB)
  581. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
  582. #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
  583. #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
  584. #endif
  585. #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  586. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
  587. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
  588. #else
  589. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
  590. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
  591. #endif
  592. /* Enable VSC9953 L2 Switch driver on T1040 SoC */
  593. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
  594. #define CONFIG_VSC9953
  595. #ifdef CONFIG_TARGET_T1040RDB
  596. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
  597. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
  598. #else
  599. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
  600. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
  601. #endif
  602. #endif
  603. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  604. #endif
  605. /*
  606. * Environment
  607. */
  608. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  609. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  610. /*
  611. * Miscellaneous configurable options
  612. */
  613. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  614. /*
  615. * For booting Linux, the board info and command line data
  616. * have to be in the first 64 MB of memory, since this is
  617. * the maximum mapped by the Linux kernel during initialization.
  618. */
  619. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  620. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  621. #ifdef CONFIG_CMD_KGDB
  622. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  623. #endif
  624. /*
  625. * Dynamic MTD Partition support with mtdparts
  626. */
  627. /*
  628. * Environment Configuration
  629. */
  630. #define CONFIG_ROOTPATH "/opt/nfsroot"
  631. #define CONFIG_BOOTFILE "uImage"
  632. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  633. /* default location for tftp and bootm */
  634. #define CONFIG_LOADADDR 1000000
  635. #define __USB_PHY_TYPE utmi
  636. #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
  637. #ifdef CONFIG_TARGET_T1040RDB
  638. #define FDTFILE "t1040rdb/t1040rdb.dtb"
  639. #elif defined(CONFIG_TARGET_T1042RDB_PI)
  640. #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
  641. #elif defined(CONFIG_TARGET_T1042RDB)
  642. #define FDTFILE "t1042rdb/t1042rdb.dtb"
  643. #elif defined(CONFIG_TARGET_T1040D4RDB)
  644. #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
  645. #elif defined(CONFIG_TARGET_T1042D4RDB)
  646. #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
  647. #endif
  648. #ifdef CONFIG_FSL_DIU_FB
  649. #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
  650. #else
  651. #define DIU_ENVIRONMENT
  652. #endif
  653. #define CONFIG_EXTRA_ENV_SETTINGS \
  654. "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
  655. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  656. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  657. "netdev=eth0\0" \
  658. "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
  659. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  660. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  661. "tftpflash=tftpboot $loadaddr $uboot && " \
  662. "protect off $ubootaddr +$filesize && " \
  663. "erase $ubootaddr +$filesize && " \
  664. "cp.b $loadaddr $ubootaddr $filesize && " \
  665. "protect on $ubootaddr +$filesize && " \
  666. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  667. "consoledev=ttyS0\0" \
  668. "ramdiskaddr=2000000\0" \
  669. "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
  670. "fdtaddr=1e00000\0" \
  671. "fdtfile=" __stringify(FDTFILE) "\0" \
  672. "bdev=sda3\0"
  673. #define CONFIG_LINUX \
  674. "setenv bootargs root=/dev/ram rw " \
  675. "console=$consoledev,$baudrate $othbootargs;" \
  676. "setenv ramdiskaddr 0x02000000;" \
  677. "setenv fdtaddr 0x00c00000;" \
  678. "setenv loadaddr 0x1000000;" \
  679. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  680. #define CONFIG_HDBOOT \
  681. "setenv bootargs root=/dev/$bdev rw " \
  682. "console=$consoledev,$baudrate $othbootargs;" \
  683. "tftp $loadaddr $bootfile;" \
  684. "tftp $fdtaddr $fdtfile;" \
  685. "bootm $loadaddr - $fdtaddr"
  686. #define CONFIG_NFSBOOTCOMMAND \
  687. "setenv bootargs root=/dev/nfs rw " \
  688. "nfsroot=$serverip:$rootpath " \
  689. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  690. "console=$consoledev,$baudrate $othbootargs;" \
  691. "tftp $loadaddr $bootfile;" \
  692. "tftp $fdtaddr $fdtfile;" \
  693. "bootm $loadaddr - $fdtaddr"
  694. #define CONFIG_RAMBOOTCOMMAND \
  695. "setenv bootargs root=/dev/ram rw " \
  696. "console=$consoledev,$baudrate $othbootargs;" \
  697. "tftp $ramdiskaddr $ramdiskfile;" \
  698. "tftp $loadaddr $bootfile;" \
  699. "tftp $fdtaddr $fdtfile;" \
  700. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  701. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  702. #include <asm/fsl_secure_boot.h>
  703. #endif /* __CONFIG_H */