mtu3_hw_regs.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
  4. *
  5. * Copyright (C) 2016 MediaTek Inc.
  6. *
  7. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  8. */
  9. #ifndef _SSUSB_HW_REGS_H_
  10. #define _SSUSB_HW_REGS_H_
  11. /* segment offset of MAC register */
  12. #define SSUSB_XCHI_BASE 0x0000
  13. #define SSUSB_DEV_BASE 0x1000
  14. #define SSUSB_EPCTL_CSR_BASE 0x1800
  15. #define SSUSB_USB3_MAC_CSR_BASE 0x2400
  16. #define SSUSB_USB3_SYS_CSR_BASE 0x2400
  17. #define SSUSB_USB2_CSR_BASE 0x3400
  18. /* IPPC register in Infra */
  19. #define SSUSB_SIFSLV_IPPC_BASE 0x0000
  20. /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
  21. #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
  22. #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
  23. #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
  24. #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
  25. #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
  26. #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
  27. #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
  28. #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
  29. #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
  30. #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
  31. #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
  32. #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
  33. #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
  34. #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
  35. #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
  36. #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
  37. #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
  38. #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
  39. #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
  40. #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
  41. #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
  42. #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
  43. #define U3D_QFCR (SSUSB_DEV_BASE + 0x0428)
  44. #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
  45. #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
  46. #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
  47. #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
  48. #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
  49. #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
  50. #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
  51. #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
  52. #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
  53. #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
  54. #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
  55. #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
  56. #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
  57. #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
  58. #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
  59. #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
  60. #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
  61. #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
  62. #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
  63. #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
  64. #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
  65. #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
  66. #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
  67. #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
  68. #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
  69. #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
  70. #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
  71. #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
  72. #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
  73. #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
  74. #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
  75. #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
  76. /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
  77. /* U3D_LV1ISR */
  78. #define EP_CTRL_INTR BIT(5)
  79. #define MAC2_INTR BIT(4)
  80. #define DMA_INTR BIT(3)
  81. #define MAC3_INTR BIT(2)
  82. #define QMU_INTR BIT(1)
  83. #define BMU_INTR BIT(0)
  84. /* U3D_LV1IECR */
  85. #define LV1IECR_MSK GENMASK(31, 0)
  86. /* U3D_EPISR */
  87. #define EPRISR(x) (BIT(16) << (x))
  88. #define SETUPENDISR BIT(16)
  89. #define EPTISR(x) (BIT(0) << (x))
  90. #define EP0ISR BIT(0)
  91. /* U3D_EP0CSR */
  92. #define EP0_SENDSTALL BIT(25)
  93. #define EP0_FIFOFULL BIT(23)
  94. #define EP0_SENTSTALL BIT(22)
  95. #define EP0_DPHTX BIT(20)
  96. #define EP0_DATAEND BIT(19)
  97. #define EP0_TXPKTRDY BIT(18)
  98. #define EP0_SETUPPKTRDY BIT(17)
  99. #define EP0_RXPKTRDY BIT(16)
  100. #define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
  101. #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK)
  102. #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
  103. /* U3D_TX1CSR0 */
  104. #define TX_DMAREQEN BIT(29)
  105. #define TX_FIFOFULL BIT(25)
  106. #define TX_FIFOEMPTY BIT(24)
  107. #define TX_SENTSTALL BIT(22)
  108. #define TX_SENDSTALL BIT(21)
  109. #define TX_TXPKTRDY BIT(16)
  110. #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
  111. #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK)
  112. #define TX_W1C_BITS (~(TX_SENTSTALL))
  113. /* U3D_TX1CSR1 */
  114. #define TX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
  115. #define TX_MULT_G2(x) (((x) & 0x7) << 21)
  116. #define TX_MULT_OG(x) (((x) & 0x3) << 22)
  117. #define TX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
  118. #define TX_SLOT(x) (((x) & 0x3f) << 8)
  119. #define TX_TYPE(x) (((x) & 0x3) << 4)
  120. #define TX_SS_BURST(x) (((x) & 0xf) << 0)
  121. #define TX_MULT(g2c, x) \
  122. ({ \
  123. typeof(x) x_ = (x); \
  124. (g2c) ? TX_MULT_G2(x_) : TX_MULT_OG(x_); \
  125. })
  126. #define TX_MAX_PKT(g2c, x) \
  127. ({ \
  128. typeof(x) x_ = (x); \
  129. (g2c) ? TX_MAX_PKT_G2(x_) : TX_MAX_PKT_OG(x_); \
  130. })
  131. /* for TX_TYPE & RX_TYPE */
  132. #define TYPE_BULK (0x0)
  133. #define TYPE_INT (0x1)
  134. #define TYPE_ISO (0x2)
  135. #define TYPE_MASK (0x3)
  136. /* U3D_TX1CSR2 */
  137. #define TX_BINTERVAL(x) (((x) & 0xff) << 24)
  138. #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
  139. #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
  140. /* U3D_RX1CSR0 */
  141. #define RX_DMAREQEN BIT(29)
  142. #define RX_SENTSTALL BIT(22)
  143. #define RX_SENDSTALL BIT(21)
  144. #define RX_RXPKTRDY BIT(16)
  145. #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
  146. #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK)
  147. #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY))
  148. /* U3D_RX1CSR1 */
  149. #define RX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
  150. #define RX_MULT_G2(x) (((x) & 0x7) << 21)
  151. #define RX_MULT_OG(x) (((x) & 0x3) << 22)
  152. #define RX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
  153. #define RX_SLOT(x) (((x) & 0x3f) << 8)
  154. #define RX_TYPE(x) (((x) & 0x3) << 4)
  155. #define RX_SS_BURST(x) (((x) & 0xf) << 0)
  156. #define RX_MULT(g2c, x) \
  157. ({ \
  158. typeof(x) x_ = (x); \
  159. (g2c) ? RX_MULT_G2(x_) : RX_MULT_OG(x_); \
  160. })
  161. #define RX_MAX_PKT(g2c, x) \
  162. ({ \
  163. typeof(x) x_ = (x); \
  164. (g2c) ? RX_MAX_PKT_G2(x_) : RX_MAX_PKT_OG(x_); \
  165. })
  166. /* U3D_RX1CSR2 */
  167. #define RX_BINTERVAL(x) (((x) & 0xff) << 24)
  168. #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
  169. #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
  170. /* U3D_QCR0 */
  171. #define QMU_RX_CS_EN(x) (BIT(16) << (x))
  172. #define QMU_TX_CS_EN(x) (BIT(0) << (x))
  173. #define QMU_CS16B_EN BIT(0)
  174. /* U3D_QCR1 */
  175. #define QMU_TX_ZLP(x) (BIT(0) << (x))
  176. /* U3D_QCR3 */
  177. #define QMU_RX_COZ(x) (BIT(16) << (x))
  178. #define QMU_RX_ZLP(x) (BIT(0) << (x))
  179. /* U3D_TXQCSR1 */
  180. /* U3D_RXQCSR1 */
  181. #define QMU_Q_ACTIVE BIT(15)
  182. #define QMU_Q_STOP BIT(2)
  183. #define QMU_Q_RESUME BIT(1)
  184. #define QMU_Q_START BIT(0)
  185. /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
  186. #define QMU_RX_DONE_INT(x) (BIT(16) << (x))
  187. #define QMU_TX_DONE_INT(x) (BIT(0) << (x))
  188. /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
  189. #define RXQ_ZLPERR_INT BIT(20)
  190. #define RXQ_LENERR_INT BIT(18)
  191. #define RXQ_CSERR_INT BIT(17)
  192. #define RXQ_EMPTY_INT BIT(16)
  193. #define TXQ_LENERR_INT BIT(2)
  194. #define TXQ_CSERR_INT BIT(1)
  195. #define TXQ_EMPTY_INT BIT(0)
  196. /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
  197. #define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
  198. #define QMU_TX_CS_ERR(x) (BIT(0) << (x))
  199. /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
  200. #define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
  201. #define QMU_RX_CS_ERR(x) (BIT(0) << (x))
  202. /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
  203. #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
  204. /* U3D_CAP_EPINFO */
  205. #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
  206. #define CAP_TX_EP_NUM(x) ((x) & 0x1f)
  207. /* U3D_MISC_CTRL */
  208. #define VBUS_ON BIT(1)
  209. #define VBUS_FRC_EN BIT(0)
  210. /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
  211. #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
  212. #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
  213. #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
  214. #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
  215. /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
  216. /* U3D_DEVICE_CONF */
  217. #define DEV_ADDR_MSK GENMASK(30, 24)
  218. #define DEV_ADDR(x) ((0x7f & (x)) << 24)
  219. #define HW_USB2_3_SEL BIT(18)
  220. #define SW_USB2_3_SEL_EN BIT(17)
  221. #define SW_USB2_3_SEL BIT(16)
  222. #define SSUSB_DEV_SPEED(x) ((x) & 0x7)
  223. /* U3D_EP_RST */
  224. #define EP1_IN_RST BIT(17)
  225. #define EP1_OUT_RST BIT(1)
  226. #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
  227. #define EP0_RST BIT(0)
  228. /* U3D_DEV_LINK_INTR_ENABLE */
  229. /* U3D_DEV_LINK_INTR */
  230. #define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
  231. /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
  232. #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
  233. #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
  234. #define U3D_LINK_STATE_MACHINE (SSUSB_USB3_MAC_CSR_BASE + 0x0134)
  235. #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
  236. #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
  237. #define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170)
  238. /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
  239. /* U3D_LTSSM_CTRL */
  240. #define FORCE_POLLING_FAIL BIT(4)
  241. #define FORCE_RXDETECT_FAIL BIT(3)
  242. #define SOFT_U3_EXIT_EN BIT(2)
  243. #define COMPLIANCE_EN BIT(1)
  244. #define U1_GO_U2_EN BIT(0)
  245. /* U3D_USB3_CONFIG */
  246. #define USB3_EN BIT(0)
  247. /* U3D_LINK_STATE_MACHINE */
  248. #define LTSSM_STATE(x) ((x) & 0x1f)
  249. /* U3D_LTSSM_INTR_ENABLE */
  250. /* U3D_LTSSM_INTR */
  251. #define U3_RESUME_INTR BIT(18)
  252. #define U3_LFPS_TMOUT_INTR BIT(17)
  253. #define VBUS_FALL_INTR BIT(16)
  254. #define VBUS_RISE_INTR BIT(15)
  255. #define RXDET_SUCCESS_INTR BIT(14)
  256. #define EXIT_U3_INTR BIT(13)
  257. #define EXIT_U2_INTR BIT(12)
  258. #define EXIT_U1_INTR BIT(11)
  259. #define ENTER_U3_INTR BIT(10)
  260. #define ENTER_U2_INTR BIT(9)
  261. #define ENTER_U1_INTR BIT(8)
  262. #define ENTER_U0_INTR BIT(7)
  263. #define RECOVERY_INTR BIT(6)
  264. #define WARM_RST_INTR BIT(5)
  265. #define HOT_RST_INTR BIT(4)
  266. #define LOOPBACK_INTR BIT(3)
  267. #define COMPLIANCE_INTR BIT(2)
  268. #define SS_DISABLE_INTR BIT(1)
  269. #define SS_INACTIVE_INTR BIT(0)
  270. /* U3D_U3U2_SWITCH_CTRL */
  271. #define SOFTCON_CLR_AUTO_EN BIT(0)
  272. /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
  273. #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
  274. #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
  275. #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
  276. /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
  277. /* U3D_LINK_UX_INACT_TIMER */
  278. #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)
  279. #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
  280. #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)
  281. #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
  282. #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
  283. /* U3D_LINK_POWER_CONTROL */
  284. #define SW_U2_ACCEPT_ENABLE BIT(9)
  285. #define SW_U1_ACCEPT_ENABLE BIT(8)
  286. #define UX_EXIT BIT(5)
  287. #define LGO_U3 BIT(4)
  288. #define LGO_U2 BIT(3)
  289. #define LGO_U1 BIT(2)
  290. #define SW_U2_REQUEST_ENABLE BIT(1)
  291. #define SW_U1_REQUEST_ENABLE BIT(0)
  292. /* U3D_LINK_ERR_COUNT */
  293. #define CLR_LINK_ERR_CNT BIT(16)
  294. #define LINK_ERROR_COUNT GENMASK(15, 0)
  295. /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
  296. #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
  297. #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
  298. #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
  299. #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
  300. #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
  301. #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
  302. #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
  303. #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
  304. #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
  305. #define U3D_USB20_OPSTATE (SSUSB_USB2_CSR_BASE + 0x0060)
  306. /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
  307. /* U3D_POWER_MANAGEMENT */
  308. #define LPM_BESL_STALL BIT(14)
  309. #define LPM_BESLD_STALL BIT(13)
  310. #define LPM_RWP BIT(11)
  311. #define LPM_HRWE BIT(10)
  312. #define LPM_MODE(x) (((x) & 0x3) << 8)
  313. #define ISO_UPDATE BIT(7)
  314. #define SOFT_CONN BIT(6)
  315. #define HS_ENABLE BIT(5)
  316. #define RESUME BIT(2)
  317. #define SUSPENDM_ENABLE BIT(0)
  318. /* U3D_DEVICE_CONTROL */
  319. #define DC_HOSTREQ BIT(1)
  320. #define DC_SESSION BIT(0)
  321. /* U3D_USB2_TEST_MODE */
  322. #define U2U3_AUTO_SWITCH BIT(10)
  323. #define LPM_FORCE_STALL BIT(8)
  324. #define FIFO_ACCESS BIT(6)
  325. #define FORCE_FS BIT(5)
  326. #define FORCE_HS BIT(4)
  327. #define TEST_PACKET_MODE BIT(3)
  328. #define TEST_K_MODE BIT(2)
  329. #define TEST_J_MODE BIT(1)
  330. #define TEST_SE0_NAK_MODE BIT(0)
  331. /* U3D_COMMON_USB_INTR_ENABLE */
  332. /* U3D_COMMON_USB_INTR */
  333. #define LPM_RESUME_INTR BIT(9)
  334. #define LPM_INTR BIT(8)
  335. #define DISCONN_INTR BIT(5)
  336. #define CONN_INTR BIT(4)
  337. #define SOF_INTR BIT(3)
  338. #define RESET_INTR BIT(2)
  339. #define RESUME_INTR BIT(1)
  340. #define SUSPEND_INTR BIT(0)
  341. /* U3D_LINK_RESET_INFO */
  342. #define WTCHRP_MSK GENMASK(19, 16)
  343. /* U3D_USB20_LPM_PARAMETER */
  344. #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
  345. #define LPM_BESLCK(x) (((x) & 0xf) << 8)
  346. #define LPM_BESLDCK(x) (((x) & 0xf) << 4)
  347. #define LPM_BESL GENMASK(3, 0)
  348. /* U3D_USB20_MISC_CONTROL */
  349. #define LPM_U3_ACK_EN BIT(0)
  350. /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
  351. #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
  352. #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
  353. #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
  354. #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
  355. #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
  356. #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
  357. #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
  358. #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
  359. #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
  360. #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
  361. #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
  362. #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
  363. #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
  364. #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
  365. #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
  366. #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
  367. #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
  368. #define U3D_SSUSB_IP_TRUNK_VERS (U3D_SSUSB_HW_SUB_ID)
  369. #define U3D_SSUSB_PRB_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x00B0)
  370. #define U3D_SSUSB_PRB_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x00B4)
  371. #define U3D_SSUSB_PRB_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x00B8)
  372. #define U3D_SSUSB_PRB_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x00BC)
  373. #define U3D_SSUSB_PRB_CTRL4 (SSUSB_SIFSLV_IPPC_BASE + 0x00C0)
  374. #define U3D_SSUSB_PRB_CTRL5 (SSUSB_SIFSLV_IPPC_BASE + 0x00C4)
  375. #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
  376. /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
  377. /* U3D_SSUSB_IP_PW_CTRL0 */
  378. #define SSUSB_IP_SW_RST BIT(0)
  379. /* U3D_SSUSB_IP_PW_CTRL1 */
  380. #define SSUSB_IP_HOST_PDN BIT(0)
  381. /* U3D_SSUSB_IP_PW_CTRL2 */
  382. #define SSUSB_IP_DEV_PDN BIT(0)
  383. /* U3D_SSUSB_IP_PW_CTRL3 */
  384. #define SSUSB_IP_PCIE_PDN BIT(0)
  385. /* U3D_SSUSB_IP_PW_STS1 */
  386. #define SSUSB_IP_SLEEP_STS BIT(30)
  387. #define SSUSB_U3_MAC_RST_B_STS BIT(16)
  388. #define SSUSB_XHCI_RST_B_STS BIT(11)
  389. #define SSUSB_SYS125_RST_B_STS BIT(10)
  390. #define SSUSB_REF_RST_B_STS BIT(8)
  391. #define SSUSB_SYSPLL_STABLE BIT(0)
  392. /* U3D_SSUSB_IP_PW_STS2 */
  393. #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
  394. /* U3D_SSUSB_OTG_STS */
  395. #define SSUSB_VBUS_VALID BIT(9)
  396. /* U3D_SSUSB_OTG_STS_CLR */
  397. #define SSUSB_VBUS_INTR_CLR BIT(6)
  398. /* U3D_SSUSB_IP_XHCI_CAP */
  399. #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
  400. #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
  401. /* U3D_SSUSB_IP_DEV_CAP */
  402. #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
  403. /* U3D_SSUSB_OTG_INT_EN */
  404. #define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
  405. #define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
  406. /* U3D_SSUSB_U3_CTRL_0P */
  407. #define SSUSB_U3_PORT_SSP_SPEED BIT(9)
  408. #define SSUSB_U3_PORT_DUAL_MODE BIT(7)
  409. #define SSUSB_U3_PORT_HOST_SEL BIT(2)
  410. #define SSUSB_U3_PORT_PDN BIT(1)
  411. #define SSUSB_U3_PORT_DIS BIT(0)
  412. /* U3D_SSUSB_U2_CTRL_0P */
  413. #define SSUSB_U2_PORT_RG_IDDIG BIT(12)
  414. #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
  415. #define SSUSB_U2_PORT_VBUSVALID BIT(9)
  416. #define SSUSB_U2_PORT_OTG_SEL BIT(7)
  417. #define SSUSB_U2_PORT_HOST BIT(2)
  418. #define SSUSB_U2_PORT_PDN BIT(1)
  419. #define SSUSB_U2_PORT_DIS BIT(0)
  420. #define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
  421. /* U3D_SSUSB_DEV_RST_CTRL */
  422. #define SSUSB_DEV_SW_RST BIT(0)
  423. /* U3D_SSUSB_IP_TRUNK_VERS */
  424. #define IP_TRUNK_VERS(x) (((x) >> 16) & 0xffff)
  425. #endif /* _SSUSB_HW_REGS_H_ */