dwc3-generic.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Generic DWC3 Glue layer
  4. *
  5. * Copyright (C) 2016 - 2018 Xilinx, Inc.
  6. *
  7. * Based on dwc3-omap.c.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <log.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <dwc3-uboot.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/gadget.h>
  20. #include <malloc.h>
  21. #include <usb.h>
  22. #include "core.h"
  23. #include "gadget.h"
  24. #include <reset.h>
  25. #include <clk.h>
  26. #include <usb/xhci.h>
  27. struct dwc3_glue_data {
  28. struct clk_bulk clks;
  29. struct reset_ctl_bulk resets;
  30. fdt_addr_t regs;
  31. };
  32. struct dwc3_generic_plat {
  33. fdt_addr_t base;
  34. u32 maximum_speed;
  35. enum usb_dr_mode dr_mode;
  36. };
  37. struct dwc3_generic_priv {
  38. void *base;
  39. struct dwc3 dwc3;
  40. struct phy_bulk phys;
  41. };
  42. struct dwc3_generic_host_priv {
  43. struct xhci_ctrl xhci_ctrl;
  44. struct dwc3_generic_priv gen_priv;
  45. };
  46. static int dwc3_generic_probe(struct udevice *dev,
  47. struct dwc3_generic_priv *priv)
  48. {
  49. int rc;
  50. struct dwc3_generic_plat *plat = dev_get_plat(dev);
  51. struct dwc3 *dwc3 = &priv->dwc3;
  52. struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
  53. dwc3->dev = dev;
  54. dwc3->maximum_speed = plat->maximum_speed;
  55. dwc3->dr_mode = plat->dr_mode;
  56. #if CONFIG_IS_ENABLED(OF_CONTROL)
  57. dwc3_of_parse(dwc3);
  58. #endif
  59. /*
  60. * It must hold whole USB3.0 OTG controller in resetting to hold pipe
  61. * power state in P2 before initializing TypeC PHY on RK3399 platform.
  62. */
  63. if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
  64. reset_assert_bulk(&glue->resets);
  65. udelay(1);
  66. }
  67. rc = dwc3_setup_phy(dev, &priv->phys);
  68. if (rc && rc != -ENOTSUPP)
  69. return rc;
  70. if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
  71. reset_deassert_bulk(&glue->resets);
  72. priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
  73. dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
  74. rc = dwc3_init(dwc3);
  75. if (rc) {
  76. unmap_physmem(priv->base, MAP_NOCACHE);
  77. return rc;
  78. }
  79. return 0;
  80. }
  81. static int dwc3_generic_remove(struct udevice *dev,
  82. struct dwc3_generic_priv *priv)
  83. {
  84. struct dwc3 *dwc3 = &priv->dwc3;
  85. dwc3_remove(dwc3);
  86. dwc3_shutdown_phy(dev, &priv->phys);
  87. unmap_physmem(dwc3->regs, MAP_NOCACHE);
  88. return 0;
  89. }
  90. static int dwc3_generic_of_to_plat(struct udevice *dev)
  91. {
  92. struct dwc3_generic_plat *plat = dev_get_plat(dev);
  93. ofnode node = dev_ofnode(dev);
  94. plat->base = dev_read_addr(dev);
  95. plat->maximum_speed = usb_get_maximum_speed(node);
  96. if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
  97. pr_info("No USB maximum speed specified. Using super speed\n");
  98. plat->maximum_speed = USB_SPEED_SUPER;
  99. }
  100. plat->dr_mode = usb_get_dr_mode(node);
  101. if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
  102. pr_err("Invalid usb mode setup\n");
  103. return -ENODEV;
  104. }
  105. return 0;
  106. }
  107. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  108. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  109. {
  110. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  111. struct dwc3 *dwc3 = &priv->dwc3;
  112. dwc3_gadget_uboot_handle_interrupt(dwc3);
  113. return 0;
  114. }
  115. static int dwc3_generic_peripheral_probe(struct udevice *dev)
  116. {
  117. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  118. return dwc3_generic_probe(dev, priv);
  119. }
  120. static int dwc3_generic_peripheral_remove(struct udevice *dev)
  121. {
  122. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  123. return dwc3_generic_remove(dev, priv);
  124. }
  125. U_BOOT_DRIVER(dwc3_generic_peripheral) = {
  126. .name = "dwc3-generic-peripheral",
  127. .id = UCLASS_USB_GADGET_GENERIC,
  128. .of_to_plat = dwc3_generic_of_to_plat,
  129. .probe = dwc3_generic_peripheral_probe,
  130. .remove = dwc3_generic_peripheral_remove,
  131. .priv_auto = sizeof(struct dwc3_generic_priv),
  132. .plat_auto = sizeof(struct dwc3_generic_plat),
  133. };
  134. #endif
  135. #if defined(CONFIG_SPL_USB_HOST) || \
  136. !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)
  137. static int dwc3_generic_host_probe(struct udevice *dev)
  138. {
  139. struct xhci_hcor *hcor;
  140. struct xhci_hccr *hccr;
  141. struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
  142. int rc;
  143. rc = dwc3_generic_probe(dev, &priv->gen_priv);
  144. if (rc)
  145. return rc;
  146. hccr = (struct xhci_hccr *)priv->gen_priv.base;
  147. hcor = (struct xhci_hcor *)(priv->gen_priv.base +
  148. HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
  149. return xhci_register(dev, hccr, hcor);
  150. }
  151. static int dwc3_generic_host_remove(struct udevice *dev)
  152. {
  153. struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
  154. int rc;
  155. rc = xhci_deregister(dev);
  156. if (rc)
  157. return rc;
  158. return dwc3_generic_remove(dev, &priv->gen_priv);
  159. }
  160. U_BOOT_DRIVER(dwc3_generic_host) = {
  161. .name = "dwc3-generic-host",
  162. .id = UCLASS_USB,
  163. .of_to_plat = dwc3_generic_of_to_plat,
  164. .probe = dwc3_generic_host_probe,
  165. .remove = dwc3_generic_host_remove,
  166. .priv_auto = sizeof(struct dwc3_generic_host_priv),
  167. .plat_auto = sizeof(struct dwc3_generic_plat),
  168. .ops = &xhci_usb_ops,
  169. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  170. };
  171. #endif
  172. struct dwc3_glue_ops {
  173. void (*select_dr_mode)(struct udevice *dev, int index,
  174. enum usb_dr_mode mode);
  175. };
  176. void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
  177. enum usb_dr_mode mode)
  178. {
  179. #define USBOTGSS_UTMI_OTG_STATUS 0x0084
  180. #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
  181. /* UTMI_OTG_STATUS REGISTER */
  182. #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
  183. #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
  184. #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
  185. #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
  186. #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
  187. #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
  188. #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
  189. enum dwc3_omap_utmi_mode {
  190. DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
  191. DWC3_OMAP_UTMI_MODE_HW,
  192. DWC3_OMAP_UTMI_MODE_SW,
  193. };
  194. u32 use_id_pin;
  195. u32 host_mode;
  196. u32 reg;
  197. u32 utmi_mode;
  198. u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
  199. struct dwc3_glue_data *glue = dev_get_plat(dev);
  200. void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
  201. if (device_is_compatible(dev, "ti,am437x-dwc3"))
  202. utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
  203. utmi_mode = dev_read_u32_default(dev, "utmi-mode",
  204. DWC3_OMAP_UTMI_MODE_UNKNOWN);
  205. if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
  206. debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
  207. dev->name);
  208. mode = USB_DR_MODE_PERIPHERAL;
  209. }
  210. switch (mode) {
  211. case USB_DR_MODE_PERIPHERAL:
  212. use_id_pin = 0;
  213. host_mode = 0;
  214. break;
  215. case USB_DR_MODE_HOST:
  216. use_id_pin = 0;
  217. host_mode = 1;
  218. break;
  219. case USB_DR_MODE_OTG:
  220. default:
  221. use_id_pin = 1;
  222. host_mode = 0;
  223. break;
  224. }
  225. reg = readl(base + utmi_status_offset);
  226. reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
  227. if (!use_id_pin)
  228. reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  229. writel(reg, base + utmi_status_offset);
  230. reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
  231. USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
  232. USBOTGSS_UTMI_OTG_STATUS_IDDIG);
  233. reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
  234. USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  235. if (!host_mode)
  236. reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
  237. USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
  238. writel(reg, base + utmi_status_offset);
  239. unmap_physmem(base, MAP_NOCACHE);
  240. }
  241. struct dwc3_glue_ops ti_ops = {
  242. .select_dr_mode = dwc3_ti_select_dr_mode,
  243. };
  244. static int dwc3_glue_bind(struct udevice *parent)
  245. {
  246. ofnode node;
  247. int ret;
  248. ofnode_for_each_subnode(node, dev_ofnode(parent)) {
  249. const char *name = ofnode_get_name(node);
  250. enum usb_dr_mode dr_mode;
  251. struct udevice *dev;
  252. const char *driver = NULL;
  253. debug("%s: subnode name: %s\n", __func__, name);
  254. dr_mode = usb_get_dr_mode(node);
  255. switch (dr_mode) {
  256. case USB_DR_MODE_PERIPHERAL:
  257. case USB_DR_MODE_OTG:
  258. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  259. debug("%s: dr_mode: OTG or Peripheral\n", __func__);
  260. driver = "dwc3-generic-peripheral";
  261. #endif
  262. break;
  263. #if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
  264. case USB_DR_MODE_HOST:
  265. debug("%s: dr_mode: HOST\n", __func__);
  266. driver = "dwc3-generic-host";
  267. break;
  268. #endif
  269. default:
  270. debug("%s: unsupported dr_mode\n", __func__);
  271. return -ENODEV;
  272. };
  273. if (!driver)
  274. continue;
  275. ret = device_bind_driver_to_node(parent, driver, name,
  276. node, &dev);
  277. if (ret) {
  278. debug("%s: not able to bind usb device mode\n",
  279. __func__);
  280. return ret;
  281. }
  282. }
  283. return 0;
  284. }
  285. static int dwc3_glue_reset_init(struct udevice *dev,
  286. struct dwc3_glue_data *glue)
  287. {
  288. int ret;
  289. ret = reset_get_bulk(dev, &glue->resets);
  290. if (ret == -ENOTSUPP || ret == -ENOENT)
  291. return 0;
  292. else if (ret)
  293. return ret;
  294. ret = reset_deassert_bulk(&glue->resets);
  295. if (ret) {
  296. reset_release_bulk(&glue->resets);
  297. return ret;
  298. }
  299. return 0;
  300. }
  301. static int dwc3_glue_clk_init(struct udevice *dev,
  302. struct dwc3_glue_data *glue)
  303. {
  304. int ret;
  305. ret = clk_get_bulk(dev, &glue->clks);
  306. if (ret == -ENOSYS || ret == -ENOENT)
  307. return 0;
  308. if (ret)
  309. return ret;
  310. #if CONFIG_IS_ENABLED(CLK)
  311. ret = clk_enable_bulk(&glue->clks);
  312. if (ret) {
  313. clk_release_bulk(&glue->clks);
  314. return ret;
  315. }
  316. #endif
  317. return 0;
  318. }
  319. static int dwc3_glue_probe(struct udevice *dev)
  320. {
  321. struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
  322. struct dwc3_glue_data *glue = dev_get_plat(dev);
  323. struct udevice *child = NULL;
  324. int index = 0;
  325. int ret;
  326. glue->regs = dev_read_addr(dev);
  327. ret = dwc3_glue_clk_init(dev, glue);
  328. if (ret)
  329. return ret;
  330. ret = dwc3_glue_reset_init(dev, glue);
  331. if (ret)
  332. return ret;
  333. ret = device_find_first_child(dev, &child);
  334. if (ret)
  335. return ret;
  336. if (glue->resets.count == 0) {
  337. ret = dwc3_glue_reset_init(child, glue);
  338. if (ret)
  339. return ret;
  340. }
  341. while (child) {
  342. enum usb_dr_mode dr_mode;
  343. dr_mode = usb_get_dr_mode(dev_ofnode(child));
  344. device_find_next_child(&child);
  345. if (ops && ops->select_dr_mode)
  346. ops->select_dr_mode(dev, index, dr_mode);
  347. index++;
  348. }
  349. return 0;
  350. }
  351. static int dwc3_glue_remove(struct udevice *dev)
  352. {
  353. struct dwc3_glue_data *glue = dev_get_plat(dev);
  354. reset_release_bulk(&glue->resets);
  355. clk_release_bulk(&glue->clks);
  356. return 0;
  357. }
  358. static const struct udevice_id dwc3_glue_ids[] = {
  359. { .compatible = "xlnx,zynqmp-dwc3" },
  360. { .compatible = "xlnx,versal-dwc3" },
  361. { .compatible = "ti,keystone-dwc3"},
  362. { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
  363. { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
  364. { .compatible = "ti,am654-dwc3" },
  365. { .compatible = "rockchip,rk3328-dwc3" },
  366. { .compatible = "rockchip,rk3399-dwc3" },
  367. { .compatible = "qcom,dwc3" },
  368. { .compatible = "intel,tangier-dwc3" },
  369. { }
  370. };
  371. U_BOOT_DRIVER(dwc3_generic_wrapper) = {
  372. .name = "dwc3-generic-wrapper",
  373. .id = UCLASS_NOP,
  374. .of_match = dwc3_glue_ids,
  375. .bind = dwc3_glue_bind,
  376. .probe = dwc3_glue_probe,
  377. .remove = dwc3_glue_remove,
  378. .plat_auto = sizeof(struct dwc3_glue_data),
  379. };