soc.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/bootm.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/dma.h>
  20. #include <asm/mach-imx/hab.h>
  21. #include <stdbool.h>
  22. #include <asm/arch/mxc_hdmi.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <dm.h>
  25. #include <fsl_sec.h>
  26. #include <imx_thermal.h>
  27. #include <mmc.h>
  28. #define has_err007805() \
  29. (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
  30. struct scu_regs {
  31. u32 ctrl;
  32. u32 config;
  33. u32 status;
  34. u32 invalidate;
  35. u32 fpga_rev;
  36. };
  37. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL)
  38. static const struct imx_thermal_plat imx6_thermal_plat = {
  39. .regs = (void *)ANATOP_BASE_ADDR,
  40. .fuse_bank = 1,
  41. .fuse_word = 6,
  42. };
  43. U_BOOT_DRVINFO(imx6_thermal) = {
  44. .name = "imx_thermal",
  45. .plat = &imx6_thermal_plat,
  46. };
  47. #endif
  48. #if defined(CONFIG_IMX_HAB)
  49. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  50. .bank = 0,
  51. .word = 6,
  52. };
  53. #endif
  54. u32 get_nr_cpus(void)
  55. {
  56. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  57. return readl(&scu->config) & 3;
  58. }
  59. u32 get_cpu_rev(void)
  60. {
  61. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  62. u32 reg = readl(&anatop->digprog_sololite);
  63. u32 type = ((reg >> 16) & 0xff);
  64. u32 major, cfg = 0;
  65. if (type != MXC_CPU_MX6SL) {
  66. reg = readl(&anatop->digprog);
  67. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  68. cfg = readl(&scu->config) & 3;
  69. type = ((reg >> 16) & 0xff);
  70. if (type == MXC_CPU_MX6DL) {
  71. if (!cfg)
  72. type = MXC_CPU_MX6SOLO;
  73. }
  74. if (type == MXC_CPU_MX6Q) {
  75. if (cfg == 1)
  76. type = MXC_CPU_MX6D;
  77. }
  78. if (type == MXC_CPU_MX6ULL) {
  79. if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
  80. type = MXC_CPU_MX6ULZ;
  81. }
  82. }
  83. major = ((reg >> 8) & 0xff);
  84. if ((major >= 1) &&
  85. ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  86. major--;
  87. type = MXC_CPU_MX6QP;
  88. if (cfg == 1)
  89. type = MXC_CPU_MX6DP;
  90. }
  91. reg &= 0xff; /* mx6 silicon revision */
  92. /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
  93. if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
  94. reg = 0x3;
  95. return (type << 12) | (reg + (0x10 * (major + 1)));
  96. }
  97. /*
  98. * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
  99. * defines a 2-bit SPEED_GRADING
  100. */
  101. #define OCOTP_CFG3_SPEED_SHIFT 16
  102. #define OCOTP_CFG3_SPEED_800MHZ 0
  103. #define OCOTP_CFG3_SPEED_850MHZ 1
  104. #define OCOTP_CFG3_SPEED_1GHZ 2
  105. #define OCOTP_CFG3_SPEED_1P2GHZ 3
  106. /*
  107. * For i.MX6UL
  108. */
  109. #define OCOTP_CFG3_SPEED_528MHZ 1
  110. #define OCOTP_CFG3_SPEED_696MHZ 2
  111. /*
  112. * For i.MX6ULL
  113. */
  114. #define OCOTP_CFG3_SPEED_792MHZ 2
  115. #define OCOTP_CFG3_SPEED_900MHZ 3
  116. u32 get_cpu_speed_grade_hz(void)
  117. {
  118. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  119. struct fuse_bank *bank = &ocotp->bank[0];
  120. struct fuse_bank0_regs *fuse =
  121. (struct fuse_bank0_regs *)bank->fuse_regs;
  122. uint32_t val;
  123. val = readl(&fuse->cfg3);
  124. val >>= OCOTP_CFG3_SPEED_SHIFT;
  125. val &= 0x3;
  126. if (is_mx6ul()) {
  127. if (val == OCOTP_CFG3_SPEED_528MHZ)
  128. return 528000000;
  129. else if (val == OCOTP_CFG3_SPEED_696MHZ)
  130. return 696000000;
  131. else
  132. return 0;
  133. }
  134. if (is_mx6ull()) {
  135. if (val == OCOTP_CFG3_SPEED_528MHZ)
  136. return 528000000;
  137. else if (val == OCOTP_CFG3_SPEED_792MHZ)
  138. return 792000000;
  139. else if (val == OCOTP_CFG3_SPEED_900MHZ)
  140. return 900000000;
  141. else
  142. return 0;
  143. }
  144. switch (val) {
  145. /* Valid for IMX6DQ */
  146. case OCOTP_CFG3_SPEED_1P2GHZ:
  147. if (is_mx6dq() || is_mx6dqp())
  148. return 1200000000;
  149. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  150. case OCOTP_CFG3_SPEED_1GHZ:
  151. return 996000000;
  152. /* Valid for IMX6DQ */
  153. case OCOTP_CFG3_SPEED_850MHZ:
  154. if (is_mx6dq() || is_mx6dqp())
  155. return 852000000;
  156. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  157. case OCOTP_CFG3_SPEED_800MHZ:
  158. return 792000000;
  159. }
  160. return 0;
  161. }
  162. /*
  163. * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
  164. * defines a 2-bit Temperature Grade
  165. *
  166. * return temperature grade and min/max temperature in Celsius
  167. */
  168. #define OCOTP_MEM0_TEMP_SHIFT 6
  169. u32 get_cpu_temp_grade(int *minc, int *maxc)
  170. {
  171. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  172. struct fuse_bank *bank = &ocotp->bank[1];
  173. struct fuse_bank1_regs *fuse =
  174. (struct fuse_bank1_regs *)bank->fuse_regs;
  175. uint32_t val;
  176. val = readl(&fuse->mem0);
  177. val >>= OCOTP_MEM0_TEMP_SHIFT;
  178. val &= 0x3;
  179. if (minc && maxc) {
  180. if (val == TEMP_AUTOMOTIVE) {
  181. *minc = -40;
  182. *maxc = 125;
  183. } else if (val == TEMP_INDUSTRIAL) {
  184. *minc = -40;
  185. *maxc = 105;
  186. } else if (val == TEMP_EXTCOMMERCIAL) {
  187. *minc = -20;
  188. *maxc = 105;
  189. } else {
  190. *minc = 0;
  191. *maxc = 95;
  192. }
  193. }
  194. return val;
  195. }
  196. #ifdef CONFIG_REVISION_TAG
  197. u32 __weak get_board_rev(void)
  198. {
  199. u32 cpurev = get_cpu_rev();
  200. u32 type = ((cpurev >> 12) & 0xff);
  201. if (type == MXC_CPU_MX6SOLO)
  202. cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  203. if (type == MXC_CPU_MX6D)
  204. cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  205. return cpurev;
  206. }
  207. #endif
  208. static void clear_ldo_ramp(void)
  209. {
  210. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  211. int reg;
  212. /* ROM may modify LDO ramp up time according to fuse setting, so in
  213. * order to be in the safe side we neeed to reset these settings to
  214. * match the reset value: 0'b00
  215. */
  216. reg = readl(&anatop->ana_misc2);
  217. reg &= ~(0x3f << 24);
  218. writel(reg, &anatop->ana_misc2);
  219. }
  220. /*
  221. * Set the PMU_REG_CORE register
  222. *
  223. * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
  224. * Possible values are from 0.725V to 1.450V in steps of
  225. * 0.025V (25mV).
  226. */
  227. int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
  228. {
  229. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  230. u32 val, step, old, reg = readl(&anatop->reg_core);
  231. u8 shift;
  232. /* No LDO_SOC/PU/ARM */
  233. if (is_mx6sll())
  234. return 0;
  235. if (mv < 725)
  236. val = 0x00; /* Power gated off */
  237. else if (mv > 1450)
  238. val = 0x1F; /* Power FET switched full on. No regulation */
  239. else
  240. val = (mv - 700) / 25;
  241. clear_ldo_ramp();
  242. switch (ldo) {
  243. case LDO_SOC:
  244. shift = 18;
  245. break;
  246. case LDO_PU:
  247. shift = 9;
  248. break;
  249. case LDO_ARM:
  250. shift = 0;
  251. break;
  252. default:
  253. return -EINVAL;
  254. }
  255. old = (reg & (0x1F << shift)) >> shift;
  256. step = abs(val - old);
  257. if (step == 0)
  258. return 0;
  259. reg = (reg & ~(0x1F << shift)) | (val << shift);
  260. writel(reg, &anatop->reg_core);
  261. /*
  262. * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
  263. * step
  264. */
  265. udelay(3 * step);
  266. return 0;
  267. }
  268. static void set_ahb_rate(u32 val)
  269. {
  270. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  271. u32 reg, div;
  272. div = get_periph_clk() / val - 1;
  273. reg = readl(&mxc_ccm->cbcdr);
  274. writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
  275. (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
  276. }
  277. static void clear_mmdc_ch_mask(void)
  278. {
  279. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  280. u32 reg;
  281. reg = readl(&mxc_ccm->ccdr);
  282. /* Clear MMDC channel mask */
  283. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
  284. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
  285. else
  286. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
  287. writel(reg, &mxc_ccm->ccdr);
  288. }
  289. #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
  290. static void init_bandgap(void)
  291. {
  292. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  293. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  294. struct fuse_bank *bank = &ocotp->bank[1];
  295. struct fuse_bank1_regs *fuse =
  296. (struct fuse_bank1_regs *)bank->fuse_regs;
  297. uint32_t val;
  298. /*
  299. * Ensure the bandgap has stabilized.
  300. */
  301. while (!(readl(&anatop->ana_misc0) & 0x80))
  302. ;
  303. /*
  304. * For best noise performance of the analog blocks using the
  305. * outputs of the bandgap, the reftop_selfbiasoff bit should
  306. * be set.
  307. */
  308. writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
  309. /*
  310. * On i.MX6ULL,we need to set VBGADJ bits according to the
  311. * REFTOP_TRIM[3:0] in fuse table
  312. * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  313. * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  314. * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  315. * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  316. * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  317. * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  318. * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  319. * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
  320. */
  321. if (is_mx6ull()) {
  322. val = readl(&fuse->mem0);
  323. val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  324. val &= 0x7;
  325. writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  326. &anatop->ana_misc0_set);
  327. }
  328. }
  329. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  330. static void noc_setup(void)
  331. {
  332. enable_ipu_clock();
  333. writel(0x80000201, 0xbb0608);
  334. /* Bypass IPU1 QoS generator */
  335. writel(0x00000002, 0x00bb048c);
  336. /* Bypass IPU2 QoS generator */
  337. writel(0x00000002, 0x00bb050c);
  338. /* Bandwidth THR for of PRE0 */
  339. writel(0x00000200, 0x00bb0690);
  340. /* Bandwidth THR for of PRE1 */
  341. writel(0x00000200, 0x00bb0710);
  342. /* Bandwidth THR for of PRE2 */
  343. writel(0x00000200, 0x00bb0790);
  344. /* Bandwidth THR for of PRE3 */
  345. writel(0x00000200, 0x00bb0810);
  346. /* Saturation THR for of PRE0 */
  347. writel(0x00000010, 0x00bb0694);
  348. /* Saturation THR for of PRE1 */
  349. writel(0x00000010, 0x00bb0714);
  350. /* Saturation THR for of PRE2 */
  351. writel(0x00000010, 0x00bb0794);
  352. /* Saturation THR for of PRE */
  353. writel(0x00000010, 0x00bb0814);
  354. disable_ipu_clock();
  355. }
  356. #endif
  357. int arch_cpu_init(void)
  358. {
  359. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  360. init_aips();
  361. /* Need to clear MMDC_CHx_MASK to make warm reset work. */
  362. clear_mmdc_ch_mask();
  363. /*
  364. * Disable self-bias circuit in the analog bandap.
  365. * The self-bias circuit is used by the bandgap during startup.
  366. * This bit should be set after the bandgap has initialized.
  367. */
  368. init_bandgap();
  369. if (!is_mx6ul() && !is_mx6ull()) {
  370. /*
  371. * When low freq boot is enabled, ROM will not set AHB
  372. * freq, so we need to ensure AHB freq is 132MHz in such
  373. * scenario.
  374. *
  375. * To i.MX6UL, when power up, default ARM core and
  376. * AHB rate is 396M and 132M.
  377. */
  378. if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
  379. set_ahb_rate(132000000);
  380. }
  381. if (is_mx6ul()) {
  382. if (is_soc_rev(CHIP_REV_1_0) == 0) {
  383. /*
  384. * According to the design team's requirement on
  385. * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
  386. * as open drain 100K (0x0000b8a0).
  387. * Only exists on TO1.0
  388. */
  389. writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  390. } else {
  391. /*
  392. * From TO1.1, SNVS adds internal pull up control
  393. * for POR_B, the register filed is GPBIT[1:0],
  394. * after system boot up, it can be set to 2b'01
  395. * to disable internal pull up.It can save about
  396. * 30uA power in SNVS mode.
  397. */
  398. writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
  399. (~0x1400)) | 0x400,
  400. MX6UL_SNVS_LP_BASE_ADDR + 0x10);
  401. }
  402. }
  403. if (is_mx6ull()) {
  404. /*
  405. * GPBIT[1:0] is suggested to set to 2'b11:
  406. * 2'b00 : always PUP100K
  407. * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
  408. * 2'b10 : always disable PUP100K
  409. * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
  410. * register offset is different from i.MX6UL, since
  411. * i.MX6UL is fixed by ECO.
  412. */
  413. writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
  414. 0x3, MX6UL_SNVS_LP_BASE_ADDR);
  415. }
  416. /* Set perclk to source from OSC 24MHz */
  417. if (has_err007805())
  418. setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
  419. imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
  420. if (is_mx6sx())
  421. setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
  422. init_src();
  423. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  424. if (is_mx6dqp())
  425. noc_setup();
  426. #endif
  427. return 0;
  428. }
  429. #ifdef CONFIG_ENV_IS_IN_MMC
  430. __weak int board_mmc_get_env_dev(int devno)
  431. {
  432. return CONFIG_SYS_MMC_ENV_DEV;
  433. }
  434. static int mmc_get_boot_dev(void)
  435. {
  436. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  437. u32 soc_sbmr = readl(&src_regs->sbmr1);
  438. u32 bootsel;
  439. int devno;
  440. /*
  441. * Refer to
  442. * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
  443. * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
  444. * i.MX6SL/SX/UL has same layout.
  445. */
  446. bootsel = (soc_sbmr & 0x000000FF) >> 6;
  447. /* No boot from sd/mmc */
  448. if (bootsel != 1)
  449. return -1;
  450. /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  451. devno = (soc_sbmr & 0x00001800) >> 11;
  452. return devno;
  453. }
  454. int mmc_get_env_dev(void)
  455. {
  456. int devno = mmc_get_boot_dev();
  457. /* If not boot from sd/mmc, use default value */
  458. if (devno < 0)
  459. return CONFIG_SYS_MMC_ENV_DEV;
  460. return board_mmc_get_env_dev(devno);
  461. }
  462. #ifdef CONFIG_SYS_MMC_ENV_PART
  463. __weak int board_mmc_get_env_part(int devno)
  464. {
  465. return CONFIG_SYS_MMC_ENV_PART;
  466. }
  467. uint mmc_get_env_part(struct mmc *mmc)
  468. {
  469. int devno = mmc_get_boot_dev();
  470. /* If not boot from sd/mmc, use default value */
  471. if (devno < 0)
  472. return CONFIG_SYS_MMC_ENV_PART;
  473. return board_mmc_get_env_part(devno);
  474. }
  475. #endif
  476. #endif
  477. int board_postclk_init(void)
  478. {
  479. /* NO LDO SOC on i.MX6SLL */
  480. if (is_mx6sll())
  481. return 0;
  482. set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
  483. return 0;
  484. }
  485. #ifndef CONFIG_SPL_BUILD
  486. /*
  487. * cfg_val will be used for
  488. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  489. * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
  490. * instead of SBMR1 to determine the boot device.
  491. */
  492. const struct boot_mode soc_boot_modes[] = {
  493. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  494. /* reserved value should start rom usb */
  495. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  496. {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  497. #else
  498. {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  499. #endif
  500. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  501. {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  502. {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  503. {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  504. {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  505. /* 4 bit bus width */
  506. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  507. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  508. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  509. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  510. {NULL, 0},
  511. };
  512. #endif
  513. void reset_misc(void)
  514. {
  515. #ifndef CONFIG_SPL_BUILD
  516. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  517. lcdif_power_down();
  518. #endif
  519. #endif
  520. }
  521. void s_init(void)
  522. {
  523. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  524. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  525. u32 mask480;
  526. u32 mask528;
  527. u32 reg, periph1, periph2;
  528. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
  529. return;
  530. /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
  531. * to make sure PFD is working right, otherwise, PFDs may
  532. * not output clock after reset, MX6DL and MX6SL have added 396M pfd
  533. * workaround in ROM code, as bus clock need it
  534. */
  535. mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
  536. ANATOP_PFD_CLKGATE_MASK(1) |
  537. ANATOP_PFD_CLKGATE_MASK(2) |
  538. ANATOP_PFD_CLKGATE_MASK(3);
  539. mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
  540. ANATOP_PFD_CLKGATE_MASK(3);
  541. reg = readl(&ccm->cbcmr);
  542. periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
  543. >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
  544. periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
  545. >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
  546. /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
  547. if ((periph2 != 0x2) && (periph1 != 0x2))
  548. mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
  549. if ((periph2 != 0x1) && (periph1 != 0x1) &&
  550. (periph2 != 0x3) && (periph1 != 0x3))
  551. mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
  552. writel(mask480, &anatop->pfd_480_set);
  553. writel(mask528, &anatop->pfd_528_set);
  554. writel(mask480, &anatop->pfd_480_clr);
  555. writel(mask528, &anatop->pfd_528_clr);
  556. }
  557. #ifdef CONFIG_IMX_HDMI
  558. void imx_enable_hdmi_phy(void)
  559. {
  560. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  561. u8 reg;
  562. reg = readb(&hdmi->phy_conf0);
  563. reg |= HDMI_PHY_CONF0_PDZ_MASK;
  564. writeb(reg, &hdmi->phy_conf0);
  565. udelay(3000);
  566. reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
  567. writeb(reg, &hdmi->phy_conf0);
  568. udelay(3000);
  569. reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
  570. writeb(reg, &hdmi->phy_conf0);
  571. writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
  572. }
  573. void imx_setup_hdmi(void)
  574. {
  575. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  576. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  577. int reg, count;
  578. u8 val;
  579. /* Turn on HDMI PHY clock */
  580. reg = readl(&mxc_ccm->CCGR2);
  581. reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
  582. MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
  583. writel(reg, &mxc_ccm->CCGR2);
  584. writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
  585. reg = readl(&mxc_ccm->chsccdr);
  586. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
  587. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
  588. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  589. reg |= (CHSCCDR_PODF_DIVIDE_BY_3
  590. << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  591. |(CHSCCDR_IPU_PRE_CLK_540M_PFD
  592. << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  593. writel(reg, &mxc_ccm->chsccdr);
  594. /* Clear the overflow condition */
  595. if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
  596. /* TMDS software reset */
  597. writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
  598. val = readb(&hdmi->fc_invidconf);
  599. /* Need minimum 3 times to write to clear the register */
  600. for (count = 0 ; count < 5 ; count++)
  601. writeb(val, &hdmi->fc_invidconf);
  602. }
  603. }
  604. #endif
  605. #ifdef CONFIG_ARCH_MISC_INIT
  606. /*
  607. * UNIQUE_ID describes a unique ID based on silicon wafer
  608. * and die X/Y position
  609. *
  610. * UNIQUE_ID offset 0x410
  611. * 31:0 fuse 0
  612. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  613. *
  614. * UNIQUE_ID offset 0x420
  615. * 31:24 fuse 1
  616. * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  617. * 23:16 fuse 1
  618. * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  619. * 15:11 fuse 1
  620. * The wafer number of the wafer on which the device was fabricated/SJC
  621. * CHALLENGE/ Unique ID
  622. * 10:0 fuse 1
  623. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  624. */
  625. static void setup_serial_number(void)
  626. {
  627. char serial_string[17];
  628. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  629. struct fuse_bank *bank = &ocotp->bank[0];
  630. struct fuse_bank0_regs *fuse =
  631. (struct fuse_bank0_regs *)bank->fuse_regs;
  632. if (env_get("serial#"))
  633. return;
  634. snprintf(serial_string, sizeof(serial_string), "%08x%08x",
  635. fuse->uid_low, fuse->uid_high);
  636. env_set("serial#", serial_string);
  637. }
  638. int arch_misc_init(void)
  639. {
  640. #ifdef CONFIG_FSL_CAAM
  641. sec_init();
  642. #endif
  643. setup_serial_number();
  644. return 0;
  645. }
  646. #endif
  647. /*
  648. * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
  649. * MX6Q and MX6QP processors
  650. */
  651. void gpr_init(void)
  652. {
  653. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  654. /*
  655. * If this function is used in a common MX6 spl implementation
  656. * we have to ensure that it is only called for suitable cpu types,
  657. * otherwise it breaks hardware parts like enet1, can1, can2, etc.
  658. */
  659. if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
  660. return;
  661. /* enable AXI cache for VDOA/VPU/IPU */
  662. writel(0xF00000CF, &iomux->gpr[4]);
  663. if (is_mx6dqp()) {
  664. /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
  665. writel(0x77177717, &iomux->gpr[6]);
  666. writel(0x77177717, &iomux->gpr[7]);
  667. } else {
  668. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  669. writel(0x007F007F, &iomux->gpr[6]);
  670. writel(0x007F007F, &iomux->gpr[7]);
  671. }
  672. }