ddr.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <log.h>
  9. #include <linux/delay.h>
  10. #include <linux/types.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/io.h>
  15. #include <asm/types.h>
  16. #include <wait_bit.h>
  17. #if defined(CONFIG_MX6_DDRCAL)
  18. static void reset_read_data_fifos(void)
  19. {
  20. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  21. /* Reset data FIFOs twice. */
  22. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  23. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  24. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  25. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  26. }
  27. static void precharge_all(const bool cs0_enable, const bool cs1_enable)
  28. {
  29. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  30. /*
  31. * Issue the Precharge-All command to the DDR device for both
  32. * chip selects. Note, CON_REQ bit should also remain set. If
  33. * only using one chip select, then precharge only the desired
  34. * chip select.
  35. */
  36. if (cs0_enable) { /* CS0 */
  37. writel(0x04008050, &mmdc0->mdscr);
  38. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  39. }
  40. if (cs1_enable) { /* CS1 */
  41. writel(0x04008058, &mmdc0->mdscr);
  42. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  43. }
  44. }
  45. static void force_delay_measurement(int bus_size)
  46. {
  47. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  48. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  49. writel(0x800, &mmdc0->mpmur0);
  50. if (bus_size == 0x2)
  51. writel(0x800, &mmdc1->mpmur0);
  52. }
  53. static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
  54. {
  55. u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
  56. /*
  57. * DQS gating absolute offset should be modified from reflecting
  58. * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
  59. */
  60. val_ctrl = readl(reg_ctrl);
  61. val_ctrl &= 0xf0000000;
  62. dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
  63. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  64. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  65. val_ctrl |= dg_dl_abs_offset + dg_hc_del;
  66. dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
  67. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  68. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  69. val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
  70. writel(val_ctrl, reg_ctrl);
  71. }
  72. static void correct_mpwldectr_result(void *reg)
  73. {
  74. /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
  75. const unsigned int limit = 0x148;
  76. u32 val = readl(reg);
  77. u32 old = val;
  78. if ((val & 0x17f) > limit)
  79. val &= 0xffff << 16;
  80. if (((val >> 16) & 0x17f) > limit)
  81. val &= 0xffff;
  82. if (old != val)
  83. writel(val, reg);
  84. }
  85. int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  86. {
  87. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  88. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  89. u32 esdmisc_val, zq_val;
  90. u32 errors = 0;
  91. u32 ldectrl[4] = {0};
  92. u32 ddr_mr1 = 0x4;
  93. u32 rwalat_max;
  94. /*
  95. * Stash old values in case calibration fails,
  96. * we need to restore them
  97. */
  98. ldectrl[0] = readl(&mmdc0->mpwldectrl0);
  99. ldectrl[1] = readl(&mmdc0->mpwldectrl1);
  100. if (sysinfo->dsize == 2) {
  101. ldectrl[2] = readl(&mmdc1->mpwldectrl0);
  102. ldectrl[3] = readl(&mmdc1->mpwldectrl1);
  103. }
  104. /* disable DDR logic power down timer */
  105. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  106. /* disable Adopt power down timer */
  107. setbits_le32(&mmdc0->mapsr, 0x1);
  108. debug("Starting write leveling calibration.\n");
  109. /*
  110. * 2. disable auto refresh and ZQ calibration
  111. * before proceeding with Write Leveling calibration
  112. */
  113. esdmisc_val = readl(&mmdc0->mdref);
  114. writel(0x0000C000, &mmdc0->mdref);
  115. zq_val = readl(&mmdc0->mpzqhwctrl);
  116. writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
  117. /* 3. increase walat and ralat to maximum */
  118. rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
  119. setbits_le32(&mmdc0->mdmisc, rwalat_max);
  120. if (sysinfo->dsize == 2)
  121. setbits_le32(&mmdc1->mdmisc, rwalat_max);
  122. /*
  123. * 4 & 5. Configure the external DDR device to enter write-leveling
  124. * mode through Load Mode Register command.
  125. * Register setting:
  126. * Bits[31:16] MR1 value (0x0080 write leveling enable)
  127. * Bit[9] set WL_EN to enable MMDC DQS output
  128. * Bits[6:4] set CMD bits for Load Mode Register programming
  129. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  130. */
  131. writel(0x00808231, &mmdc0->mdscr);
  132. /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
  133. writel(0x00000001, &mmdc0->mpwlgcr);
  134. /*
  135. * 7. Upon completion of this process the MMDC de-asserts
  136. * the MPWLGCR[HW_WL_EN]
  137. */
  138. wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
  139. /*
  140. * 8. check for any errors: check both PHYs for x64 configuration,
  141. * if x32, check only PHY0
  142. */
  143. if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
  144. errors |= 1;
  145. if (sysinfo->dsize == 2)
  146. if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
  147. errors |= 2;
  148. debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
  149. /* check to see if cal failed */
  150. if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
  151. (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
  152. ((sysinfo->dsize < 2) ||
  153. ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
  154. (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
  155. debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
  156. writel(ldectrl[0], &mmdc0->mpwldectrl0);
  157. writel(ldectrl[1], &mmdc0->mpwldectrl1);
  158. if (sysinfo->dsize == 2) {
  159. writel(ldectrl[2], &mmdc1->mpwldectrl0);
  160. writel(ldectrl[3], &mmdc1->mpwldectrl1);
  161. }
  162. errors |= 4;
  163. }
  164. correct_mpwldectr_result(&mmdc0->mpwldectrl0);
  165. correct_mpwldectr_result(&mmdc0->mpwldectrl1);
  166. if (sysinfo->dsize == 2) {
  167. correct_mpwldectr_result(&mmdc1->mpwldectrl0);
  168. correct_mpwldectr_result(&mmdc1->mpwldectrl1);
  169. }
  170. /*
  171. * User should issue MRS command to exit write leveling mode
  172. * through Load Mode Register command
  173. * Register setting:
  174. * Bits[31:16] MR1 value "ddr_mr1" value from initialization
  175. * Bit[9] clear WL_EN to disable MMDC DQS output
  176. * Bits[6:4] set CMD bits for Load Mode Register programming
  177. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  178. */
  179. writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
  180. /* re-enable auto refresh and zq cal */
  181. writel(esdmisc_val, &mmdc0->mdref);
  182. writel(zq_val, &mmdc0->mpzqhwctrl);
  183. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  184. readl(&mmdc0->mpwldectrl0));
  185. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  186. readl(&mmdc0->mpwldectrl1));
  187. if (sysinfo->dsize == 2) {
  188. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  189. readl(&mmdc1->mpwldectrl0));
  190. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  191. readl(&mmdc1->mpwldectrl1));
  192. }
  193. /* We must force a readback of these values, to get them to stick */
  194. readl(&mmdc0->mpwldectrl0);
  195. readl(&mmdc0->mpwldectrl1);
  196. if (sysinfo->dsize == 2) {
  197. readl(&mmdc1->mpwldectrl0);
  198. readl(&mmdc1->mpwldectrl1);
  199. }
  200. /* enable DDR logic power down timer: */
  201. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  202. /* Enable Adopt power down timer: */
  203. clrbits_le32(&mmdc0->mapsr, 0x1);
  204. /* Clear CON_REQ */
  205. writel(0, &mmdc0->mdscr);
  206. return errors;
  207. }
  208. static void mmdc_set_sdqs(bool set)
  209. {
  210. struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
  211. (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  212. struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
  213. (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  214. struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
  215. (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  216. struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
  217. (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
  218. struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
  219. (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  220. int i, sdqs_cnt;
  221. u32 sdqs;
  222. if (is_mx6sx()) {
  223. sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
  224. sdqs_cnt = 2;
  225. } else if (is_mx6sl()) {
  226. sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
  227. sdqs_cnt = 2;
  228. } else if (is_mx6ul() || is_mx6ull()) {
  229. sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
  230. sdqs_cnt = 2;
  231. } else if (is_mx6sdl()) {
  232. sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
  233. sdqs_cnt = 8;
  234. } else { /* MX6DQ */
  235. sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
  236. sdqs_cnt = 8;
  237. }
  238. for (i = 0; i < sdqs_cnt; i++) {
  239. if (set)
  240. setbits_le32(sdqs + (4 * i), 0x7000);
  241. else
  242. clrbits_le32(sdqs + (4 * i), 0x7000);
  243. }
  244. }
  245. int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  246. {
  247. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  248. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  249. bool cs0_enable;
  250. bool cs1_enable;
  251. bool cs0_enable_initial;
  252. bool cs1_enable_initial;
  253. u32 esdmisc_val;
  254. u32 temp_ref;
  255. u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
  256. u32 errors = 0;
  257. u32 initdelay = 0x40404040;
  258. /* check to see which chip selects are enabled */
  259. cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
  260. cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
  261. /* disable DDR logic power down timer: */
  262. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  263. /* disable Adopt power down timer: */
  264. setbits_le32(&mmdc0->mapsr, 0x1);
  265. /* set DQS pull ups */
  266. mmdc_set_sdqs(true);
  267. /* Save old RALAT and WALAT values */
  268. esdmisc_val = readl(&mmdc0->mdmisc);
  269. setbits_le32(&mmdc0->mdmisc,
  270. (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
  271. /* Disable auto refresh before proceeding with calibration */
  272. temp_ref = readl(&mmdc0->mdref);
  273. writel(0x0000c000, &mmdc0->mdref);
  274. /*
  275. * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
  276. * this also sets the CON_REQ bit.
  277. */
  278. if (cs0_enable_initial)
  279. writel(0x00008020, &mmdc0->mdscr);
  280. if (cs1_enable_initial)
  281. writel(0x00008028, &mmdc0->mdscr);
  282. /* poll to make sure the con_ack bit was asserted */
  283. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  284. /*
  285. * Check MDMISC register CALIB_PER_CS to see which CS calibration
  286. * is targeted to (under normal cases, it should be cleared
  287. * as this is the default value, indicating calibration is directed
  288. * to CS0).
  289. * Disable the other chip select not being target for calibration
  290. * to avoid any potential issues. This will get re-enabled at end
  291. * of calibration.
  292. */
  293. if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
  294. clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
  295. else
  296. clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
  297. /*
  298. * Check to see which chip selects are now enabled for
  299. * the remainder of the calibration.
  300. */
  301. cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
  302. cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
  303. precharge_all(cs0_enable, cs1_enable);
  304. /* Write the pre-defined value into MPPDCMPR1 */
  305. writel(pddword, &mmdc0->mppdcmpr1);
  306. /*
  307. * Issue a write access to the external DDR device by setting
  308. * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
  309. * this bit until it clears to indicate completion of the write access.
  310. */
  311. setbits_le32(&mmdc0->mpswdar0, 1);
  312. wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
  313. /* Set the RD_DL_ABS# bits to their default values
  314. * (will be calibrated later in the read delay-line calibration).
  315. * Both PHYs for x64 configuration, if x32, do only PHY0.
  316. */
  317. writel(initdelay, &mmdc0->mprddlctl);
  318. if (sysinfo->dsize == 0x2)
  319. writel(initdelay, &mmdc1->mprddlctl);
  320. /* Force a measurment, for previous delay setup to take effect. */
  321. force_delay_measurement(sysinfo->dsize);
  322. /*
  323. * ***************************
  324. * Read DQS Gating calibration
  325. * ***************************
  326. */
  327. debug("Starting Read DQS Gating calibration.\n");
  328. /*
  329. * Reset the read data FIFOs (two resets); only need to issue reset
  330. * to PHY0 since in x64 mode, the reset will also go to PHY1.
  331. */
  332. reset_read_data_fifos();
  333. /*
  334. * Start the automatic read DQS gating calibration process by
  335. * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
  336. * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
  337. * to indicate completion.
  338. * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
  339. * no errors were seen during calibration.
  340. */
  341. /*
  342. * Set bit 30: chooses option to wait 32 cycles instead of
  343. * 16 before comparing read data.
  344. */
  345. setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  346. if (sysinfo->dsize == 2)
  347. setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  348. /* Set bit 28 to start automatic read DQS gating calibration */
  349. setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
  350. /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
  351. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
  352. /*
  353. * Check to see if any errors were encountered during calibration
  354. * (check MPDGCTRL0[HW_DG_ERR]).
  355. * Check both PHYs for x64 configuration, if x32, check only PHY0.
  356. */
  357. if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
  358. errors |= 1;
  359. if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
  360. errors |= 2;
  361. /* now disable mpdgctrl0[DG_CMP_CYC] */
  362. clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  363. if (sysinfo->dsize == 2)
  364. clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  365. /*
  366. * DQS gating absolute offset should be modified from
  367. * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
  368. * reflecting (HW_DG_UPx - 0x80)
  369. */
  370. modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
  371. &mmdc0->mpdgctrl0);
  372. modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
  373. &mmdc0->mpdgctrl1);
  374. if (sysinfo->dsize == 0x2) {
  375. modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
  376. &mmdc1->mpdgctrl0);
  377. modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
  378. &mmdc1->mpdgctrl1);
  379. }
  380. debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
  381. /*
  382. * **********************
  383. * Read Delay calibration
  384. * **********************
  385. */
  386. debug("Starting Read Delay calibration.\n");
  387. reset_read_data_fifos();
  388. /*
  389. * 4. Issue the Precharge-All command to the DDR device for both
  390. * chip selects. If only using one chip select, then precharge
  391. * only the desired chip select.
  392. */
  393. precharge_all(cs0_enable, cs1_enable);
  394. /*
  395. * 9. Read delay-line calibration
  396. * Start the automatic read calibration process by asserting
  397. * MPRDDLHWCTL[HW_RD_DL_EN].
  398. */
  399. writel(0x00000030, &mmdc0->mprddlhwctl);
  400. /*
  401. * 10. poll for completion
  402. * MMDC indicates that the write data calibration had finished by
  403. * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
  404. * no error bits were set.
  405. */
  406. wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
  407. /* check both PHYs for x64 configuration, if x32, check only PHY0 */
  408. if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
  409. errors |= 4;
  410. if ((sysinfo->dsize == 0x2) &&
  411. (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
  412. errors |= 8;
  413. debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
  414. /*
  415. * ***********************
  416. * Write Delay Calibration
  417. * ***********************
  418. */
  419. debug("Starting Write Delay calibration.\n");
  420. reset_read_data_fifos();
  421. /*
  422. * 4. Issue the Precharge-All command to the DDR device for both
  423. * chip selects. If only using one chip select, then precharge
  424. * only the desired chip select.
  425. */
  426. precharge_all(cs0_enable, cs1_enable);
  427. /*
  428. * 8. Set the WR_DL_ABS# bits to their default values.
  429. * Both PHYs for x64 configuration, if x32, do only PHY0.
  430. */
  431. writel(initdelay, &mmdc0->mpwrdlctl);
  432. if (sysinfo->dsize == 0x2)
  433. writel(initdelay, &mmdc1->mpwrdlctl);
  434. /*
  435. * XXX This isn't in the manual. Force a measurement,
  436. * for previous delay setup to effect.
  437. */
  438. force_delay_measurement(sysinfo->dsize);
  439. /*
  440. * 9. 10. Start the automatic write calibration process
  441. * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
  442. */
  443. writel(0x00000030, &mmdc0->mpwrdlhwctl);
  444. /*
  445. * Poll for completion.
  446. * MMDC indicates that the write data calibration had finished
  447. * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
  448. * Also, ensure that no error bits were set.
  449. */
  450. wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
  451. /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
  452. if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
  453. errors |= 16;
  454. if ((sysinfo->dsize == 0x2) &&
  455. (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
  456. errors |= 32;
  457. debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
  458. reset_read_data_fifos();
  459. /* Enable DDR logic power down timer */
  460. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  461. /* Enable Adopt power down timer */
  462. clrbits_le32(&mmdc0->mapsr, 0x1);
  463. /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
  464. writel(esdmisc_val, &mmdc0->mdmisc);
  465. /* Clear DQS pull ups */
  466. mmdc_set_sdqs(false);
  467. /* Re-enable SDE (chip selects) if they were set initially */
  468. if (cs1_enable_initial)
  469. /* Set SDE_1 */
  470. setbits_le32(&mmdc0->mdctl, 1 << 30);
  471. if (cs0_enable_initial)
  472. /* Set SDE_0 */
  473. setbits_le32(&mmdc0->mdctl, 1 << 31);
  474. /* Re-enable to auto refresh */
  475. writel(temp_ref, &mmdc0->mdref);
  476. /* Clear the MDSCR (including the con_req bit) */
  477. writel(0x0, &mmdc0->mdscr); /* CS0 */
  478. /* Poll to make sure the con_ack bit is clear */
  479. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
  480. /*
  481. * Print out the registers that were updated as a result
  482. * of the calibration process.
  483. */
  484. debug("MMDC registers updated from calibration\n");
  485. debug("Read DQS gating calibration:\n");
  486. debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
  487. debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
  488. if (sysinfo->dsize == 2) {
  489. debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
  490. debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
  491. }
  492. debug("Read calibration:\n");
  493. debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
  494. if (sysinfo->dsize == 2)
  495. debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
  496. debug("Write calibration:\n");
  497. debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
  498. if (sysinfo->dsize == 2)
  499. debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
  500. /*
  501. * Registers below are for debugging purposes. These print out
  502. * the upper and lower boundaries captured during
  503. * read DQS gating calibration.
  504. */
  505. debug("Status registers bounds for read DQS gating:\n");
  506. debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
  507. debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
  508. debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
  509. debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
  510. if (sysinfo->dsize == 2) {
  511. debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
  512. debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
  513. debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
  514. debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
  515. }
  516. debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
  517. return errors;
  518. }
  519. #endif
  520. #if defined(CONFIG_MX6SX)
  521. /* Configure MX6SX mmdc iomux */
  522. void mx6sx_dram_iocfg(unsigned width,
  523. const struct mx6sx_iomux_ddr_regs *ddr,
  524. const struct mx6sx_iomux_grp_regs *grp)
  525. {
  526. struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  527. struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  528. mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  529. mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  530. /* DDR IO TYPE */
  531. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  532. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  533. /* CLOCK */
  534. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  535. /* ADDRESS */
  536. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  537. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  538. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  539. /* Control */
  540. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  541. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  542. writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  543. writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  544. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  545. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  546. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  547. /* Data Strobes */
  548. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  549. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  550. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  551. if (width >= 32) {
  552. writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  553. writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  554. }
  555. /* Data */
  556. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  557. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  558. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  559. if (width >= 32) {
  560. writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  561. writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  562. }
  563. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  564. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  565. if (width >= 32) {
  566. writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  567. writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  568. }
  569. }
  570. #endif
  571. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  572. void mx6ul_dram_iocfg(unsigned width,
  573. const struct mx6ul_iomux_ddr_regs *ddr,
  574. const struct mx6ul_iomux_grp_regs *grp)
  575. {
  576. struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
  577. struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
  578. mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  579. mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
  580. /* DDR IO TYPE */
  581. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  582. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  583. /* CLOCK */
  584. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  585. /* ADDRESS */
  586. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  587. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  588. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  589. /* Control */
  590. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  591. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  592. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  593. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  594. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  595. /* Data Strobes */
  596. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  597. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  598. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  599. /* Data */
  600. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  601. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  602. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  603. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  604. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  605. }
  606. #endif
  607. #if defined(CONFIG_MX6SL)
  608. void mx6sl_dram_iocfg(unsigned width,
  609. const struct mx6sl_iomux_ddr_regs *ddr,
  610. const struct mx6sl_iomux_grp_regs *grp)
  611. {
  612. struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
  613. struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
  614. mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
  615. mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
  616. /* DDR IO TYPE */
  617. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  618. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  619. /* CLOCK */
  620. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  621. /* ADDRESS */
  622. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  623. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  624. mx6_grp_iomux->grp_addds = grp->grp_addds;
  625. /* Control */
  626. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  627. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  628. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  629. /* Data Strobes */
  630. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  631. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  632. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  633. if (width >= 32) {
  634. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  635. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  636. }
  637. /* Data */
  638. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  639. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  640. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  641. if (width >= 32) {
  642. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  643. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  644. }
  645. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  646. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  647. if (width >= 32) {
  648. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  649. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  650. }
  651. }
  652. #endif
  653. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
  654. /* Configure MX6DQ mmdc iomux */
  655. void mx6dq_dram_iocfg(unsigned width,
  656. const struct mx6dq_iomux_ddr_regs *ddr,
  657. const struct mx6dq_iomux_grp_regs *grp)
  658. {
  659. volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
  660. volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
  661. mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  662. mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
  663. /* DDR IO Type */
  664. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  665. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  666. /* Clock */
  667. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  668. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  669. /* Address */
  670. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  671. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  672. mx6_grp_iomux->grp_addds = grp->grp_addds;
  673. /* Control */
  674. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  675. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  676. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  677. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  678. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  679. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  680. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  681. /* Data Strobes */
  682. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  683. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  684. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  685. if (width >= 32) {
  686. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  687. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  688. }
  689. if (width >= 64) {
  690. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  691. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  692. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  693. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  694. }
  695. /* Data */
  696. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  697. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  698. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  699. if (width >= 32) {
  700. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  701. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  702. }
  703. if (width >= 64) {
  704. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  705. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  706. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  707. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  708. }
  709. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  710. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  711. if (width >= 32) {
  712. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  713. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  714. }
  715. if (width >= 64) {
  716. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  717. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  718. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  719. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  720. }
  721. }
  722. #endif
  723. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  724. /* Configure MX6SDL mmdc iomux */
  725. void mx6sdl_dram_iocfg(unsigned width,
  726. const struct mx6sdl_iomux_ddr_regs *ddr,
  727. const struct mx6sdl_iomux_grp_regs *grp)
  728. {
  729. volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
  730. volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
  731. mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  732. mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
  733. /* DDR IO Type */
  734. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  735. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  736. /* Clock */
  737. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  738. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  739. /* Address */
  740. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  741. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  742. mx6_grp_iomux->grp_addds = grp->grp_addds;
  743. /* Control */
  744. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  745. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  746. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  747. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  748. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  749. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  750. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  751. /* Data Strobes */
  752. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  753. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  754. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  755. if (width >= 32) {
  756. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  757. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  758. }
  759. if (width >= 64) {
  760. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  761. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  762. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  763. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  764. }
  765. /* Data */
  766. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  767. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  768. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  769. if (width >= 32) {
  770. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  771. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  772. }
  773. if (width >= 64) {
  774. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  775. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  776. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  777. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  778. }
  779. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  780. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  781. if (width >= 32) {
  782. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  783. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  784. }
  785. if (width >= 64) {
  786. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  787. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  788. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  789. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  790. }
  791. }
  792. #endif
  793. /*
  794. * Configure mx6 mmdc registers based on:
  795. * - board-specific memory configuration
  796. * - board-specific calibration data
  797. * - ddr3/lpddr2 chip details
  798. *
  799. * The various calculations here are derived from the Freescale
  800. * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
  801. * MMDC configuration registers based on memory system and memory chip
  802. * parameters.
  803. *
  804. * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
  805. * configuration registers based on memory system and memory chip
  806. * parameters.
  807. *
  808. * The defaults here are those which were specified in the spreadsheet.
  809. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
  810. * and/or IMX6SLRM section titled MMDC initialization.
  811. */
  812. #define MR(val, ba, cmd, cs1) \
  813. ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
  814. #define MMDC1(entry, value) do { \
  815. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
  816. mmdc1->entry = value; \
  817. } while (0)
  818. /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
  819. #define BOOT_CFG3_DDR_MASK 0x30
  820. #define BOOT_CFG3_EXT_DDR_MASK 0x33
  821. #define DDR_MMAP_NOC_SINGLE 0
  822. #define DDR_MMAP_NOC_DUAL 0x31
  823. /* NoC ACTIVATE shifts */
  824. #define NOC_RD_SHIFT 0
  825. #define NOC_FAW_PERIOD_SHIFT 4
  826. #define NOC_FAW_BANKS_SHIFT 10
  827. /* NoC DdrTiming shifts */
  828. #define NOC_ACT_TO_ACT_SHIFT 0
  829. #define NOC_RD_TO_MISS_SHIFT 6
  830. #define NOC_WR_TO_MISS_SHIFT 12
  831. #define NOC_BURST_LEN_SHIFT 18
  832. #define NOC_RD_TO_WR_SHIFT 21
  833. #define NOC_WR_TO_RD_SHIFT 26
  834. #define NOC_BW_RATIO_SHIFT 31
  835. /*
  836. * According JESD209-2B-LPDDR2: Table 103
  837. * WL: write latency
  838. */
  839. static int lpddr2_wl(uint32_t mem_speed)
  840. {
  841. switch (mem_speed) {
  842. case 1066:
  843. case 933:
  844. return 4;
  845. case 800:
  846. return 3;
  847. case 677:
  848. case 533:
  849. return 2;
  850. case 400:
  851. case 333:
  852. return 1;
  853. default:
  854. puts("invalid memory speed\n");
  855. hang();
  856. }
  857. return 0;
  858. }
  859. /*
  860. * According JESD209-2B-LPDDR2: Table 103
  861. * RL: read latency
  862. */
  863. static int lpddr2_rl(uint32_t mem_speed)
  864. {
  865. switch (mem_speed) {
  866. case 1066:
  867. return 8;
  868. case 933:
  869. return 7;
  870. case 800:
  871. return 6;
  872. case 677:
  873. return 5;
  874. case 533:
  875. return 4;
  876. case 400:
  877. case 333:
  878. return 3;
  879. default:
  880. puts("invalid memory speed\n");
  881. hang();
  882. }
  883. return 0;
  884. }
  885. void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  886. const struct mx6_mmdc_calibration *calib,
  887. const struct mx6_lpddr2_cfg *lpddr2_cfg)
  888. {
  889. volatile struct mmdc_p_regs *mmdc0;
  890. u32 val;
  891. u8 tcke, tcksrx, tcksre, trrd;
  892. u8 twl, txp, tfaw, tcl;
  893. u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
  894. u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
  895. u16 cs0_end;
  896. u8 coladdr;
  897. int clkper; /* clock period in picoseconds */
  898. int clock; /* clock freq in mHz */
  899. int cs;
  900. /* only support 16/32 bits */
  901. if (sysinfo->dsize > 1)
  902. hang();
  903. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  904. clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
  905. clkper = (1000 * 1000) / clock; /* pico seconds */
  906. twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
  907. /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
  908. switch (lpddr2_cfg->density) {
  909. case 1:
  910. case 2:
  911. case 4:
  912. trfc = DIV_ROUND_UP(130000, clkper) - 1;
  913. txsr = DIV_ROUND_UP(140000, clkper) - 1;
  914. break;
  915. case 8:
  916. trfc = DIV_ROUND_UP(210000, clkper) - 1;
  917. txsr = DIV_ROUND_UP(220000, clkper) - 1;
  918. break;
  919. default:
  920. /*
  921. * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
  922. */
  923. hang();
  924. break;
  925. }
  926. /*
  927. * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
  928. * set them to 0. */
  929. txp = DIV_ROUND_UP(7500, clkper) - 1;
  930. tcke = 3;
  931. if (lpddr2_cfg->mem_speed == 333)
  932. tfaw = DIV_ROUND_UP(60000, clkper) - 1;
  933. else
  934. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  935. trrd = DIV_ROUND_UP(10000, clkper) - 1;
  936. /* tckesr for LPDDR2 */
  937. tcksre = DIV_ROUND_UP(15000, clkper);
  938. tcksrx = tcksre;
  939. twr = DIV_ROUND_UP(15000, clkper) - 1;
  940. /*
  941. * tMRR: 2, tMRW: 5
  942. * tMRD should be set to max(tMRR, tMRW)
  943. */
  944. tmrd = 5;
  945. tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
  946. /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
  947. trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
  948. trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
  949. clkper / 10) - 1;
  950. trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
  951. trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
  952. /* To LPDDR2, CL in MDCFG0 refers to RL */
  953. tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
  954. twtr = DIV_ROUND_UP(7500, clkper) - 1;
  955. trtp = DIV_ROUND_UP(7500, clkper) - 1;
  956. cs0_end = 4 * sysinfo->cs_density - 1;
  957. debug("density:%d Gb (%d Gb per chip)\n",
  958. sysinfo->cs_density, lpddr2_cfg->density);
  959. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  960. debug("memspd:%d\n", lpddr2_cfg->mem_speed);
  961. debug("trcd_lp=%d\n", trcd_lp);
  962. debug("trppb_lp=%d\n", trppb_lp);
  963. debug("trpab_lp=%d\n", trpab_lp);
  964. debug("trc_lp=%d\n", trc_lp);
  965. debug("tcke=%d\n", tcke);
  966. debug("tcksrx=%d\n", tcksrx);
  967. debug("tcksre=%d\n", tcksre);
  968. debug("trfc=%d\n", trfc);
  969. debug("txsr=%d\n", txsr);
  970. debug("txp=%d\n", txp);
  971. debug("tfaw=%d\n", tfaw);
  972. debug("tcl=%d\n", tcl);
  973. debug("tras=%d\n", tras);
  974. debug("twr=%d\n", twr);
  975. debug("tmrd=%d\n", tmrd);
  976. debug("twl=%d\n", twl);
  977. debug("trtp=%d\n", trtp);
  978. debug("twtr=%d\n", twtr);
  979. debug("trrd=%d\n", trrd);
  980. debug("cs0_end=%d\n", cs0_end);
  981. debug("ncs=%d\n", sysinfo->ncs);
  982. /*
  983. * board-specific configuration:
  984. * These values are determined empirically and vary per board layout
  985. */
  986. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  987. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  988. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  989. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  990. mmdc0->mprddlctl = calib->p0_mprddlctl;
  991. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  992. mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
  993. /* Read data DQ Byte0-3 delay */
  994. mmdc0->mprddqby0dl = 0x33333333;
  995. mmdc0->mprddqby1dl = 0x33333333;
  996. if (sysinfo->dsize > 0) {
  997. mmdc0->mprddqby2dl = 0x33333333;
  998. mmdc0->mprddqby3dl = 0x33333333;
  999. }
  1000. /* Write data DQ Byte0-3 delay */
  1001. mmdc0->mpwrdqby0dl = 0xf3333333;
  1002. mmdc0->mpwrdqby1dl = 0xf3333333;
  1003. if (sysinfo->dsize > 0) {
  1004. mmdc0->mpwrdqby2dl = 0xf3333333;
  1005. mmdc0->mpwrdqby3dl = 0xf3333333;
  1006. }
  1007. /*
  1008. * In LPDDR2 mode this register should be cleared,
  1009. * so no termination will be activated.
  1010. */
  1011. mmdc0->mpodtctrl = 0;
  1012. /* complete calibration */
  1013. val = (1 << 11); /* Force measurement on delay-lines */
  1014. mmdc0->mpmur0 = val;
  1015. /* Step 1: configuration request */
  1016. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1017. /* Step 2: Timing configuration */
  1018. mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
  1019. (tfaw << 4) | tcl;
  1020. mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
  1021. mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
  1022. mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
  1023. (trppb_lp << 4) | trpab_lp;
  1024. mmdc0->mdotc = 0;
  1025. mmdc0->mdasp = cs0_end; /* CS addressing */
  1026. /* Step 3: Configure DDR type */
  1027. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1028. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1029. (sysinfo->ralat << 6) | (1 << 3);
  1030. /* Step 4: Configure delay while leaving reset */
  1031. mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
  1032. (sysinfo->rst_to_cke << 0);
  1033. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1034. coladdr = lpddr2_cfg->coladdr;
  1035. if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1036. coladdr += 4;
  1037. else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1038. coladdr += 1;
  1039. mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
  1040. (coladdr - 9) << 20 | /* COL */
  1041. (0 << 19) | /* Burst Length = 4 for LPDDR2 */
  1042. (sysinfo->dsize << 16); /* DDR data bus size */
  1043. /* Step 6: Perform ZQ calibration */
  1044. val = 0xa1390003; /* one-time HW ZQ calib */
  1045. mmdc0->mpzqhwctrl = val;
  1046. /* Step 7: Enable MMDC with desired chip select */
  1047. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1048. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1049. /* Step 8: Write Mode Registers to Init LPDDR2 devices */
  1050. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1051. /* MR63: reset */
  1052. mmdc0->mdscr = MR(63, 0, 3, cs);
  1053. /* MR10: calibration,
  1054. * 0xff is calibration command after intilization.
  1055. */
  1056. val = 0xA | (0xff << 8);
  1057. mmdc0->mdscr = MR(val, 0, 3, cs);
  1058. /* MR1 */
  1059. val = 0x1 | (0x82 << 8);
  1060. mmdc0->mdscr = MR(val, 0, 3, cs);
  1061. /* MR2 */
  1062. val = 0x2 | (0x04 << 8);
  1063. mmdc0->mdscr = MR(val, 0, 3, cs);
  1064. /* MR3 */
  1065. val = 0x3 | (0x02 << 8);
  1066. mmdc0->mdscr = MR(val, 0, 3, cs);
  1067. }
  1068. /* Step 10: Power down control and self-refresh */
  1069. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1070. 5 << 12 | /* PWDT_1: 256 cycles */
  1071. 5 << 8 | /* PWDT_0: 256 cycles */
  1072. 1 << 6 | /* BOTH_CS_PD */
  1073. (tcksrx & 0x7) << 3 |
  1074. (tcksre & 0x7);
  1075. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1076. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1077. val = 0xa1310003;
  1078. mmdc0->mpzqhwctrl = val;
  1079. /* Step 12: Configure and activate periodic refresh */
  1080. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1081. /* Step 13: Deassert config request - init complete */
  1082. mmdc0->mdscr = 0x00000000;
  1083. /* wait for auto-ZQ calibration to complete */
  1084. mdelay(1);
  1085. }
  1086. void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1087. const struct mx6_mmdc_calibration *calib,
  1088. const struct mx6_ddr3_cfg *ddr3_cfg)
  1089. {
  1090. volatile struct mmdc_p_regs *mmdc0;
  1091. volatile struct mmdc_p_regs *mmdc1;
  1092. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  1093. u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
  1094. u32 val;
  1095. u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
  1096. u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
  1097. u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
  1098. u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
  1099. u16 cs0_end;
  1100. u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  1101. u8 coladdr;
  1102. int clkper; /* clock period in picoseconds */
  1103. int clock; /* clock freq in MHz */
  1104. int cs;
  1105. u16 mem_speed = ddr3_cfg->mem_speed;
  1106. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1107. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
  1108. mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1109. /* Limit mem_speed for MX6D/MX6Q */
  1110. if (is_mx6dq() || is_mx6dqp()) {
  1111. if (mem_speed > 1066)
  1112. mem_speed = 1066; /* 1066 MT/s */
  1113. tcwl = 4;
  1114. }
  1115. /* Limit mem_speed for MX6S/MX6DL */
  1116. else {
  1117. if (mem_speed > 800)
  1118. mem_speed = 800; /* 800 MT/s */
  1119. tcwl = 3;
  1120. }
  1121. clock = mem_speed / 2;
  1122. /*
  1123. * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
  1124. * up to 528 MHz, so reduce the clock to fit chip specs
  1125. */
  1126. if (is_mx6dq() || is_mx6dqp()) {
  1127. if (clock > 528)
  1128. clock = 528; /* 528 MHz */
  1129. }
  1130. clkper = (1000 * 1000) / clock; /* pico seconds */
  1131. todtlon = tcwl;
  1132. taxpd = tcwl;
  1133. tanpd = tcwl;
  1134. switch (ddr3_cfg->density) {
  1135. case 1: /* 1Gb per chip */
  1136. trfc = DIV_ROUND_UP(110000, clkper) - 1;
  1137. txs = DIV_ROUND_UP(120000, clkper) - 1;
  1138. break;
  1139. case 2: /* 2Gb per chip */
  1140. trfc = DIV_ROUND_UP(160000, clkper) - 1;
  1141. txs = DIV_ROUND_UP(170000, clkper) - 1;
  1142. break;
  1143. case 4: /* 4Gb per chip */
  1144. trfc = DIV_ROUND_UP(260000, clkper) - 1;
  1145. txs = DIV_ROUND_UP(270000, clkper) - 1;
  1146. break;
  1147. case 8: /* 8Gb per chip */
  1148. trfc = DIV_ROUND_UP(350000, clkper) - 1;
  1149. txs = DIV_ROUND_UP(360000, clkper) - 1;
  1150. break;
  1151. default:
  1152. /* invalid density */
  1153. puts("invalid chip density\n");
  1154. hang();
  1155. break;
  1156. }
  1157. txpr = txs;
  1158. switch (mem_speed) {
  1159. case 800:
  1160. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1161. tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1162. if (ddr3_cfg->pagesz == 1) {
  1163. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  1164. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1165. } else {
  1166. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1167. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1168. }
  1169. break;
  1170. case 1066:
  1171. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1172. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  1173. if (ddr3_cfg->pagesz == 1) {
  1174. tfaw = DIV_ROUND_UP(37500, clkper) - 1;
  1175. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  1176. } else {
  1177. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1178. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1179. }
  1180. break;
  1181. default:
  1182. puts("invalid memory speed\n");
  1183. hang();
  1184. break;
  1185. }
  1186. txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
  1187. tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
  1188. taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  1189. tcksrx = tcksre;
  1190. taofpd = taonpd;
  1191. twr = DIV_ROUND_UP(15000, clkper) - 1;
  1192. tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
  1193. trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  1194. tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  1195. tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  1196. trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  1197. twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
  1198. trcd = trp;
  1199. trtp = twtr;
  1200. cs0_end = 4 * sysinfo->cs_density - 1;
  1201. debug("density:%d Gb (%d Gb per chip)\n",
  1202. sysinfo->cs_density, ddr3_cfg->density);
  1203. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  1204. debug("memspd:%d\n", mem_speed);
  1205. debug("tcke=%d\n", tcke);
  1206. debug("tcksrx=%d\n", tcksrx);
  1207. debug("tcksre=%d\n", tcksre);
  1208. debug("taofpd=%d\n", taofpd);
  1209. debug("taonpd=%d\n", taonpd);
  1210. debug("todtlon=%d\n", todtlon);
  1211. debug("tanpd=%d\n", tanpd);
  1212. debug("taxpd=%d\n", taxpd);
  1213. debug("trfc=%d\n", trfc);
  1214. debug("txs=%d\n", txs);
  1215. debug("txp=%d\n", txp);
  1216. debug("txpdll=%d\n", txpdll);
  1217. debug("tfaw=%d\n", tfaw);
  1218. debug("tcl=%d\n", tcl);
  1219. debug("trcd=%d\n", trcd);
  1220. debug("trp=%d\n", trp);
  1221. debug("trc=%d\n", trc);
  1222. debug("tras=%d\n", tras);
  1223. debug("twr=%d\n", twr);
  1224. debug("tmrd=%d\n", tmrd);
  1225. debug("tcwl=%d\n", tcwl);
  1226. debug("tdllk=%d\n", tdllk);
  1227. debug("trtp=%d\n", trtp);
  1228. debug("twtr=%d\n", twtr);
  1229. debug("trrd=%d\n", trrd);
  1230. debug("txpr=%d\n", txpr);
  1231. debug("cs0_end=%d\n", cs0_end);
  1232. debug("ncs=%d\n", sysinfo->ncs);
  1233. debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  1234. debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  1235. debug("SRT=%d\n", ddr3_cfg->SRT);
  1236. debug("twr=%d\n", twr);
  1237. /*
  1238. * board-specific configuration:
  1239. * These values are determined empirically and vary per board layout
  1240. * see:
  1241. * appnote, ddr3 spreadsheet
  1242. */
  1243. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  1244. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  1245. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  1246. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  1247. mmdc0->mprddlctl = calib->p0_mprddlctl;
  1248. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  1249. if (sysinfo->dsize > 1) {
  1250. MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
  1251. MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
  1252. MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
  1253. MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
  1254. MMDC1(mprddlctl, calib->p1_mprddlctl);
  1255. MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
  1256. }
  1257. /* Read data DQ Byte0-3 delay */
  1258. mmdc0->mprddqby0dl = 0x33333333;
  1259. mmdc0->mprddqby1dl = 0x33333333;
  1260. if (sysinfo->dsize > 0) {
  1261. mmdc0->mprddqby2dl = 0x33333333;
  1262. mmdc0->mprddqby3dl = 0x33333333;
  1263. }
  1264. if (sysinfo->dsize > 1) {
  1265. MMDC1(mprddqby0dl, 0x33333333);
  1266. MMDC1(mprddqby1dl, 0x33333333);
  1267. MMDC1(mprddqby2dl, 0x33333333);
  1268. MMDC1(mprddqby3dl, 0x33333333);
  1269. }
  1270. /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
  1271. val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  1272. mmdc0->mpodtctrl = val;
  1273. if (sysinfo->dsize > 1)
  1274. MMDC1(mpodtctrl, val);
  1275. /* complete calibration */
  1276. val = (1 << 11); /* Force measurement on delay-lines */
  1277. mmdc0->mpmur0 = val;
  1278. if (sysinfo->dsize > 1)
  1279. MMDC1(mpmur0, val);
  1280. /* Step 1: configuration request */
  1281. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1282. /* Step 2: Timing configuration */
  1283. mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  1284. (txpdll << 9) | (tfaw << 4) | tcl;
  1285. mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  1286. (tras << 16) | (1 << 15) /* trpa */ |
  1287. (twr << 9) | (tmrd << 5) | tcwl;
  1288. mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  1289. mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  1290. (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  1291. mmdc0->mdasp = cs0_end; /* CS addressing */
  1292. /* Step 3: Configure DDR type */
  1293. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1294. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1295. (sysinfo->ralat << 6);
  1296. /* Step 4: Configure delay while leaving reset */
  1297. mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  1298. (sysinfo->rst_to_cke << 0);
  1299. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1300. coladdr = ddr3_cfg->coladdr;
  1301. if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1302. coladdr += 4;
  1303. else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1304. coladdr += 1;
  1305. mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  1306. (coladdr - 9) << 20 | /* COL */
  1307. (1 << 19) | /* Burst Length = 8 for DDR3 */
  1308. (sysinfo->dsize << 16); /* DDR data bus size */
  1309. /* Step 6: Perform ZQ calibration */
  1310. val = 0xa1390001; /* one-time HW ZQ calib */
  1311. mmdc0->mpzqhwctrl = val;
  1312. if (sysinfo->dsize > 1)
  1313. MMDC1(mpzqhwctrl, val);
  1314. /* Step 7: Enable MMDC with desired chip select */
  1315. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1316. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1317. /* Step 8: Write Mode Registers to Init DDR3 devices */
  1318. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1319. /* MR2 */
  1320. val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
  1321. ((tcwl - 3) & 3) << 3;
  1322. debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
  1323. mmdc0->mdscr = MR(val, 2, 3, cs);
  1324. /* MR3 */
  1325. debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
  1326. mmdc0->mdscr = MR(0, 3, 3, cs);
  1327. /* MR1 */
  1328. val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  1329. ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  1330. debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
  1331. mmdc0->mdscr = MR(val, 1, 3, cs);
  1332. /* MR0 */
  1333. val = ((tcl - 1) << 4) | /* CAS */
  1334. (1 << 8) | /* DLL Reset */
  1335. ((twr - 3) << 9) | /* Write Recovery */
  1336. (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
  1337. debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
  1338. mmdc0->mdscr = MR(val, 0, 3, cs);
  1339. /* ZQ calibration */
  1340. val = (1 << 10);
  1341. mmdc0->mdscr = MR(val, 0, 4, cs);
  1342. }
  1343. /* Step 10: Power down control and self-refresh */
  1344. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1345. 5 << 12 | /* PWDT_1: 256 cycles */
  1346. 5 << 8 | /* PWDT_0: 256 cycles */
  1347. 1 << 6 | /* BOTH_CS_PD */
  1348. (tcksrx & 0x7) << 3 |
  1349. (tcksre & 0x7);
  1350. if (!sysinfo->pd_fast_exit)
  1351. mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
  1352. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1353. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1354. val = 0xa1390003;
  1355. mmdc0->mpzqhwctrl = val;
  1356. if (sysinfo->dsize > 1)
  1357. MMDC1(mpzqhwctrl, val);
  1358. /* Step 12: Configure and activate periodic refresh */
  1359. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1360. /*
  1361. * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
  1362. * configure it and disable MMDC arbitration/reordering (see EB828)
  1363. */
  1364. if (is_mx6dqp() &&
  1365. ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
  1366. (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
  1367. struct mx6dqp_noc_sched_regs *noc_sched =
  1368. (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
  1369. /*
  1370. * These values are fixed based on integration parameters and
  1371. * should not be modified
  1372. */
  1373. noc_sched->rlat = 0x00000040;
  1374. noc_sched->ipu1 = 0x00000020;
  1375. noc_sched->ipu2 = 0x00000020;
  1376. noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
  1377. (tfaw << NOC_FAW_PERIOD_SHIFT) |
  1378. (trrd << NOC_RD_SHIFT);
  1379. noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
  1380. << NOC_BW_RATIO_SHIFT) |
  1381. ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
  1382. ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
  1383. (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
  1384. ((tcwl + twr + trp + trcd)
  1385. << NOC_WR_TO_MISS_SHIFT) |
  1386. ((trtp + trp + trcd - 4)
  1387. << NOC_RD_TO_MISS_SHIFT) |
  1388. (trc << NOC_ACT_TO_ACT_SHIFT);
  1389. if (sysinfo->dsize == 2) {
  1390. if (ddr3_cfg->coladdr == 10) {
  1391. if (ddr3_cfg->rowaddr == 15 &&
  1392. sysinfo->ncs == 2)
  1393. noc_sched->ddrconf = 4;
  1394. else
  1395. noc_sched->ddrconf = 0;
  1396. } else if (ddr3_cfg->coladdr == 11) {
  1397. noc_sched->ddrconf = 1;
  1398. }
  1399. } else {
  1400. if (ddr3_cfg->coladdr == 9) {
  1401. if (ddr3_cfg->rowaddr == 13)
  1402. noc_sched->ddrconf = 2;
  1403. else if (ddr3_cfg->rowaddr == 14)
  1404. noc_sched->ddrconf = 15;
  1405. } else if (ddr3_cfg->coladdr == 10) {
  1406. if (ddr3_cfg->rowaddr == 14 &&
  1407. sysinfo->ncs == 2)
  1408. noc_sched->ddrconf = 14;
  1409. else if (ddr3_cfg->rowaddr == 15 &&
  1410. sysinfo->ncs == 2)
  1411. noc_sched->ddrconf = 9;
  1412. else
  1413. noc_sched->ddrconf = 3;
  1414. } else if (ddr3_cfg->coladdr == 11) {
  1415. if (ddr3_cfg->rowaddr == 15 &&
  1416. sysinfo->ncs == 2)
  1417. noc_sched->ddrconf = 4;
  1418. else
  1419. noc_sched->ddrconf = 0;
  1420. } else if (ddr3_cfg->coladdr == 12) {
  1421. if (ddr3_cfg->rowaddr == 14)
  1422. noc_sched->ddrconf = 1;
  1423. }
  1424. }
  1425. /* Disable MMDC arbitration/reordering */
  1426. mmdc0->maarcr = 0x14420000;
  1427. }
  1428. /* Step 13: Deassert config request - init complete */
  1429. mmdc0->mdscr = 0x00000000;
  1430. /* wait for auto-ZQ calibration to complete */
  1431. mdelay(1);
  1432. }
  1433. void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
  1434. struct mx6_mmdc_calibration *calib)
  1435. {
  1436. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1437. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1438. calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
  1439. calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
  1440. calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
  1441. calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
  1442. calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
  1443. calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
  1444. if (sysinfo->dsize == 2) {
  1445. calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
  1446. calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
  1447. calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
  1448. calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
  1449. calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
  1450. calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
  1451. }
  1452. }
  1453. void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1454. const struct mx6_mmdc_calibration *calib,
  1455. const void *ddr_cfg)
  1456. {
  1457. if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
  1458. mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
  1459. } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
  1460. mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
  1461. } else {
  1462. puts("Unsupported ddr type\n");
  1463. hang();
  1464. }
  1465. }