chromebook_coral.dts 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/x86-gpio.h>
  4. /include/ "skeleton.dtsi"
  5. /include/ "keyboard.dtsi"
  6. /include/ "reset.dtsi"
  7. /include/ "rtc.dtsi"
  8. /include/ "tsc_timer.dtsi"
  9. #ifdef CONFIG_CHROMEOS
  10. #include "chromeos-x86.dtsi"
  11. #include "flashmap-x86-ro.dtsi"
  12. #include "flashmap-16mb-rw.dtsi"
  13. #endif
  14. #include <asm/intel_pinctrl_defs.h>
  15. #include <asm/arch-apollolake/cpu.h>
  16. #include <asm/arch-apollolake/gpio.h>
  17. #include <asm/arch-apollolake/iomap.h>
  18. #include <asm/arch-apollolake/pm.h>
  19. #include <dt-bindings/clock/intel-clock.h>
  20. / {
  21. model = "Google Coral";
  22. compatible = "google,coral", "intel,apollolake";
  23. aliases {
  24. cros-ec0 = &cros_ec;
  25. fsp = &fsp_s;
  26. spi0 = &spi;
  27. i2c0 = &i2c_0;
  28. i2c1 = &i2c_1;
  29. i2c2 = &i2c_2;
  30. i2c3 = &i2c_3;
  31. i2c4 = &i2c_4;
  32. i2c5 = &i2c_5;
  33. i2c6 = &i2c_6;
  34. i2c7 = &i2c_7;
  35. };
  36. config {
  37. silent_console = <0>;
  38. };
  39. chosen {
  40. stdout-path = &serial;
  41. };
  42. clk: clock {
  43. compatible = "intel,apl-clk";
  44. #clock-cells = <1>;
  45. };
  46. cpus {
  47. u-boot,dm-pre-reloc;
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. cpu@0 {
  51. u-boot,dm-pre-reloc;
  52. device_type = "cpu";
  53. compatible = "intel,apl-cpu";
  54. reg = <0>;
  55. intel,apic-id = <0>;
  56. };
  57. cpu@1 {
  58. device_type = "cpu";
  59. compatible = "intel,apl-cpu";
  60. reg = <1>;
  61. intel,apic-id = <2>;
  62. };
  63. cpu@2 {
  64. device_type = "cpu";
  65. compatible = "intel,apl-cpu";
  66. reg = <2>;
  67. intel,apic-id = <4>;
  68. };
  69. cpu@3 {
  70. device_type = "cpu";
  71. compatible = "intel,apl-cpu";
  72. reg = <3>;
  73. intel,apic-id = <6>;
  74. };
  75. };
  76. acpi_gpe: general-purpose-events {
  77. reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  78. compatible = "intel,acpi-gpe";
  79. interrupt-controller;
  80. #interrupt-cells = <2>;
  81. };
  82. keyboard {
  83. intel,duplicate-por;
  84. };
  85. pci {
  86. compatible = "pci-x86";
  87. #address-cells = <3>;
  88. #size-cells = <2>;
  89. u-boot,dm-pre-reloc;
  90. ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  91. 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
  92. 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
  93. u-boot,skip-auto-config-until-reloc;
  94. host_bridge: host-bridge@0,0 {
  95. u-boot,dm-pre-reloc;
  96. reg = <0x00000000 0 0 0 0>;
  97. compatible = "intel,apl-hostbridge";
  98. pciex-region-size = <0x10000000>;
  99. /*
  100. * Parameters used by the FSP-S binary blob. This is
  101. * really unfortunate since these parameters mostly
  102. * relate to drivers but we need them in one place. We
  103. * could put them in the driver nodes easily, but then
  104. * would have to scan each node to find them. So just
  105. * dump them here for now.
  106. */
  107. fsp_s: fsp-s {
  108. };
  109. };
  110. punit@0,1 {
  111. u-boot,dm-pre-reloc;
  112. reg = <0x00000800 0 0 0 0>;
  113. compatible = "intel,apl-punit";
  114. };
  115. p2sb: p2sb@d,0 {
  116. u-boot,dm-pre-reloc;
  117. reg = <0x02006810 0 0 0 0>;
  118. compatible = "intel,p2sb";
  119. early-regs = <IOMAP_P2SB_BAR 0x100000>;
  120. n {
  121. compatible = "intel,apl-pinctrl";
  122. u-boot,dm-pre-reloc;
  123. intel,p2sb-port-id = <PID_GPIO_N>;
  124. gpio_n: gpio-n {
  125. compatible = "intel,gpio";
  126. u-boot,dm-pre-reloc;
  127. gpio-controller;
  128. #gpio-cells = <2>;
  129. };
  130. };
  131. nw {
  132. u-boot,dm-pre-reloc;
  133. compatible = "intel,apl-pinctrl";
  134. intel,p2sb-port-id = <PID_GPIO_NW>;
  135. #gpio-cells = <2>;
  136. gpio_nw: gpio-nw {
  137. compatible = "intel,gpio";
  138. u-boot,dm-pre-reloc;
  139. gpio-controller;
  140. #gpio-cells = <2>;
  141. };
  142. };
  143. w {
  144. u-boot,dm-pre-reloc;
  145. compatible = "intel,apl-pinctrl";
  146. intel,p2sb-port-id = <PID_GPIO_W>;
  147. #gpio-cells = <2>;
  148. gpio_w: gpio-w {
  149. compatible = "intel,gpio";
  150. u-boot,dm-pre-reloc;
  151. gpio-controller;
  152. #gpio-cells = <2>;
  153. };
  154. };
  155. sw {
  156. u-boot,dm-pre-reloc;
  157. compatible = "intel,apl-pinctrl";
  158. intel,p2sb-port-id = <PID_GPIO_SW>;
  159. #gpio-cells = <2>;
  160. gpio_sw: gpio-sw {
  161. compatible = "intel,gpio";
  162. u-boot,dm-pre-reloc;
  163. gpio-controller;
  164. #gpio-cells = <2>;
  165. };
  166. };
  167. itss {
  168. u-boot,dm-pre-reloc;
  169. compatible = "intel,itss";
  170. intel,p2sb-port-id = <PID_ITSS>;
  171. intel,pmc-routes = <
  172. PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
  173. PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
  174. PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
  175. PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
  176. PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
  177. PMC_GPE_N_31_0 GPIO_GPE_N_31_0
  178. PMC_GPE_N_63_32 GPIO_GPE_N_63_32
  179. PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
  180. };
  181. };
  182. pmc@d,1 {
  183. u-boot,dm-pre-reloc;
  184. reg = <0x6900 0 0 0 0>;
  185. /*
  186. * Values for BAR0, BAR2 and ACPI_BASE for when PCI
  187. * auto-configure is not available
  188. */
  189. early-regs = <0xfe042000 0x2000
  190. 0xfe044000 0x2000
  191. IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  192. compatible = "intel,apl-pmc";
  193. gpe0-dwx-mask = <0xf>;
  194. gpe0-dwx-shift-base = <4>;
  195. /*
  196. * GPE configuration
  197. * Note that GPE events called out in ASL code rely on
  198. * this route, i.e., if this route changes then the
  199. * affected GPE * offset bits also need to be changed.
  200. * This sets the PMC register GPE_CFG fields.
  201. */
  202. gpe0-dw = <PMC_GPE_N_31_0
  203. PMC_GPE_N_63_32
  204. PMC_GPE_SW_31_0>;
  205. gpe0-sts = <0x20>;
  206. gpe0-en = <0x30>;
  207. };
  208. spi: fast-spi@d,2 {
  209. u-boot,dm-pre-reloc;
  210. reg = <0x02006a10 0 0 0 0>;
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. compatible = "intel,fast-spi";
  214. early-regs = <IOMAP_SPI_BASE 0x1000>;
  215. intel,hardware-seq = <1>;
  216. fwstore_spi: spi-flash@0 {
  217. #size-cells = <1>;
  218. #address-cells = <1>;
  219. u-boot,dm-pre-reloc;
  220. reg = <0>;
  221. compatible = "winbond,w25q128fw",
  222. "jedec,spi-nor";
  223. rw-mrc-cache {
  224. label = "rw-mrc-cache";
  225. reg = <0x008e0000 0x00010000>;
  226. u-boot,dm-pre-reloc;
  227. };
  228. rw-var-mrc-cache {
  229. label = "rw-mrc-cache";
  230. reg = <0x008f0000 0x0001000>;
  231. u-boot,dm-pre-reloc;
  232. };
  233. };
  234. };
  235. i2c_0: i2c2@16,0 {
  236. compatible = "intel,apl-i2c";
  237. reg = <0x0200b010 0 0 0 0>;
  238. clocks = <&clk CLK_I2C>;
  239. i2c-scl-rising-time-ns = <104>;
  240. i2c-scl-falling-time-ns = <52>;
  241. };
  242. i2c_1: i2c2@16,1 {
  243. compatible = "intel,apl-i2c";
  244. reg = <0x0200b110 0 0 0 0>;
  245. clocks = <&clk CLK_I2C>;
  246. status = "disabled";
  247. };
  248. i2c_2: i2c2@16,2 {
  249. compatible = "intel,apl-i2c";
  250. reg = <0x0200b210 0 0 0 0>;
  251. #address-cells = <1>;
  252. #size-cells = <0>;
  253. clock-frequency = <400000>;
  254. clocks = <&clk CLK_I2C>;
  255. i2c-scl-rising-time-ns = <57>;
  256. i2c-scl-falling-time-ns = <28>;
  257. tpm@50 {
  258. reg = <0x50>;
  259. compatible = "google,cr50";
  260. u-boot,i2c-offset-len = <0>;
  261. ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
  262. interrupts-extended = <&acpi_gpe 0x3c 0>;
  263. };
  264. };
  265. i2c_3: i2c2@16,3 {
  266. compatible = "intel,apl-i2c";
  267. reg = <0x0200b110 0 0 0 0>;
  268. clocks = <&clk CLK_I2C>;
  269. i2c-scl-rising-time-ns = <76>;
  270. i2c-scl-falling-time-ns = <164>;
  271. };
  272. i2c_4: i2c2@17,0 {
  273. compatible = "intel,apl-i2c";
  274. reg = <0x0200b110 0 0 0 0>;
  275. clocks = <&clk CLK_I2C>;
  276. i2c-sda-hold-time-ns = <350>;
  277. i2c-scl-rising-time-ns = <114>;
  278. i2c-scl-falling-time-ns = <164>;
  279. };
  280. i2c_5: i2c2@17,1 {
  281. compatible = "intel,apl-i2c";
  282. reg = <0x0200b110 0 0 0 0>;
  283. clocks = <&clk CLK_I2C>;
  284. i2c-scl-rising-time-ns = <76>;
  285. i2c-scl-falling-time-ns = <164>;
  286. };
  287. i2c_6: i2c2@17,2 {
  288. compatible = "intel,apl-i2c";
  289. reg = <0x0200b110 0 0 0 0>;
  290. clocks = <&clk CLK_I2C>;
  291. status = "disabled";
  292. };
  293. i2c_7: i2c2@17,3 {
  294. compatible = "intel,apl-i2c";
  295. reg = <0x0200b110 0 0 0 0>;
  296. clocks = <&clk CLK_I2C>;
  297. status = "disabled";
  298. };
  299. serial: serial@18,2 {
  300. reg = <0x0200c210 0 0 0 0>;
  301. u-boot,dm-pre-reloc;
  302. compatible = "intel,apl-ns16550";
  303. early-regs = <0xde000000 0x20>;
  304. reg-shift = <2>;
  305. clock-frequency = <1843200>;
  306. current-speed = <115200>;
  307. };
  308. pch: pch@1f,0 {
  309. reg = <0x0000f800 0 0 0 0>;
  310. compatible = "intel,apl-pch";
  311. u-boot,dm-pre-reloc;
  312. #address-cells = <1>;
  313. #size-cells = <1>;
  314. lpc {
  315. compatible = "intel,apl-lpc";
  316. #address-cells = <1>;
  317. #size-cells = <0>;
  318. u-boot,dm-pre-reloc;
  319. cros_ec: cros-ec {
  320. u-boot,dm-pre-reloc;
  321. compatible = "google,cros-ec-lpc";
  322. reg = <0x204 1 0x200 1 0x880 0x80>;
  323. /*
  324. * Describes the flash memory within
  325. * the EC
  326. */
  327. #address-cells = <1>;
  328. #size-cells = <1>;
  329. flash@8000000 {
  330. reg = <0x08000000 0x20000>;
  331. erase-value = <0xff>;
  332. };
  333. };
  334. };
  335. };
  336. };
  337. };
  338. &host_bridge {
  339. /*
  340. * PL1 override 12000 mW: the energy calculation is wrong with the
  341. * current VR solution. Experiments show that SoC TDP max (6W) can be
  342. * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
  343. */
  344. tdp-pl-override-mw = <12000 15000>;
  345. early-pads = <
  346. /* These two are for the debug UART */
  347. GPIO_46 /* UART2 RX */
  348. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  349. (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  350. GPIO_47 /* UART2 TX */
  351. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  352. (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  353. GPIO_75 /* I2S1_BCLK -- PCH_WP */
  354. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
  355. (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
  356. /* I2C2 - TPM */
  357. GPIO_128 /* LPSS_I2C2_SDA */
  358. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  359. (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  360. GPIO_129 /* LPSS_I2C2_SCL */
  361. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  362. (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  363. GPIO_28 /* TPM IRQ */
  364. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  365. PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
  366. PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
  367. (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
  368. /*
  369. * WLAN_PE_RST - default to deasserted just in case FSP
  370. * misbehaves
  371. */
  372. GPIO_122 /* SIO_SPI_2_RXD */
  373. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  374. PAD_CFG0_RX_DISABLE | 0)
  375. (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  376. /* LPC */
  377. PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  378. PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  379. PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  380. PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  381. PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  382. PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  383. PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  384. PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  385. PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  386. >;
  387. lpddr4-swizzle = /bits/ 8 <
  388. /* LP4_PHYS_CH0A */
  389. /* DQA[0:7] pins of LPDDR4 module */
  390. 6 7 5 4 3 1 0 2
  391. /* DQA[8:15] pins of LPDDR4 module */
  392. 12 10 11 13 14 8 9 15
  393. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  394. 16 22 23 20 18 17 19 21
  395. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  396. 30 28 29 25 24 26 27 31
  397. /* LP4_PHYS_CH0B */
  398. /* DQA[0:7] pins of LPDDR4 module */
  399. 7 3 5 2 6 0 1 4
  400. /* DQA[8:15] pins of LPDDR4 module */
  401. 9 14 12 13 10 11 8 15
  402. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  403. 20 22 23 16 19 17 18 21
  404. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  405. 28 24 26 27 29 30 31 25
  406. /* LP4_PHYS_CH1A */
  407. /* DQA[0:7] pins of LPDDR4 module */
  408. 2 1 6 7 5 4 3 0
  409. /* DQA[8:15] pins of LPDDR4 module */
  410. 11 10 8 9 12 15 13 14
  411. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  412. 17 23 19 16 21 22 20 18
  413. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  414. 31 29 26 25 28 27 24 30
  415. /* LP4_PHYS_CH1B */
  416. /* DQA[0:7] pins of LPDDR4 module */
  417. 4 3 7 5 6 1 0 2
  418. /* DQA[8:15] pins of LPDDR4 module */
  419. 15 9 8 11 14 13 12 10
  420. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  421. 20 23 22 21 18 19 16 17
  422. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  423. 25 28 30 31 26 27 24 29>;
  424. };
  425. &fsp_s {
  426. u-boot,dm-pre-proper;
  427. /* Disable unused clkreq of PCIe root ports */
  428. pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
  429. CLKREQ_DISABLED
  430. CLKREQ_DISABLED
  431. CLKREQ_DISABLED
  432. CLKREQ_DISABLED
  433. CLKREQ_DISABLED>;
  434. /*
  435. * GPIO for PERST_0
  436. * If the Board has PERST_0 signal, assign the GPIO
  437. * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
  438. *
  439. * This are not used yet, so comment them out for now.
  440. *
  441. * prt0-gpio = <GPIO_122>;
  442. *
  443. * GPIO for SD card detect
  444. * sdcard-cd-gpio = <GPIO_177>;
  445. */
  446. /*
  447. * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
  448. * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
  449. *
  450. * EMMC TX DATA Delay 1
  451. * Refer to EDS-Vol2-22.3
  452. * [14:8] steps of delay for HS400, each 125ps
  453. * [6:0] steps of delay for SDR104/HS200, each 125ps
  454. /*
  455. * EMMC TX DATA Delay 2
  456. * Refer to EDS-Vol2-22.3.
  457. * [30:24] steps of delay for SDR50, each 125ps
  458. * [22:16] steps of delay for DDR50, each 125ps
  459. * [14:8] steps of delay for SDR25/HS50, each 125ps
  460. * [6:0] steps of delay for SDR12, each 125ps
  461. */
  462. /*
  463. * EMMC RX CMD/DATA Delay 1
  464. * Refer to EDS-Vol2-22.3.
  465. * [30:24] steps of delay for SDR50, each 125ps
  466. * [22:16] steps of delay for DDR50, each 125ps
  467. * [14:8] steps of delay for SDR25/HS50, each 125ps
  468. * [6:0] steps of delay for SDR12, each 125ps
  469. */
  470. /*
  471. * EMMC RX CMD/DATA Delay 2
  472. * Refer to EDS-Vol2-22.3.
  473. * [17:16] stands for Rx Clock before Output Buffer
  474. * [14:8] steps of delay for Auto Tuning Mode, each 125ps
  475. * [6:0] steps of delay for HS200, each 125ps
  476. */
  477. emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
  478. /* Enable DPTF */
  479. dptf-enable;
  480. /* Enable Audio Clock and Power gating */
  481. hdaudio-clk-gate-enable;
  482. hdaudio-pwr-gate-enable;
  483. hdaudio-bios-config-lockdown;
  484. /* Enable lpss s0ix */
  485. lpss-s0ix-enable;
  486. /*
  487. * TODO(sjg@chromium.org): Move this to the I2C nodes
  488. * Intel Common SoC Config
  489. *+-------------------+---------------------------+
  490. *| Field | Value |
  491. *+-------------------+---------------------------+
  492. *| I2C0 | Audio |
  493. *| I2C2 | TPM |
  494. *| I2C3 | Touchscreen |
  495. *| I2C4 | Trackpad |
  496. *| I2C5 | Digitizer |
  497. *+-------------------+---------------------------+
  498. *
  499. common_soc_config" = "{
  500. .i2c[0] = {
  501. .speed = I2C_SPEED_FAST,
  502. .rise-time-ns = 104,
  503. .fall-time-ns = 52,
  504. },
  505. .i2c[2] = {
  506. .early_init = 1,
  507. .speed = I2C_SPEED_FAST,
  508. .rise-time-ns = 57,
  509. .fall-time-ns = 28,
  510. },
  511. .i2c[3] = {
  512. .speed = I2C_SPEED_FAST,
  513. .rise-time-ns = 76,
  514. .fall-time-ns = 164,
  515. },
  516. .i2c[4] = {
  517. .speed = I2C_SPEED_FAST,
  518. .rise-time-ns = 114,
  519. .fall-time-ns = 164,
  520. .data_hold_time_ns = 350,
  521. },
  522. .i2c[5] = {
  523. .speed = I2C_SPEED_FAST,
  524. .rise-time-ns = 152,
  525. .fall-time-ns = 30,
  526. },
  527. }"
  528. */
  529. /* Minimum SLP S3 assertion width 28ms */
  530. slp-s3-assertion-width-usecs = <28000>;
  531. pads = <
  532. /* PCIE_WAKE[0:3]_N */
  533. PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
  534. PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */
  535. PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */
  536. PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */
  537. /* EMMC interface */
  538. PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
  539. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
  540. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
  541. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
  542. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
  543. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
  544. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
  545. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
  546. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
  547. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
  548. PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
  549. /* SDIO -- unused */
  550. PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */
  551. PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */
  552. /* Configure SDIO to enable power gating */
  553. PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
  554. PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */
  555. PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */
  556. PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */
  557. /* SDCARD */
  558. /* Pull down clock by 20K */
  559. PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
  560. PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
  561. PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
  562. PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
  563. PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
  564. /* Card detect is active LOW with external pull up */
  565. PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
  566. PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
  567. /* CLK feedback, internal signal, needs 20K pull down */
  568. PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
  569. /* No h/w write proect for uSD cards, pull down by 20K */
  570. PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
  571. /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
  572. PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */
  573. /* SMBus -- unused */
  574. PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */
  575. PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */
  576. PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */
  577. /* LPC */
  578. PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  579. PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  580. PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  581. PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  582. PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  583. PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  584. PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  585. PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  586. PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  587. /* I2C0 - Audio */
  588. PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
  589. PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
  590. /* I2C1 - NFC with external pulls */
  591. PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
  592. PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
  593. /* I2C2 - TPM */
  594. PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
  595. PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
  596. /* I2C3 - touch */
  597. PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
  598. PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
  599. /* I2C4 - trackpad */
  600. /* LPSS_I2C4_SDA */
  601. PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
  602. /* LPSS_I2C4_SCL */
  603. PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
  604. /* I2C5 -- pen with external pulls */
  605. PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
  606. PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
  607. /* I2C6-7 -- unused */
  608. PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */
  609. PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */
  610. PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */
  611. PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */
  612. /* Audio Amp - I2S6 */
  613. PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
  614. PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
  615. PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */
  616. PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
  617. /* NFC Reset */
  618. PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */
  619. PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */
  620. /* Touch enable */
  621. PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */
  622. PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */
  623. PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */
  624. PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */
  625. /* PCIE_CLKREQ[0:3]_N */
  626. PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */
  627. PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */
  628. PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */
  629. PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */
  630. /* OSC_CLK_OUT_[0:4] -- unused */
  631. PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
  632. PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
  633. PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
  634. PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
  635. PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
  636. /* PMU Signals */
  637. PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
  638. PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
  639. PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
  640. PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
  641. PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
  642. PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
  643. PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
  644. PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
  645. PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
  646. PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */
  647. PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
  648. PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
  649. /* DDI[0:1] SDA and SCL -- unused */
  650. PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */
  651. PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */
  652. PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */
  653. PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */
  654. /* MIPI I2C -- unused */
  655. PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */
  656. PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */
  657. /* Panel 0 control */
  658. PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
  659. PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
  660. PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
  661. /* Panel 1 control -- unused */
  662. PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
  663. PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
  664. PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
  665. /* Hot plug detect */
  666. PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
  667. PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
  668. /* MDSI signals -- unused */
  669. PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */
  670. PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */
  671. /* USB overcurrent pins */
  672. PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
  673. PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
  674. /* PMC SPI -- almost entirely unused */
  675. PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
  676. PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
  677. PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
  678. PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
  679. PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
  680. PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
  681. /* PMIC Signals Unused signals related to an old PMIC interface */
  682. PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
  683. PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */
  684. PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */
  685. PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */
  686. PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
  687. PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */
  688. PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
  689. PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
  690. PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
  691. /* I2S1 -- largely unused */
  692. PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */
  693. PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */
  694. PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */
  695. PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */
  696. PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
  697. /* DMIC or I2S4 */
  698. /* AVS_DMIC_CLK_A1 */
  699. PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
  700. PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
  701. PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */
  702. PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */
  703. PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
  704. /* I2S2 -- Headset amp */
  705. PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */
  706. PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */
  707. PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */
  708. PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */
  709. PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */
  710. /* I2S3 -- largely unused */
  711. PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */
  712. PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */
  713. PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */
  714. PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */
  715. /* Fast SPI */
  716. PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
  717. PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */
  718. PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
  719. PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */
  720. PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
  721. PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
  722. PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */
  723. PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
  724. PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */
  725. /* SIO_SPI_0 - Used for FP */
  726. PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */
  727. PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */
  728. PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */
  729. PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */
  730. /* SIO_SPI_1 -- largely unused */
  731. PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */
  732. PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */
  733. PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */
  734. /* Headset interrupt */
  735. PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
  736. PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */
  737. /* SIO_SPI_2 -- unused */
  738. PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */
  739. PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */
  740. PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */
  741. PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */
  742. /* WLAN_PE_RST - default to deasserted */
  743. PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */
  744. PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */
  745. /* Debug tracing */
  746. PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
  747. PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
  748. PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
  749. PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */
  750. PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
  751. PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
  752. PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
  753. PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
  754. PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
  755. PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
  756. PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */
  757. PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */
  758. PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */
  759. PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
  760. PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
  761. PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */
  762. PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */
  763. PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */
  764. PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
  765. PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */
  766. PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
  767. PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
  768. PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
  769. PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */
  770. PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */
  771. PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
  772. PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */
  773. PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */
  774. PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
  775. PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */
  776. PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
  777. PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */
  778. PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */
  779. PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
  780. PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */
  781. PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */
  782. PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */
  783. PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */
  784. /* LPSS_UART[0:2] */
  785. PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
  786. /* Next 2 are straps */
  787. PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */
  788. PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */
  789. PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */
  790. PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */
  791. PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */
  792. PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */
  793. PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
  794. PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */
  795. PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
  796. PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */
  797. PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
  798. /* Camera interface -- completely unused */
  799. PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */
  800. PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */
  801. PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */
  802. PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */
  803. PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */
  804. PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */
  805. PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */
  806. PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */
  807. PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */
  808. PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */
  809. PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */
  810. PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
  811. >;
  812. };