mv_ddr_topology.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include "ddr_ml_wrapper.h"
  6. #include "mv_ddr_plat.h"
  7. #include "mv_ddr_topology.h"
  8. #include "mv_ddr_common.h"
  9. #include "mv_ddr_spd.h"
  10. #include "ddr_topology_def.h"
  11. #include "ddr3_training_ip_db.h"
  12. #include "ddr3_training_ip.h"
  13. #include "mv_ddr_training_db.h"
  14. unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
  15. {
  16. unsigned int cl = ceil_div(taa_min, tclk);
  17. return mv_ddr_spd_supported_cl_get(cl);
  18. }
  19. unsigned int mv_ddr_cwl_calc(unsigned int tclk)
  20. {
  21. unsigned int cwl;
  22. if (tclk >= 1250)
  23. cwl = 9;
  24. else if (tclk >= 1071)
  25. cwl = 10;
  26. else if (tclk >= 938)
  27. cwl = 11;
  28. else if (tclk >= 833)
  29. cwl = 12;
  30. else if (tclk >= 750)
  31. cwl = 14;
  32. else if (tclk >= 625)
  33. cwl = 16;
  34. else
  35. cwl = 0;
  36. return cwl;
  37. }
  38. int mv_ddr_topology_map_update(void)
  39. {
  40. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  41. struct if_params *iface_params = &(tm->interface_params[0]);
  42. unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  43. enum mv_ddr_speed_bin speed_bin_index;
  44. enum mv_ddr_freq freq = MV_DDR_FREQ_LAST;
  45. unsigned int tclk;
  46. unsigned char val = 0;
  47. int i;
  48. if (iface_params->memory_freq == MV_DDR_FREQ_SAR)
  49. iface_params->memory_freq = mv_ddr_init_freq_get();
  50. if (tm->cfg_src == MV_DDR_CFG_SPD) {
  51. /* check dram device type */
  52. val = mv_ddr_spd_dev_type_get(&tm->spd_data);
  53. if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
  54. printf("mv_ddr: unsupported dram device type found\n");
  55. return -1;
  56. }
  57. /* update topology map with timing data */
  58. if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
  59. printf("mv_ddr: negative timing data found\n");
  60. return -1;
  61. }
  62. /* update device width in topology map */
  63. iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
  64. /* update die capacity in topology map */
  65. iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
  66. /* update bus bit mask in topology map */
  67. tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
  68. /* update cs bit mask in topology map */
  69. val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
  70. for (i = 0; i < octets_per_if_num; i++)
  71. iface_params->as_bus_params[i].cs_bitmask = val;
  72. /* check dram module type */
  73. val = mv_ddr_spd_module_type_get(&tm->spd_data);
  74. switch (val) {
  75. case MV_DDR_SPD_MODULE_TYPE_UDIMM:
  76. case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
  77. case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
  78. case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
  79. case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
  80. case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
  81. break;
  82. default:
  83. printf("mv_ddr: unsupported dram module type found\n");
  84. return -1;
  85. }
  86. /* update mirror bit mask in topology map */
  87. val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
  88. for (i = 0; i < octets_per_if_num; i++)
  89. iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1;
  90. tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);
  91. /* update cas write latency (cwl) */
  92. val = mv_ddr_cwl_calc(tclk);
  93. if (val == 0) {
  94. printf("mv_ddr: unsupported cas write latency value found\n");
  95. return -1;
  96. }
  97. iface_params->cas_wl = val;
  98. /* update cas latency (cl) */
  99. mv_ddr_spd_supported_cls_calc(&tm->spd_data);
  100. val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
  101. if (val == 0) {
  102. printf("mv_ddr: unsupported cas latency value found\n");
  103. return -1;
  104. }
  105. iface_params->cas_l = val;
  106. } else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
  107. /* set cas and cas-write latencies per speed bin, if they unset */
  108. speed_bin_index = iface_params->speed_bin_index;
  109. freq = iface_params->memory_freq;
  110. if (tm->twin_die_combined == COMBINED) {
  111. iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
  112. iface_params->memory_size -= 1;
  113. }
  114. if (iface_params->cas_l == 0)
  115. iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
  116. if (iface_params->cas_wl == 0)
  117. iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq);
  118. }
  119. return 0;
  120. }
  121. unsigned short mv_ddr_bus_bit_mask_get(void)
  122. {
  123. unsigned short pri_and_ext_bus_width = 0x0;
  124. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  125. unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  126. if (tm->cfg_src == MV_DDR_CFG_SPD) {
  127. if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
  128. tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
  129. enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
  130. enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
  131. switch (pri_bus_width) {
  132. case MV_DDR_PRI_BUS_WIDTH_16:
  133. pri_and_ext_bus_width = BUS_MASK_16BIT;
  134. break;
  135. case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
  136. pri_and_ext_bus_width = BUS_MASK_32BIT;
  137. break;
  138. case MV_DDR_PRI_BUS_WIDTH_64:
  139. pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
  140. break;
  141. default:
  142. pri_and_ext_bus_width = 0x0;
  143. }
  144. if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
  145. pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
  146. }
  147. return pri_and_ext_bus_width;
  148. }
  149. unsigned int mv_ddr_if_bus_width_get(void)
  150. {
  151. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  152. unsigned int bus_width;
  153. switch (tm->bus_act_mask) {
  154. case BUS_MASK_16BIT:
  155. case BUS_MASK_16BIT_ECC:
  156. case BUS_MASK_16BIT_ECC_PUP3:
  157. bus_width = 16;
  158. break;
  159. case BUS_MASK_32BIT:
  160. case BUS_MASK_32BIT_ECC:
  161. case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
  162. bus_width = 32;
  163. break;
  164. case MV_DDR_64BIT_BUS_MASK:
  165. case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
  166. bus_width = 64;
  167. break;
  168. default:
  169. printf("mv_ddr: unsupported bus active mask parameter found\n");
  170. bus_width = 0;
  171. }
  172. return bus_width;
  173. }
  174. unsigned int mv_ddr_cs_num_get(void)
  175. {
  176. unsigned int cs_num = 0;
  177. unsigned int cs, sphy;
  178. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  179. struct if_params *iface_params = &(tm->interface_params[0]);
  180. unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  181. for (sphy = 0; sphy < sphy_max; sphy++) {
  182. VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
  183. break;
  184. }
  185. for (cs = 0; cs < MAX_CS_NUM; cs++) {
  186. VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs);
  187. cs_num++;
  188. }
  189. return cs_num;
  190. }
  191. int mv_ddr_is_ecc_ena(void)
  192. {
  193. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  194. if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
  195. DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
  196. DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
  197. return 1;
  198. else
  199. return 0;
  200. }
  201. int mv_ddr_ck_delay_get(void)
  202. {
  203. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  204. if (tm->ck_delay)
  205. return tm->ck_delay;
  206. return -1;
  207. }
  208. /* translate topology map definition to real memory size in bits */
  209. static unsigned int mem_size[] = {
  210. ADDR_SIZE_512MB,
  211. ADDR_SIZE_1GB,
  212. ADDR_SIZE_2GB,
  213. ADDR_SIZE_4GB,
  214. ADDR_SIZE_8GB,
  215. ADDR_SIZE_16GB
  216. /* TODO: add capacity up to 256GB */
  217. };
  218. unsigned long long mv_ddr_mem_sz_per_cs_get(void)
  219. {
  220. unsigned long long mem_sz_per_cs;
  221. unsigned int i, sphys, sphys_per_dunit;
  222. unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
  223. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  224. struct if_params *iface_params = &(tm->interface_params[0]);
  225. /* calc number of active subphys excl. ecc one */
  226. for (i = 0, sphys = 0; i < sphy_max - 1; i++) {
  227. VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);
  228. sphys++;
  229. }
  230. /* calc number of subphys per ddr unit */
  231. if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT)
  232. sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT;
  233. else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT)
  234. sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT;
  235. else {
  236. printf("mv_ddr: unsupported bus width type found\n");
  237. return 0;
  238. }
  239. /* calc dram size per cs */
  240. mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
  241. (unsigned long long)sphys /
  242. (unsigned long long)sphys_per_dunit;
  243. return mem_sz_per_cs;
  244. }
  245. unsigned long long mv_ddr_mem_sz_get(void)
  246. {
  247. unsigned long long tot_mem_sz = 0;
  248. unsigned long long mem_sz_per_cs = 0;
  249. unsigned long long max_cs = mv_ddr_cs_num_get();
  250. mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get();
  251. tot_mem_sz = max_cs * mem_sz_per_cs;
  252. return tot_mem_sz;
  253. }
  254. unsigned int mv_ddr_rtt_nom_get(void)
  255. {
  256. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  257. unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom;
  258. if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
  259. printf("error: %s: unsupported rtt_nom parameter found\n", __func__);
  260. rtt_nom = PARAM_UNDEFINED;
  261. }
  262. return rtt_nom;
  263. }
  264. unsigned int mv_ddr_rtt_park_get(void)
  265. {
  266. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  267. unsigned int cs_num = mv_ddr_cs_num_get();
  268. unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST;
  269. if (cs_num > 0 && cs_num <= MAX_CS_NUM)
  270. rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
  271. if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
  272. printf("error: %s: unsupported rtt_park parameter found\n", __func__);
  273. rtt_park = PARAM_UNDEFINED;
  274. }
  275. return rtt_park;
  276. }
  277. unsigned int mv_ddr_rtt_wr_get(void)
  278. {
  279. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  280. unsigned int cs_num = mv_ddr_cs_num_get();
  281. unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST;
  282. if (cs_num > 0 && cs_num <= MAX_CS_NUM)
  283. rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
  284. if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
  285. printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
  286. rtt_wr = PARAM_UNDEFINED;
  287. }
  288. return rtt_wr;
  289. }
  290. unsigned int mv_ddr_dic_get(void)
  291. {
  292. struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
  293. unsigned int dic = tm->edata.mem_edata.dic;
  294. if (dic >= MV_DDR_DIC_RZQ_LAST) {
  295. printf("error: %s: unsupported dic parameter found\n", __func__);
  296. dic = PARAM_UNDEFINED;
  297. }
  298. return dic;
  299. }